[Commit-gnuradio] r8475 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-05-21 14:23:23 -0600 (Wed, 21 May 2008)
New Revision: 8475

Modified:
   usrp2/trunk/fpga/sdr_lib/hb_dec.v
Log:
seems to work all the way down to 4 clocks per input.  Needs to work for 2 and 
3 as well, so more work necessary


Modified: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-05-21 19:27:46 UTC (rev 8474)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v   2008-05-21 20:23:23 UTC (rev 8475)
@@ -2,10 +2,10 @@
 // Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B 
0 A]
 // Strobe in cannot come faster than every 2nd clock cycle
 // These taps designed by halfgen4 from ldoolittle
-// myfilt = round(65536 * 2 * halfgen4(.7/4,8))
+// myfilt = round(2^18 * halfgen4(.7/4,8))
 
 module hb_dec
-  #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=20)
+  #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=24)
     (input clk,
      input rst,
      input bypass,
@@ -77,28 +77,29 @@
    assign clear = stb_out_pre[3];
    
    // Data
-   wire [IWIDTH-1:0]   data_odd_a, data_odd_b, data_odd_c, data_odd_d, 
data_even;
-   wire [IWIDTH-1:0]   sum1, sum2;     
-   wire [OWIDTH-1:0]   final_sum;
-   reg [CWIDTH-1:0]    coeff1, coeff2;
-   wire [35:0]                 prod1, prod2;
+   wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d;
+   reg [IWIDTH-1:0]  data_even;
+   wire [IWIDTH-1:0] sum1, sum2;       
+   wire [OWIDTH-1:0] final_sum;
+   reg [CWIDTH-1:0]  coeff1, coeff2;
+   wire [35:0]              prod1, prod2;
 
    always @*            // Outer coeffs
      case(phase_d1)
-       1 : coeff1 = -53;
-       2 : coeff1 = 223;
-       3 : coeff1 = -636;
-       4 : coeff1 = 1480;
-       default : coeff1 = -53;
+       1 : coeff1 = -107;
+       2 : coeff1 = 445;
+       3 : coeff1 = -1271;
+       4 : coeff1 = 2959;
+       default : coeff1 = -107;
      endcase // case(phase)
    
    always @*            //  Inner coeffs
      case(phase_d1)
-       1 : coeff2 = -3053;
-       2 : coeff2 = 5976;
-       3 : coeff2 = -12353;
-       4 : coeff2 = 41179;
-       default : coeff2 = 23456;
+       1 : coeff2 = -6107;
+       2 : coeff2 = 11953;
+       3 : coeff2 = -24706;
+       4 : coeff2 = 82359;
+       default : coeff2 = -6107;
      endcase // case(phase)
    
    srl #(.WIDTH(IWIDTH)) srl_odd_a
@@ -112,28 +113,54 @@
 
    add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1 
(.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
    add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2 
(.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
-   
+
+   wire [IWIDTH-1:0]   data_even_pre;
    srl #(.WIDTH(IWIDTH)) srl_even
-     
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
+     
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even_pre));
 
-   wire [IWIDTH-1:0]   sum_of_prod;
+   always @(posedge clk)
+     if(write_odd)
+       data_even <= data_even_pre;
    
+   localparam          MWIDTH = ACCWIDTH-2;
+   
+   wire [MWIDTH-1:0]   sum_of_prod;
+
    MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1), 
.B(sum1) );
    MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2), 
.B(sum2) );
-   add2_and_round_reg #(.WIDTH(IWIDTH)) add3 
(.clk(clk),.in1(prod1[35:18]),.in2(prod2[35:18]),.sum(sum_of_prod));
+   add2_and_round_reg #(.WIDTH(MWIDTH)) 
+     add3 
(.clk(clk),.in1(prod1[35:36-MWIDTH]),.in2(prod2[35:36-MWIDTH]),.sum(sum_of_prod));
 
    wire [ACCWIDTH-1:0]         acc_out;
    wire [OWIDTH-1:0]   acc_round;
    
-   acc #(.IWIDTH(IWIDTH),.OWIDTH(ACCWIDTH)) 
+   acc #(.IWIDTH(MWIDTH),.OWIDTH(ACCWIDTH)) 
      acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
 
+   /*
    round_reg #(.bits_in(ACCWIDTH),.bits_out(OWIDTH))
      final_round (.clk(clk),.in(acc_out),.out(acc_round));
 
    add2_and_round_reg #(.WIDTH(OWIDTH)) 
      final_adder (.clk(clk), .in1(acc_round), .in2(data_even), 
.sum(final_sum));
+    */
+   localparam          SHIFT_FACTOR = ACCWIDTH-IWIDTH-5;
+   wire [ACCWIDTH-1:0]         data_even_signext, final_sum_unrounded;
 
+   sign_extend #(.bits_in(IWIDTH),.bits_out(ACCWIDTH-SHIFT_FACTOR))
+     signext_data_even 
(.in(data_even),.out(data_even_signext[ACCWIDTH-1:SHIFT_FACTOR]));
+   assign              data_even_signext[SHIFT_FACTOR-1:0] = 0;
+   
+   add2_and_round_reg #(.WIDTH(ACCWIDTH)) 
+     final_adder (.clk(clk), .in1(acc_out), .in2(data_even_signext), 
.sum(final_sum_unrounded));
+   /*
+   round_reg #(.bits_in(ACCWIDTH),.bits_out(OWIDTH))
+     final_round (.clk(clk),.in(final_sum_unrounded),.out(final_sum));
+    */
+   round_reg #(.bits_in(ACCWIDTH-5),.bits_out(OWIDTH))
+     final_round 
(.clk(clk),.in(final_sum_unrounded[ACCWIDTH-6:0]),.out(final_sum));
+
+
    // Output
    always @(posedge clk)
      if(bypass)