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[Commit-gnuradio] r8471 - usrp2/trunk/fpga/sdr_lib
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r8471 - usrp2/trunk/fpga/sdr_lib |
|
Date: |
Wed, 21 May 2008 11:58:16 -0600 (MDT) |
Author: matt
Date: 2008-05-21 11:58:16 -0600 (Wed, 21 May 2008)
New Revision: 8471
Added:
usrp2/trunk/fpga/sdr_lib/HB.sav
usrp2/trunk/fpga/sdr_lib/SMALL_HB.sav
Modified:
usrp2/trunk/fpga/sdr_lib/hb_dec.v
Log:
progress on halfband decimator, plus some sav files for gtkwave
Added: usrp2/trunk/fpga/sdr_lib/HB.sav
===================================================================
--- usrp2/trunk/fpga/sdr_lib/HB.sav (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/HB.sav 2008-05-21 17:58:16 UTC (rev 8471)
@@ -0,0 +1,55 @@
+[size] 1400 967
+[pos] -1 -1
+*-44.529663 5615000000000000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1 -1 -1 -1
+[treeopen] hb_dec_tb.
+[treeopen] hb_dec_tb.uut.
address@hidden
+hb_dec_tb.data_in[17:0]
address@hidden
+hb_dec_tb.strobe_in
+hb_dec_tb.strobe_out
+hb_dec_tb.uut.write_even
address@hidden
+hb_dec_tb.uut.addr_even[3:0]
address@hidden
+hb_dec_tb.uut.data_even[17:0]
address@hidden
+hb_dec_tb.uut.addr_odd_a[3:0]
+hb_dec_tb.uut.addr_odd_b[3:0]
+hb_dec_tb.uut.addr_odd_c[3:0]
+hb_dec_tb.uut.addr_odd_d[3:0]
address@hidden
+hb_dec_tb.uut.data_odd_a[17:0]
+hb_dec_tb.uut.data_odd_b[17:0]
+hb_dec_tb.uut.data_odd_c[17:0]
+hb_dec_tb.uut.data_odd_d[17:0]
address@hidden
+hb_dec_tb.uut.write_odd
address@hidden
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+hb_dec_tb.uut.sum_of_prod[17:0]
+hb_dec_tb.uut.acc_out[19:0]
+hb_dec_tb.uut.acc_round[17:0]
address@hidden
+hb_dec_tb.uut.phase[2:0]
address@hidden
+hb_dec_tb.uut.stb_in
+hb_dec_tb.uut.stb_out
address@hidden
+hb_dec_tb.uut.sum2[17:0]
+hb_dec_tb.uut.stb_out_pre[15:0]
address@hidden
+hb_dec_tb.uut.do_acc
+hb_dec_tb.uut.clear
address@hidden
+hb_dec_tb.uut.sum1[17:0]
+hb_dec_tb.uut.coeff1[17:0]
+hb_dec_tb.uut.prod1[35:0]
+hb_dec_tb.uut.prod2[35:0]
+hb_dec_tb.uut.sum_of_prod[17:0]
+hb_dec_tb.uut.acc_out[19:0]
+hb_dec_tb.uut.acc_round[17:0]
+hb_dec_tb.uut.final_sum[17:0]
+hb_dec_tb.data_out[17:0]
+hb_dec_tb.uut.coeff2[17:0]
Added: usrp2/trunk/fpga/sdr_lib/SMALL_HB.sav
===================================================================
--- usrp2/trunk/fpga/sdr_lib/SMALL_HB.sav (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/SMALL_HB.sav 2008-05-21 17:58:16 UTC (rev
8471)
@@ -0,0 +1,40 @@
+[size] 1400 967
+[pos] -1 -1
+*-11.608687 1834 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1
+[treeopen] small_hb_dec_tb.
+[treeopen] small_hb_dec_tb.uut.
address@hidden
+small_hb_dec_tb.uut.clk
+small_hb_dec_tb.uut.phase
address@hidden
+small_hb_dec_tb.uut.data_in[17:0]
address@hidden
+small_hb_dec_tb.uut.d1[17:0]
+small_hb_dec_tb.uut.d2[17:0]
+small_hb_dec_tb.uut.d3[17:0]
+small_hb_dec_tb.uut.d4[17:0]
+small_hb_dec_tb.uut.d5[17:0]
+small_hb_dec_tb.uut.d6[17:0]
+small_hb_dec_tb.uut.coeff[17:0]
+small_hb_dec_tb.uut.sum[17:0]
+small_hb_dec_tb.uut.prod[35:0]
+small_hb_dec_tb.uut.accum_rnd[17:0]
address@hidden
+small_hb_dec_tb.uut.stb_in
address@hidden
+small_hb_dec_tb.uut.final_sum[17:0]
address@hidden
+small_hb_dec_tb.uut.go
+small_hb_dec_tb.uut.go_d1
+small_hb_dec_tb.uut.go_d2
+small_hb_dec_tb.uut.go_d3
+small_hb_dec_tb.uut.go_d4
+small_hb_dec_tb.uut.stb_out
address@hidden
+small_hb_dec_tb.uut.data_out[17:0]
+small_hb_dec_tb.uut.prod[35:0]
+small_hb_dec_tb.uut.accum_rnd[17:0]
+small_hb_dec_tb.uut.final_sum[17:0]
address@hidden
+small_hb_dec_tb.uut.round_acc.out[17:0]
+small_hb_dec_tb.uut.data_out[17:0]
Modified: usrp2/trunk/fpga/sdr_lib/hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/hb_dec.v 2008-05-21 16:59:27 UTC (rev 8470)
+++ usrp2/trunk/fpga/sdr_lib/hb_dec.v 2008-05-21 17:58:16 UTC (rev 8471)
@@ -2,141 +2,151 @@
// Implements impulse responses of the form [A 0 B 0 C .. 0 H 0.5 H 0 .. C 0 B
0 A]
// Strobe in cannot come faster than every 2nd clock cycle
// These taps designed by halfgen4 from ldoolittle
+// myfilt = round(65536 * 2 * halfgen4(.7/4,8))
module hb_dec
- #(parameter WIDTH=18)
+ #(parameter IWIDTH=18, OWIDTH=18, CWIDTH=18, ACCWIDTH=20)
(input clk,
input rst,
input bypass,
input stb_in,
- input [WIDTH-1:0] data_in,
+ input [IWIDTH-1:0] data_in,
output reg stb_out,
- output [WIDTH-1:0] data_out);
+ output reg [OWIDTH-1:0] data_out);
+ // Control
reg [3:0] addr_odd_a, addr_odd_b, addr_odd_c, addr_odd_d,
addr_even;
- wire [WIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d,
data_even;
- wire [WIDTH-1:0] sum1, sum2;
- reg [WIDTH-1:0] final_sum;
- reg [WIDTH-1:0] coeff1, coeff2;
-
- wire [2:0] coeff_addr;
- wire [35:0] prod1, prod2;
-
- wire write_odd, write_even;
- reg odd_even;
- reg [2:0] phase;
+ wire write_odd, write_even, do_mult;
+ reg odd;
+ reg [2:0] phase, phase_d1;
+ reg stb_out_int;
+ wire clear, do_acc;
+ assign do_mult = 1;
always @(posedge clk)
if(rst)
- odd_even <= 0;
+ odd <= 0;
else if(stb_in)
- odd_even <= ~odd_even;
+ odd <= ~odd;
- assign write_odd = stb_in & odd_even;
- assign write_even = stb_in & ~odd_even;
+ assign write_odd = stb_in & odd;
+ assign write_even = stb_in & ~odd;
always @(posedge clk)
if(rst)
phase <= 0;
- else if(stb_in & odd_even)
+ else if(stb_in & odd)
phase <= 1;
else if(phase == 4)
phase <= 0;
else if(phase != 0)
phase <= phase + 1;
- assign coeff_addr = phase;
+ always @(posedge clk)
+ phase_d1 <= phase;
+
+ reg [15:0] stb_out_pre;
+ always @(posedge clk)
+ if(rst)
+ stb_out_pre <= 0;
+ else
+ stb_out_pre <= {stb_out_pre[14:0],(stb_in & odd)};
- always @*
- case(phase)
- 1 : addr_odd_a = 1;
- 2 : addr_odd_a = 7;
- 3 : addr_odd_a = 9;
- 4 : addr_odd_a = 15;
- default : addr_odd_a = 3;
- endcase // case(phase)
+ always @(posedge clk)
+ addr_even <= 7;
always @*
case(phase)
- 1 : addr_odd_b = 1;
- 2 : addr_odd_b = 7;
- 3 : addr_odd_b = 9;
- 4 : addr_odd_b = 15;
- default : addr_odd_b = 3;
+ 1 : begin addr_odd_a = 0; addr_odd_b = 15; end
+ 2 : begin addr_odd_a = 1; addr_odd_b = 14; end
+ 3 : begin addr_odd_a = 2; addr_odd_b = 13; end
+ 4 : begin addr_odd_a = 3; addr_odd_b = 12; end
+ default : begin addr_odd_a = 0; addr_odd_b = 15; end
endcase // case(phase)
-
+
always @*
case(phase)
- 1 : addr_odd_c = 4;
- 2 : addr_odd_c = 5;
- 3 : addr_odd_c = 6;
- 4 : addr_odd_c = 15;
- default : addr_odd_c = 3;
+ 1 : begin addr_odd_c = 4; addr_odd_d = 11; end
+ 2 : begin addr_odd_c = 5; addr_odd_d = 10; end
+ 3 : begin addr_odd_c = 6; addr_odd_d = 9; end
+ 4 : begin addr_odd_c = 7; addr_odd_d = 8; end
+ default : begin addr_odd_c = 4; addr_odd_d = 11; end
endcase // case(phase)
+
+ assign do_acc = |stb_out_pre[6:3];
+ assign clear = stb_out_pre[3];
- always @*
- case(phase)
- 1 : addr_odd_d = 2;
- 2 : addr_odd_d = 3;
- 3 : addr_odd_d = 5;
- 4 : addr_odd_d = 5;
- default : addr_odd_d = 3;
+ // Data
+ wire [IWIDTH-1:0] data_odd_a, data_odd_b, data_odd_c, data_odd_d,
data_even;
+ wire [IWIDTH-1:0] sum1, sum2;
+ wire [OWIDTH-1:0] final_sum;
+ reg [CWIDTH-1:0] coeff1, coeff2;
+ wire [35:0] prod1, prod2;
+
+ always @* // Outer coeffs
+ case(phase_d1)
+ 1 : coeff1 = -53;
+ 2 : coeff1 = 223;
+ 3 : coeff1 = -636;
+ 4 : coeff1 = 1480;
+ default : coeff1 = -53;
endcase // case(phase)
- always @*
- case(coeff_addr)
- 0 : coeff1 = 12345;
- 1 : coeff1 = 1235;
- 2 : coeff1 = 3456;
- 3 : coeff1 = 345;
- 3 : coeff1 = 345;
- default : coeff1 = 23456;
- endcase // case(coeff_addr)
-
- always @*
- case(coeff_addr)
- 0 : coeff2 = 12345;
- 1 : coeff2 = 12;
- 2 : coeff2 = 356;
- 3 : coeff2 = 45;
+ always @* // Inner coeffs
+ case(phase_d1)
+ 1 : coeff2 = -3053;
+ 2 : coeff2 = 5976;
+ 3 : coeff2 = -12353;
+ 4 : coeff2 = 41179;
default : coeff2 = 23456;
- endcase // case(coeff_addr)
+ endcase // case(phase)
- srl #(.WIDTH(18)) srl_odd_a
+ srl #(.WIDTH(IWIDTH)) srl_odd_a
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_a),.out(data_odd_a));
- srl #(.WIDTH(18)) srl_odd_b
+ srl #(.WIDTH(IWIDTH)) srl_odd_b
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_b),.out(data_odd_b));
- srl #(.WIDTH(18)) srl_odd_c
+ srl #(.WIDTH(IWIDTH)) srl_odd_c
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_c),.out(data_odd_c));
- srl #(.WIDTH(18)) srl_odd_d
+ srl #(.WIDTH(IWIDTH)) srl_odd_d
(.clk(clk),.write(write_odd),.in(data_in),.addr(addr_odd_d),.out(data_odd_d));
- add2_and_round_reg #(.WIDTH(18)) add1
(.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
- add2_and_round_reg #(.WIDTH(18)) add2
(.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
+ add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add1
(.clk(clk),.in1(data_odd_a),.in2(data_odd_b),.sum(sum1));
+ add2_reg /*_and_round_reg*/ #(.WIDTH(IWIDTH)) add2
(.clk(clk),.in1(data_odd_c),.in2(data_odd_d),.sum(sum2));
- srl #(.WIDTH(18)) srl_even
+ srl #(.WIDTH(IWIDTH)) srl_even
(.clk(clk),.write(write_even),.in(data_in),.addr(addr_even),.out(data_even));
- wire [17:0] final_sum_unreg;
+ wire [IWIDTH-1:0] sum_of_prod;
+ MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1),
.B(sum1) );
+ MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2),
.B(sum2) );
+ add2_and_round_reg #(.WIDTH(IWIDTH)) add3
(.clk(clk),.in1(prod1[35:18]),.in2(prod2[35:18]),.sum(sum_of_prod));
+
+ wire [ACCWIDTH-1:0] acc_out;
+ wire [OWIDTH-1:0] acc_round;
+
+ acc #(.IWIDTH(IWIDTH),.OWIDTH(ACCWIDTH))
+ acc (.clk(clk),.clear(clear),.acc(do_acc),.in(sum_of_prod),.out(acc_out));
+
+ round_reg #(.bits_in(ACCWIDTH),.bits_out(OWIDTH))
+ final_round (.clk(clk),.in(acc_out),.out(acc_round));
+
+ add2_and_round_reg #(.WIDTH(OWIDTH))
+ final_adder (.clk(clk), .in1(acc_round), .in2(data_even),
.sum(final_sum));
+
+ // Output
always @(posedge clk)
if(bypass)
- final_sum <= data_in;
- else
- final_sum <= final_sum_unreg;
+ data_out <= data_in;
+ else if(stb_out_pre[9])
+ data_out <= final_sum;
- assign data_out = final_sum;
-
always @(posedge clk)
if(rst)
stb_out <= 0;
else if(bypass)
stb_out <= stb_in;
else
- stb_out <= 0;
+ stb_out <= stb_out_pre[9];
- MULT18X18S mult1(.C(clk), .CE(do_mult), .R(rst), .P(prod1), .A(coeff1),
.B(sum1) );
- MULT18X18S mult2(.C(clk), .CE(do_mult), .R(rst), .P(prod2), .A(coeff2),
.B(sum2) );
- add2_and_round_reg #(.WIDTH(18)) add3
(.clk(clk),.in1(prod1[35:18]),.in2(prod2[35:18]),.sum(final_sum_unreg));
-
endmodule // hb_dec
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