[Commit-gnuradio] r8467 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-05-20 16:07:37 -0600 (Tue, 20 May 2008)
New Revision: 8467

Modified:
   usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
Log:
extra stage of delay at the front for timing purposes


Modified: usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_dec.v     2008-05-20 18:56:10 UTC (rev 
8466)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_dec.v     2008-05-20 22:07:37 UTC (rev 
8467)
@@ -13,14 +13,19 @@
      output reg stb_out,
      output [WIDTH-1:0] data_out);
 
+   reg                         stb_in_d1;
+   reg [WIDTH-1:0]     data_in_d1;
+   always @(posedge clk) stb_in_d1 <= stb_in;
+   always @(posedge clk) data_in_d1 <= data_in;
+   
    wire                go;
    reg                         phase, go_d1, go_d2, go_d3, go_d4;
    always @(posedge clk)
      if(rst)
        phase <= 0;
-     else if(stb_in)
+     else if(stb_in_d1)
        phase <= ~phase;
-   assign              go = stb_in & phase;
+   assign              go = stb_in_d1 & phase;
    always @(posedge clk) go_d1 <= go;
    always @(posedge clk) go_d2 <= go_d1;
    always @(posedge clk) go_d3 <= go_d2;
@@ -31,9 +36,9 @@
    
    reg [WIDTH-1:0]     d1, d2, d3, d4 , d5, d6;
    always @(posedge clk)
-     if(stb_in | rst)
+     if(stb_in_d1 | rst)
        begin
-         d1 <= data_in;
+         d1 <= data_in_d1;
          d2 <= d1;
          d3 <= d2;
          d4 <= d3;
@@ -45,7 +50,7 @@
    always @(posedge clk)
      if(go)
        begin
-         sum_a <= data_in + d6;
+         sum_a <= data_in_d1 + d6;
          sum_b <= d2 + d4;
          middle <= d3;
        end
@@ -74,7 +79,7 @@
    reg [17:0]   final_sum;
    always @(posedge clk)
      if(bypass)
-       final_sum <= data_in;
+       final_sum <= data_in_d1;
      else if(go_d4)
        final_sum <= accum_rnd;
 
@@ -84,7 +89,7 @@
      if(rst)
        stb_out <= 0;
      else if(bypass)
-       stb_out <= stb_in;
+       stb_out <= stb_in_d1;
      else
        stb_out <= go_d4;
 endmodule // small_hb_dec