[Commit-gnuradio] r8465 - usrp2/trunk/fpga/top/u2_core

[matt]

Author: matt
Date: 2008-05-20 12:48:42 -0600 (Tue, 20 May 2008)
New Revision: 8465

Modified:
   usrp2/trunk/fpga/top/u2_core/u2_core.v
Log:
register run_rx to reduce fanout, remove adc delay regs (they are now in 
u2_rev2, and weren't used here anyway)


Modified: usrp2/trunk/fpga/top/u2_core/u2_core.v
===================================================================
--- usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-05-20 18:19:23 UTC (rev 
8464)
+++ usrp2/trunk/fpga/top/u2_core/u2_core.v      2008-05-20 18:48:42 UTC (rev 
8465)
@@ -480,11 +480,15 @@
    // ATR Controller, Slave #11
 
    wire         run_rx, run_tx;
+   reg                  run_rx_d1;
+   always @(posedge dsp_clk)
+     run_rx_d1 <= run_rx;
+   
    atr_controller atr_controller
      (.clk_i(wb_clk),.rst_i(wb_rst),
       .adr_i(s11_adr[5:0]),.sel_i(s11_sel),.dat_i(s11_dat_o),.dat_o(s11_dat_i),
       .we_i(s11_we),.stb_i(s11_stb),.cyc_i(s11_cyc),.ack_o(s11_ack),
-      .run_rx(run_rx),.run_tx(run_tx),.ctrl_lines(atr_lines) );
+      .run_rx(run_rx_d1),.run_tx(run_tx),.ctrl_lines(atr_lines) );
    assign       s11_err = 0;
    assign       s11_rty = 0;
    
@@ -503,24 +507,8 @@
    
    // /////////////////////////////////////////////////////////////////////////
    // DSP
-
-   reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
-   reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;
-
    wire [31:0]          sample_rx, sample_tx;
    wire         strobe_rx, strobe_tx;
-   
-   always @(posedge dsp_clk)
-     begin
-       adc_a_reg1 <= adc_a;
-       adc_a_reg2 <= adc_a_reg1;
-       adc_b_reg1 <= adc_b;
-       adc_b_reg2 <= adc_b_reg1;
-       adc_ovf_a_reg1 <= adc_ovf_a;
-       adc_ovf_a_reg2 <= adc_ovf_a_reg1;
-       adc_ovf_b_reg1 <= adc_ovf_b;
-       adc_ovf_b_reg2 <= adc_ovf_b_reg1;
-     end // always @ (posedge dsp_clk)
 
    rx_control #(.FIFOSIZE(10)) rx_control
      (.clk(dsp_clk), .rst(dsp_rst),
@@ -536,7 +524,7 @@
      (.clk(dsp_clk),.rst(dsp_rst),
       .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
       .adc_a(adc_a),.adc_ovf_a(adc_ovf_a),.adc_b(adc_b),.adc_ovf_b(adc_ovf_b),
-      .sample(sample_rx), .run(run_rx), .strobe(strobe_rx) );
+      .sample(sample_rx), .run(run_rx_d1), .strobe(strobe_rx) );
 
    tx_control #(.FIFOSIZE(10)) tx_control
      (.clk(dsp_clk), .rst(dsp_rst),
@@ -585,7 +573,8 @@
    // 
/////////////////////////////////////////////////////////////////////////////////////////
    // Debug Pins
 
-   // Assign various commonly used debug buses.  Try to always have uart_tx_o 
on highest bit
+   // Assign various commonly used debug buses.
+   /*
    wire [31:0] debug_rx_1 = 
{uart_tx_o,GMII_TX_EN,strobe_rx,overrun,proc_int,buffer_int,timer_int,GMII_RX_DV,
                             irq[7:0],
                             GMII_RXD,
@@ -608,7 +597,6 @@
                {8'd0},
                
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
 
-      /*
    assign      debug_serdes0 = { { rd0_dat[7:0] },
                                 { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, 
rd0_eop, rd0_read, rd0_error, rd0_done },
                                 { ser_t[15:8] },
@@ -636,8 +624,8 @@
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    
-   assign      debug = debug_serdes0; //_common;
+   assign      debug = 32'b0; 
    assign      debug_gpio_0 = 32'b0;
-   assign      debug_gpio_1 = debug_serdes1[31:0];
+   assign      debug_gpio_1 = 32'b0; 
    
 endmodule // u2_core