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[Commit-gnuradio] r8431 - in gnuradio/branches/developers/gnychis/fpga/u
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From: |
gnychis |
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Subject: |
[Commit-gnuradio] r8431 - in gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib: . testbenches |
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Date: |
Thu, 15 May 2008 11:51:06 -0600 (MDT) |
Author: gnychis
Date: 2008-05-15 11:51:05 -0600 (Thu, 15 May 2008)
New Revision: 8431
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/4packets.dat
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_1_channel.dat
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_2_channels.dat
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/chan_fifo_readers_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/channel_ram_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/data_packet_fifo_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_tx_chain.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/full_chip.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/packets.dat
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_chains.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_fake_fx2.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/strobe_gen_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx.mpf
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx_buffer_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_reader_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_writer_test.v
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_packet_fifo_test.v
Log:
adding in testbench material
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/4packets.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/4packets.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_1_channel.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_1_channel.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_2_channels.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/all_valid_packet_lengths_2_channels.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/chan_fifo_readers_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/chan_fifo_readers_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/chan_fifo_readers_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,136 @@
+module chan_fifo_readers_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [31:0] datain;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg WR_done;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire underrun;
+
+reg [15:0] i ;
+
+// fifo inputs
+wire skip;
+wire rdreq;
+
+// fifo ouputs
+wire [31:0] fifodata;
+wire pkt_waiting;
+wire tx_strobe;
+wire tx_empty;
+
+chan_fifo_reader chan0 (
+ .reset(reset),
+ .tx_clock(txclock),
+ .adc_time(ttime),
+ .skip(skip),
+ .rdreq(rdreq),
+ .pkt_waiting(pkt_waiting),
+ .fifodata(fifodata),
+ //.debug(debug),
+ .tx_q(tx_q),
+ .tx_i(tx_i),
+ .underrun(underrun),
+ .samples_format(4'd0),
+ .tx_empty(tx_empty),
+ .tx_strobe(tx_strobe) );
+
+
+// Channel fifo
+ channel_ram tx_data_fifo
+ ( .reset(reset),
+ .txclk(txclock),
+ .datain(datain),
+ .WR(WR),
+ .have_space(),
+ .dataout(fifodata),
+ .packet_waiting(pkt_waiting),
+ .RD(rdreq),
+ .WR_done(WR_done),
+ .RD_done(skip)
+ );
+
+ strobe_gen strobe_generator(
+ .reset(reset),
+ .enable(1'b1),
+ .clock(txclock),
+ .strobe_in(1'b1),
+ .strobe(tx_strobe),
+ .rate(8'd3) );
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ adcclock = 0;
+ txclock = 0;
+ datain = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ WR_done = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ send_packet(128, 16'd0, 32'hFFFFFFFF);
+ send_packet(3, 16'd0, 32'hFFFFFFFF);
+ send_packet(50, 16'd0, 32'hFFFFFFFF);
+ send_packet(100, 16'd0, 32'hFFFFFFFF);
+
+
+ end
+
+always@(posedge adcclock) begin
+ ttime <= ttime + 1;
+end
+
+always
+ #5 txclock = ~txclock ;
+
+always
+ #6 adcclock = ~adcclock ;
+
+task send_packet;
+ input [8:0]length;
+ input [15:0] channel;
+ input [31:0] timestamp;
+ begin
+ repeat (length) begin
+ @(posedge txclock)
+ WR = 1;
+ if (i == 0) datain = {channel, 7'd0,4*length - 8};
+ else if (i == 1) datain = timestamp;
+ else datain = i;//{16'hFFFF - i,i};
+ i = i + 1;
+ end
+
+ if (length < 128)
+ begin
+ @(posedge txclock)
+ WR_done = 1;
+ WR = 0;
+ @(posedge txclock)
+ WR_done = 0;
+ end
+ else
+ @(posedge txclock)
+ WR = 0;
+
+ i = 0;
+ end
+ endtask
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/chan_fifo_readers_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/channel_ram_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/channel_ram_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/channel_ram_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,105 @@
+module channel_ram_test();
+
+reg txclk, reset, WR, WR_done, RD, RD_done;
+reg [31:0] datain;
+wire [31:0] dataout;
+
+wire have_space;
+wire packet_waiting;
+
+
+reg [8:0] i;
+
+channel_ram ram
+ (
+ //System
+ .txclk(txclk),
+ .reset(reset),
+ // USB side
+ .datain(datain),
+ .WR(WR),
+ .WR_done(WR_done),
+ .have_space(have_space),
+ // Reader side
+ .dataout(dataout),
+ .RD(RD),
+ .RD_done(RD_done),
+ .packet_waiting(packet_waiting));
+
+ initial begin
+ reset = 1;
+ txclk = 0;
+ WR = 0;
+ WR_done = 0;
+ RD = 0;
+ RD_done = 0;
+ datain = 0;
+ i = 0;
+
+ #40 reset = 0;
+
+ send_packet(20);
+ send_packet(128);
+ send_packet(30);
+ send_packet(128);
+
+ read_packet(10);
+ read_packet(128);
+ read_packet(20);
+ read_packet(128);
+
+ end
+
+ always
+ #2 txclk = ~txclk;
+
+ task send_packet;
+ input [8:0]length;
+ begin
+ repeat (length) begin
+ @(posedge txclk)
+ WR = 1;
+ datain = i;
+ i = i + 1;
+ end
+
+ if (length < 128)
+ begin
+ @(posedge txclk)
+ WR_done = 1;
+ WR = 0;
+ @(posedge txclk)
+ WR_done = 0;
+ end
+ else
+ @(posedge txclk)
+ WR = 0;
+ end
+ endtask
+
+ task read_packet;
+ input [8:0]length;
+ begin
+ repeat (length) begin
+ @(posedge txclk)
+ RD = 1;
+ end
+ if (length < 128)
+ begin
+ @(posedge txclk)
+ RD_done = 1;
+ RD <= 0;
+ @(posedge txclk)
+ RD_done = 0;
+ end
+ else
+ @(posedge txclk)
+ RD = 0;
+ end
+ endtask
+
+ always @(posedge txclk)
+ if (RD)
+ $display(dataout);
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/channel_ram_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/data_packet_fifo_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/data_packet_fifo_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/data_packet_fifo_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,209 @@
+module data_packet_fifo_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [31:0] data_bus;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg pkt_complete;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire overrun;
+wire underrun;
+
+reg [15:0] i ;
+
+// fifo inputs
+reg skip;
+reg rdreq;
+
+// fifo ouputs
+wire [31:0] fifodata;
+wire pkt_waiting;
+wire tx_strobe;
+
+// Channel fifo
+ data_packet_fifo tx_data_fifo
+ ( .reset(reset),
+ .clock(txclock),
+ .ram_data_in(data_bus),
+ .write_enable(WR),
+ .ram_data_out(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .read_enable(rdreq),
+ .pkt_complete(pkt_complete),
+ .skip_packet(skip),
+ .have_space()
+ );
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ txclock = 0;
+ data_bus = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ pkt_complete = 0;
+ rdreq = 0;
+ skip = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (20) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+ // Payload len
+ if (i == 0)
+ data_bus = 32;
+ // First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1000;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+ @(posedge txclock)
+ WR <= 0;
+ @(posedge txclock)
+ WR <= 0;
+
+ repeat (12) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+
+ repeat (128) begin
+ @(posedge txclock)
+ WR = 1'b1 ;
+
+ //Payload len
+ if (i == 0)
+ data_bus = 16;
+ //First 16 bits of timestamp
+ else if (i == 1)
+ data_bus = 1600;
+ else
+ data_bus = i ;
+ i = i + 1 ;
+ end
+
+ WR <= 0;
+ i <= 0;
+ pkt_complete <= 1;
+ @(posedge txclock)
+ pkt_complete <= 0;
+
+ @(posedge txclock)
+ WR = 1'b0 ;
+ @(posedge txclock)
+ WR = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b1 ;
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b1 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+ @(posedge txclock)
+ skip = 1'b0 ;
+
+
+ repeat (128) begin
+ @(posedge txclock)
+ rdreq = 1;
+ end
+ @(posedge txclock)
+ rdreq = 1'b0 ;
+ end
+
+always
+ #5 txclock = ~txclock ;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/data_packet_fifo_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,153 @@
+module fake_fx2();
+
+integer file, start, count, r;
+
+reg [7:0] packet [0:511];
+reg usbclock;
+reg txclock;
+reg reset;
+reg bus_reset;
+reg [7:0] i;
+reg [15:0] usbdata;
+reg WR;
+
+wire have_space;
+wire txstrobe;
+wire tx_empty;
+wire tx_underrun;
+wire [15:0]tx_i_0;
+wire [15:0]tx_q_0;
+wire [15:0]tx_i_1;
+wire [15:0]tx_q_1;
+wire [15:0]tx_i_2;
+wire [15:0]tx_q_2;
+wire [15:0]tx_i_3;
+wire [15:0]tx_q_3;
+wire ok;
+wire rx_WR;
+wire [15:0]rx_databus;
+
+
+/* NOT USED YET */
+reg clear_status;
+reg channels;
+
+tx_buffer_inband tx_buffer_inband_ (
+ .usbclk(usbclock),
+ .reset(reset),
+ .usbdata(usbdata),
+ .WR(WR),
+ .txclk(txclock),
+ .txstrobe(txstrobe),
+ .tx_empty(tx_empty),
+ .have_space(have_space),
+ .tx_underrun(tx_underrun),
+ .tx_i_0(tx_i_0),
+ .tx_i_1(tx_i_1),
+ .tx_i_2(tx_i_2),
+ .tx_i_3(tx_i_3),
+ .tx_q_0(tx_q_0),
+ .tx_q_1(tx_q_1),
+ .tx_q_2(tx_q_2),
+ .tx_q_3(tx_q_3),
+ .bus_reset(bus_reset),
+ .clear_status(1'b0),
+ .channels(4'b0),
+ .debugbus(),
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus)
+);
+
+strobe_gen strobe_gen_test(
+ .clock(txclock),
+ .reset(reset),
+ .enable(1'd1),
+ .rate(8'd6),
+ .strobe_in(1'd1),
+ .strobe(txstrobe) );
+
+
+fake_tx_chain tx_chain(
+ .reset(reset),
+ .tx_empty(tx_empty),
+ .txstrobe(txstrobe),
+ .tx_q(tx_q_0),
+ .tx_i(tx_i_0),
+ .ok(ok)
+ );
+
+initial begin
+ file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ //file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
+ start = 0;
+ count = 0;
+ usbclock = 0;
+ txclock = 0;
+ WR = 0;
+ reset = 1;
+ bus_reset = 1;
+ i = 0;
+
+ clear_status = 0;
+ channels = 0;
+
+ #400 reset = 0;
+ bus_reset = 0;
+
+ if (file == 0)
+ begin
+ $display("cannot open specified file");
+ $finish;
+ end
+
+ while($feof(file) == 0)
+ begin
+ i = 0;
+
+ r = $fread(packet, file);
+ if (r != 512)
+ begin
+ $display("error while reading packets.dat");
+ //$finish;
+ end
+ else if (r == 0)
+ begin
+ $display("Done reading packets.dat");
+ $finish;
+ end
+ else if (r == 512)
+ begin
+ // Wait
+ i = 0;
+ while(have_space == 0)
+ begin
+ @(posedge usbclock)
+ i = 0;
+ end
+
+ repeat (256) begin
+ @(posedge usbclock)
+ WR = 1;
+ usbdata = {packet[2*i+1],packet[2*i]};
+ i = i + 1 ;
+ end
+ // Reproduce FX2 Bug
+ @(posedge usbclock)
+ WR = 1;
+ @(posedge usbclock)
+ WR = 0;
+ /*@(posedge usbclock)
+ WR = 0;*/
+ end
+ end
+
+ $display("Closing file...");
+ $fclose(file);
+end
+
+always
+ #64 usbclock = ~ usbclock;
+always
+ #48 txclock = ~ txclock;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,22 @@
+module fake_fx2_test(
+ input [15:0] usbdata,
+ input usbclk,
+ input WR,
+ input reset,
+ output reg have_space
+ );
+
+reg[15:0] fakefifo;
+
+always @(posedge usbclk) begin
+ if (reset)
+ have_space <= 0;
+ else if (WR == 1)
+ fakefifo <= usbdata;
+
+end
+
+always
+ #200 have_space <= ~have_space;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_fx2_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_tx_chain.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_tx_chain.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_tx_chain.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,43 @@
+module fake_tx_chain
+ ( reset, tx_empty, txstrobe, tx_q, tx_i, ok);
+
+ input wire reset ;
+ input wire tx_empty ;
+ input wire txstrobe ;
+ input wire [15:0] tx_q ;
+ input wire [15:0] tx_i ;
+ output reg ok ;
+
+ reg [15:0] counter ;
+
+ always @(reset)
+ begin
+ if (reset)
+ begin
+ ok = 1 ;
+ counter = 0 ;
+ end
+ end
+
+ always @(posedge txstrobe)
+ begin
+ if (tx_empty == 0)
+ begin
+ if (tx_i != counter)
+ begin
+ ok = 0 ;
+ $display("Q samples do not match");
+ //$finish;
+ end
+ if (tx_q != counter + 1)
+ begin
+ ok = 0 ;
+ $display("I samples do not match");
+ //$finish;
+ end
+
+ counter = counter + 2 ;
+ end
+ end
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/fake_tx_chain.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/full_chip.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/full_chip.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/full_chip.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,134 @@
+module full_chip();
+
+integer file, start, count, r;
+reg [7:0] packet [0:511];
+reg [7:0] i;
+
+reg master_clk;
+reg SLCK;
+reg SDI;
+reg SDO;
+reg SEN_FPGA;
+
+
+wire [13:0]tx_a;
+reg usbclk;
+
+wire clear_status = 0;
+
+reg WR, RD, OE;
+reg [15:0]usbdata;
+
+wire have_pkt_ready;
+wire have_space;
+
+wire [15:0]usbdata2;
+wire SDO2;
+
+assign usbdata2 = usbdata;
+assign SDO2 = SDO;
+
+usrp_inband_usb dut (
+ .MYSTERY_SIGNAL(),
+ .master_clk(master_clk),
+ .SCLK(1'b0),
+ .SDI(1'b0),
+ .SDO(SD02),
+ .SEN_FPGA(1'b0),
+
+ .FX2_1(clear_status),
+ .FX2_2(rx_overrun),
+ .FX2_3(tx_underrun),
+
+ .rx_a_a(),
+ .rx_b_a(),
+ .rx_a_b(),
+ .rx_b_b(),
+ .tx_a(tx_a),
+ .tx_b(),
+
+ .TXSYNC_A(),
+ .TXSYNC_B(),
+
+ .usbclk(usbclk),
+ .usbctl({OE, RD, WR}),
+ .usbrdy({have_pkt_rdy, have_space}),
+ .usbdata(usbdata2), // NB Careful, inout
+
+ .io_tx_a(),
+ .io_tx_b(),
+ .io_rx_a(),
+ .io_rx_b()
+ );
+
+
+
+initial begin
+ //file = $fopen("all_valid_packet_lengths_2_channels.dat", "rb");
+ file = $fopen("all_valid_packet_lengths_1_channel.dat", "rb");
+ start = 0;
+ count = 0;
+ usbclk = 0;
+ master_clk = 0;
+ WR = 0;
+ RD = 0;
+ OE = 0;
+ SDO = 2;
+ i = 0;
+
+ #40 i = 0;
+
+ if (file == 0)
+ begin
+ $display("cannot open specified file");
+ $finish;
+ end
+
+ while($feof(file) == 0)
+ begin
+ i = 0;
+
+ r = $fread(packet, file);
+ if (r != 512)
+ begin
+ $display("error while reading packets.dat");
+ //$finish;
+ end
+ else if (r == 0)
+ begin
+ $display("Done reading packets.dat");
+ $finish;
+ end
+ else if (r == 512)
+ begin
+ // Wait
+ i = 0;
+ while(have_space == 0)
+ begin
+ @(posedge usbclk)
+ i = 0;
+ end
+
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1;
+ usbdata = {packet[2*i+1],packet[2*i]};
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 0;
+ /*@(posedge usbclk)
+ WR = 0;*/
+ end
+ end
+
+ $display("Closing file...");
+ $fclose(file);
+end
+
+always
+ #4 usbclk = ~ usbclk;
+always
+ #1 master_clk = ~ master_clk;
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/full_chip.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/packets.dat
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/packets.dat
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_chains.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_chains.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_chains.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,23 @@
+module rx_chains (
+ input rxclk,
+ input reset,
+ input rxstrobe,
+ output [15:0] ch_0,
+ output [15:0] ch_1);
+
+ reg [15:0] i;
+
+ assign ch_0 = i;
+ assign ch_1 = 16'hFFFF - i;
+
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ i <= 1;
+ else
+ if (rxstrobe)
+ i <= i + 1;
+ end
+
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_chains.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_fake_fx2.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_fake_fx2.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_fake_fx2.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,117 @@
+module rx_fake_fx2();
+
+reg usbclk;
+reg rxclk;
+reg reset;
+reg bus_reset;
+wire [15:0] usbdata;
+reg RD;
+
+wire have_pkt_rdy;
+wire rxstrobe;
+wire rx_underrun;
+wire [15:0]ch_0;
+wire [15:0]ch_1;
+
+/* NOT USED YET */
+reg clear_status;
+reg [3:0]channels;
+reg SEN;
+
+rx_buffer_inband rx_buffer_inband_ (
+ .usbclk(usbclk),
+ .bus_reset(bus_reset),
+ .reset(reset),
+ .reset_regs(reset_regs),
+ .usbdata(usbdata),
+ .RD(RD),
+ .have_pkt_rdy(have_pkt_rdy),
+ .rx_overrun(rx_overrun),
+ .channels(4'd1),
+ .ch_0(ch_0),
+ .ch_1(ch_1),
+ .ch_2(),.ch_3(),.ch_4(),.ch_5(),.ch_6(),.ch_7(),
+ .rxclk(rxclk),
+ .rxstrobe(rxstrobe),
+ .clear_status(clear_status),
+ .serial_addr(),.serial_data(),
+ .serial_strobe(),
+ .debugbus() );
+
+strobe_gen strobe_gen_test(
+ .clock(rxclk),
+ .reset(reset),
+ .enable(SEN),
+ .rate(8'd15),
+ .strobe_in(1'd1),
+ .strobe(rxstrobe) );
+
+rx_chains fake_rx_chains (
+ .rxclk(rxclk),
+ .reset(reset),
+ .rxstrobe(rxstrobe),
+ .ch_0(ch_0),
+ .ch_1(ch_1) );
+
+initial begin
+ usbclk = 0;
+ rxclk = 0;
+ RD = 0;
+ SEN = 0;
+ reset = 1;
+ bus_reset = 1;
+
+ clear_status = 0;
+ channels = 0;
+
+ #384 reset = 0;
+ bus_reset = 0;
+ #528 SEN = 1;
+end
+
+reg [3:0]state;
+reg [8:0]count;
+
+parameter IDLE = 0;
+parameter WAIT = 1;
+parameter RCV = 2;
+
+always @(negedge usbclk)
+begin
+ if (bus_reset)
+ state <= IDLE;
+ else case (state)
+ IDLE: begin
+ if (have_pkt_rdy)
+ begin
+ state <= RCV;
+ RD <= 1;
+ count <= 0;
+ end
+ end
+
+ WAIT: state <= RCV;
+
+ RCV: begin
+ count <= count + 1;
+ if (usbdata != 16'hDEAD && count < 256)
+ $display(usbdata);
+
+ if (count == 256)
+ begin
+ RD <= 0;
+ state <= IDLE;
+ end
+ end
+
+ default: $display("fix test code");
+
+ endcase
+end
+
+always
+ #64 usbclk = ~ usbclk;
+always
+ #48 rxclk = ~ rxclk;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/rx_fake_fx2.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/strobe_gen_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/strobe_gen_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/strobe_gen_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,39 @@
+module strobe_gen_test();
+
+reg clock;
+reg reset;
+reg enable;
+reg [7:0] rate;
+reg strobe_in;
+wire strobe;
+
+strobe_gen strobe_gen_test(
+ .clock(clock),
+ .reset(reset),
+ .enable(enable),
+ .rate(rate),
+ .strobe_in(strobe_in),
+ .strobe(strobe) );
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ clock = 0;
+ rate = 8'd3;
+ strobe_in = 1;
+ enable = 1;
+
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge clock)
+ reset = 1'b0 ;
+ end
+end
+
+always
+ #5 clock = ~clock;
+
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/strobe_gen_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx.mpf
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx.mpf
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx.mpf
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,336 @@
+[Library]
+
+; Altera specific primitive library mappings
+
+vital2000 = $MODEL_TECH/../vital2000
+ieee = $MODEL_TECH/../ieee
+verilog = $MODEL_TECH/../verilog
+std = $MODEL_TECH/../std
+std_developerskit = $MODEL_TECH/../std_developerskit
+synopsys = $MODEL_TECH/../synopsys
+modelsim_lib = $MODEL_TECH/../modelsim_lib
+apex20k = $MODEL_TECH/../altera/vhdl/apex20k
+apex20ke = $MODEL_TECH/../altera/vhdl/apex20ke
+apexii = $MODEL_TECH/../altera/vhdl/apexii
+altera_mf = $MODEL_TECH/../altera/vhdl/altera_mf
+altera = $MODEL_TECH/../altera/vhdl/altera
+lpm = $MODEL_TECH/../altera/vhdl/220model
+220model = $MODEL_TECH/../altera/vhdl/220model
+alt_vtl = $MODEL_TECH/../altera/vhdl/alt_vtl
+flex6000 = $MODEL_TECH/../altera/vhdl/flex6000
+flex10ke = $MODEL_TECH/../altera/vhdl/flex10ke
+max = $MODEL_TECH/../altera/vhdl/max
+maxii = $MODEL_TECH/../altera/vhdl/maxii
+stratix = $MODEL_TECH/../altera/vhdl/stratix
+stratixii = $MODEL_TECH/../altera/vhdl/stratixii
+cyclone = $MODEL_TECH/../altera/vhdl/cyclone
+cycloneii = $MODEL_TECH/../altera/vhdl/cycloneii
+sgate = $MODEL_TECH/../altera/vhdl/sgate
+apex20k_ver = $MODEL_TECH/../altera/verilog/apex20k
+apex20ke_ver = $MODEL_TECH/../altera/verilog/apex20ke
+apexii_ver = $MODEL_TECH/../altera/verilog/apexii
+altera_mf_ver = $MODEL_TECH/../altera/verilog/altera_mf
+altera_ver = $MODEL_TECH/../altera/verilog/altera
+lpm_ver = $MODEL_TECH/../altera/verilog/220model
+220model_ver = $MODEL_TECH/../altera/verilog/220model
+alt_ver = $MODEL_TECH/../altera/verilog/alt_vtl
+flex6000_ver = $MODEL_TECH/../altera/verilog/flex6000
+flex10ke_ver = $MODEL_TECH/../altera/verilog/flex10ke
+max_ver = $MODEL_TECH/../altera/verilog/max
+maxii_ver = $MODEL_TECH/../altera/verilog/maxii
+stratix_ver = $MODEL_TECH/../altera/verilog/stratix
+stratixii_ver = $MODEL_TECH/../altera/verilog/stratixii
+cyclone_ver = $MODEL_TECH/../altera/verilog/cyclone
+cycloneii_ver = $MODEL_TECH/../altera/verilog/cycloneii
+sgate_ver = $MODEL_TECH/../altera/verilog/sgate
+stratixiii_ver = $MODEL_TECH/../altera/verilog/stratixiii
+stratixiii = $MODEL_TECH/../altera/vhdl/stratixiii
+
+work = work
+[vcom]
+; Turn on VHDL-1993 as the default. Normally is off.
+; VHDL93 = 1
+
+; Show source line containing error. Default is off.
+; Show_source = 1
+
+; Turn off unbound-component warnings. Default is on.
+; Show_Warning1 = 0
+
+; Turn off process-without-a-wait-statement warnings. Default is on.
+; Show_Warning2 = 0
+
+; Turn off null-range warnings. Default is on.
+; Show_Warning3 = 0
+
+; Turn off no-space-in-time-literal warnings. Default is on.
+; Show_Warning4 = 0
+
+; Turn off multiple-drivers-on-unresolved-signal warnings. Default is on.
+; Show_Warning5 = 0
+
+; Turn off optimization for IEEE std_logic_1164 package. Default is on.
+; Optimize_1164 = 0
+
+; Turn on resolving of ambiguous function overloading in favor of the
+; "explicit" function declaration (not the one automatically created by
+; the compiler for each type declaration). Default is off.
+; .ini file has Explict enable so that std_logic_signed/unsigned
+; will match synthesis tools behavior.
+ Explicit = 1
+
+; Turn off VITAL compliance checking. Default is checking on.
+; NoVitalCheck = 1
+
+; Ignore VITAL compliance checking errors. Default is to not ignore.
+; IgnoreVitalErrors = 1
+
+; Turn off VITAL compliance checking warnings. Default is to show warnings.
+; Show_VitalChecksWarnings = false
+
+; Turn off acceleration of the VITAL packages. Default is to accelerate.
+; NoVital = 1
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on some limited synthesis rule compliance checking. Checks only:
+; -- signals used (read) by a process must be in the sensitivity list
+; CheckSynthesis = 1
+
+; Require the user to specify a configuration for all bindings,
+; and do not generate a compile time default binding for the
+; component. This will result in an elaboration error of
+; 'component not bound' if the user fails to do so. Avoids the rare
+; issue of a false dependency upon the unused default binding.
+
+; RequireConfigForAllDefaultBinding = 1
+
+[vlog]
+
+; Turn off inclusion of debugging info within design units. Default is to
include.
+; NoDebug = 1
+
+; Turn off "loading..." messages. Default is messages on.
+; Quiet = 1
+
+; Turn on Verilog hazard checking (order-dependent accessing of global vars).
+; Default is off.
+; Hazard = 1
+
+; Turn on converting regular Verilog identifiers to uppercase. Allows case
+; insensitivity for module names. Default is no conversion.
+; UpCase = 1
+
+; Turns on incremental compilation of modules
+; Incremental = 1
+
+[vsim]
+; Simulator resolution
+; Set to fs, ps, ns, us, ms, or sec with optional prefix of 1, 10, or 100.
+resolution = 1ps
+
+; User time unit for run commands
+; Set to default, fs, ps, ns, us, ms, or sec. The default is to use the
+; unit specified for Resolution. For example, if Resolution is 100ps,
+; then UserTimeUnit defaults to ps.
+UserTimeUnit = default
+
+; Default run length
+RunLength = 0 ps
+
+; Maximum iterations that can be run without advancing simulation time
+IterationLimit = 5000
+
+; Directive to license manager:
+; vhdl Immediately reserve a VHDL license
+; vlog Immediately reserve a Verilog license
+; plus Immediately reserve a VHDL and Verilog license
+; nomgc Do not look for Mentor Graphics Licenses
+; nomti Do not look for Model Technology Licenses
+; noqueue Do not wait in the license queue when a license isn't available
+; License = plus
+
+; Stop the simulator after an assertion message
+; 0 = Note 1 = Warning 2 = Error 3 = Failure 4 = Fatal
+BreakOnAssertion = 3
+
+; Assertion Message Format
+; %S - Severity Level
+; %R - Report Message
+; %T - Time of assertion
+; %D - Delta
+; %I - Instance or Region pathname (if available)
+; %% - print '%' character
+; AssertionFormat = "** %S: %R\n Time: %T Iteration: %D%I\n"
+
+; Assertion File - alternate file for storing assertion messages
+; AssertFile = assert.log
+
+; Default radix for all windows and commands...
+; Set to symbolic, ascii, binary, octal, decimal, hex, unsigned
+DefaultRadix = symbolic
+
+; VSIM Startup command
+; Startup = do startup.do
+
+; File for saving command transcript
+TranscriptFile = transcript
+
+; File for saving command history
+;CommandHistory = cmdhist.log
+
+; Specify whether paths in simulator commands should be described
+; in VHDL or Verilog format. For VHDL, PathSeparator = /
+; for Verilog, PathSeparator = .
+PathSeparator = /
+
+; Specify the dataset separator for fully rooted contexts.
+; The default is ':'. For example, sim:/top
+; Must not be the same character as PathSeparator.
+DatasetSeparator = :
+
+; Disable assertion messages
+; IgnoreNote = 1
+; IgnoreWarning = 1
+; IgnoreError = 1
+; IgnoreFailure = 1
+
+; Default force kind. May be freeze, drive, or deposit
+; or in other terms, fixed, wired or charged.
+; DefaultForceKind = freeze
+
+; If zero, open files when elaborated
+; else open files on first read or write
+; DelayFileOpen = 0
+
+; Control VHDL files opened for write
+; 0 = Buffered, 1 = Unbuffered
+UnbufferedOutput = 0
+
+; Control number of VHDL files open concurrently
+; This number should always be less then the
+; current ulimit setting for max file descriptors
+; 0 = unlimited
+ConcurrentFileLimit = 40
+
+; This controls the number of hierarchical regions displayed as
+; part of a signal name shown in the waveform window. The default
+; value or a value of zero tells VSIM to display the full name.
+; WaveSignalNameWidth = 0
+
+; Turn off warnings from the std_logic_arith, std_logic_unsigned
+; and std_logic_signed packages.
+; StdArithNoWarnings = 1
+
+; Turn off warnings from the IEEE numeric_std and numeric_bit
+; packages.
+; NumericStdNoWarnings = 1
+
+; Control the format of a generate statement label. Don't quote it.
+; GenerateFormat = %s__%d
+
+; Specify whether checkpoint files should be compressed.
+; The default is to be compressed.
+; CheckpointCompressMode = 0
+
+; List of dynamically loaded objects for Verilog PLI applications
+; Veriuser = veriuser.sl
+[Project]
+Project_Version = 6
+Project_DefaultLib = work
+Project_SortMethod = unused
+Project_Files_Count = 29
+Project_File_0 = Z:/wc/inband/usrp/fpga/inband_lib/cmd_reader.v
+Project_File_P_0 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1182797882 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
28 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_1 = ./strobe_gen_test.v
+Project_File_P_1 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1177269906 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order 9
dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_2 = ./usb_fifo_writer_test.v
+Project_File_P_2 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_showsource 0 vlog_hazard 0 vlog_0InOptions
{} ood 0 vlog_upper 0 compile_to work vlog_options {} compile_order 13
cover_expr 0 dont_compile 0 cover_stmt 0
+Project_File_3 = Z:/wc/inband/usrp/fpga/inband_lib/channel_ram.v
+Project_File_P_3 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575398 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
20 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_4 = Z:/wc/simulations/data_packet_fifo_test.v
+Project_File_P_4 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
Level} last_compile 1181575397 cover_branch 0 vlog_noload 0 vlog_enable0In 0
vlog_disableopt 0 vlog_vopt 0 vlog_hazard 0 vlog_showsource 0 ood 0
vlog_0InOptions {} vlog_options {} compile_to work vlog_upper 0 compile_order
15 dont_compile 0 cover_expr 0 cover_stmt 0
+Project_File_5 = Z:/wc/simulations/fake_tx_chain.v
+Project_File_P_5 = cover_toggle 0 vlog_protect 0 file_type verilog group_id 0
cover_exttoggle 0 cover_cond 0 vlog_nodebug 0 vlog_1995compat 0 folder {Top
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Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx.mpf
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx_buffer_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx_buffer_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx_buffer_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,195 @@
+module tx_buffer_inband_test();
+
+parameter TSTAMP = 16'hFFFF ;
+
+// Inputs
+reg usbclk;
+reg bus_reset;
+reg reset;
+reg [15:0] usbdata;
+reg WR;
+reg [3:0] channels; // ={tx_num_chan, 1b'}
+reg txclk;
+reg clear_status;
+
+// Outputs
+wire have_space;
+wire tx_underrun;
+wire [15:0] tx_i_0;
+wire [15:0] tx_q_0;
+wire [15:0] tx_i_1;
+wire [15:0] tx_q_1;
+wire [15:0] tx_i_2;
+wire [15:0] tx_q_2;
+wire [15:0] tx_i_3;
+wire [15:0] tx_q_3;
+wire tx_empty;
+wire [11:0] debugbus;
+
+// Tests
+reg [15:0] i ;
+
+wire txstrobe;
+
+tx_buffer_inband tx_buffer_test (
+ .usbclk(usbclk),
+ .reset(reset),
+ .usbdata(usbdata),
+ .WR(WR),
+ .txclk(txclk),
+ .txstrobe(txstrobe),
+ .tx_empty(tx_empty),
+ .have_space(have_space),
+ .tx_underrun(tx_underrun),
+ .tx_i_0(tx_i_0),
+ .tx_i_1(tx_i_1),
+ .tx_i_2(tx_i_2),
+ .tx_i_3(tx_i_3),
+ .tx_q_0(tx_q_0),
+ .tx_q_1(tx_q_1),
+ .tx_q_2(tx_q_2),
+ .tx_q_3(tx_q_3),
+ .bus_reset(1'b0),
+ .clear_status(1'b0),
+ .channels(4'b0),
+ .debugbus()
+);
+
+strobe_gen strobe_gen_test(
+ .clock(txclk),
+ .reset(reset),
+ .enable(1'd1),
+ .rate(8'd3),
+ .strobe_in(1'd1),
+ .strobe(txstrobe) );
+
+
+// Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ usbclk = 0;
+ usbdata = 0;
+ WR = 0;
+ txclk = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge usbclk)
+ reset = 1'b0 ;
+ end
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+
+ i = 0;
+
+ // Write one full packet (channel 1)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usbdata = 1;
+ else if (i == 1)
+ // payload size
+ usbdata = 504;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ i = 0;
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+
+ i = 0;
+
+ // Write one full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usbdata = 0;
+ else if (i == 1)
+ // payload size
+ usbdata = 504;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ i = 0;
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usbclk)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usbdata = 32;
+ // timestamp = now
+ else if (i == 2 || i == 3)
+ usbdata = TSTAMP;
+ else
+ usbdata = i ;
+ i = i + 1 ;
+ end
+ @(posedge usbclk)
+ WR = 1'b0 ;
+ end
+
+always
+ #3 txclk = ~txclk ;
+always
+ #5 usbclk = ~usbclk ;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/tx_buffer_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_reader_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_reader_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_reader_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,152 @@
+module usb_fifo_reader_test () ;
+
+//INPUTS
+reg usb_clock;
+reg tx_clock;
+reg [15:0] usb_data;
+reg WR;
+reg reset;
+
+//OUPUTS
+wire [31:0] tx_data_bus;
+wire [2:0]WR_chan;
+wire [2:0]done_chan;
+wire have_space ;
+wire tx_empty ;
+
+wire [31:0]to_write_data ;
+wire [7:0] tupf_usedw ;
+wire wrfull;
+reg [15:0] i ;
+
+wire [31:0] fifodata;
+wire rdreq;
+wire pkt_waiting;
+
+usb_fifo_writer tx_usb_packet_writer
+ ( .reset (reset),
+ .usb_clock (usb_clock),
+ .write_enable_fx2 (WR),
+ .bus_data (usb_data),
+ .write_enable_fifo (tupf_write_enable),
+ .write_data (to_write_data)
+ );
+
+ fifo_1k tx_usb_packet_fifo
+ ( .aclr (reset),
+ .wrclk (usb_clock),
+ .rdclk (tx_clock),
+ .data (to_write_data),
+ .wrreq (tupf_write_enable),
+ .q (fifodata),
+ .rdreq (rdreq),
+ .wrfull (wrfull),
+ .rdempty (),
+ .rdusedw (tupf_usedw)
+ );
+
+usb_fifo_reader reader (
+ .reset(reset),
+ .tx_clock(tx_clock),
+ .tx_data_bus(tx_data_bus),
+ .WR_chan(WR_chan),
+ .done_chan(done_chan),
+ .fifodata(fifodata),
+ .pkt_waiting(pkt_waiting),
+ .rdreq(rdreq)
+ );
+
+assign pkt_waiting = (tupf_usedw >= 128) ;
+assign have_space = ~wrfull ;
+
+// Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ usb_clock = 0;
+ usb_data = 0;
+ WR = 0;
+ tx_clock = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #80 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge usb_clock)
+ reset = 1'b0 ;
+ end
+
+ // Write one half full packet (channel 0)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 1)
+ // payload size
+ usb_data = 32;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+ @(posedge usb_clock)
+ WR = 1'b0 ;
+
+ i = 0;
+ // Wait
+ while(have_space == 0)
+ begin
+ @(posedge usb_clock)
+ i = 0;
+ end
+
+ // Write one full packet (channel 1)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usb_data = 1;
+ else if (i == 1)
+ // payload size
+ usb_data = 500;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+ @(posedge usb_clock)
+ WR = 1'b0 ;
+
+ i = 0;
+ // Wait
+ while(have_space == 0)
+ begin
+ @(posedge usb_clock)
+ i = 0;
+ end
+
+ // Write one half full packet (cmd)
+ repeat (256) begin
+ @(posedge usb_clock)
+ WR = 1'b1 ;
+ if (i == 0)
+ // channel
+ usb_data = 16'h1F;
+ else if (i == 1)
+ // payload size
+ usb_data = 128;
+ else
+ usb_data = i ;
+ i = i + 1 ;
+ end
+ @(posedge usb_clock)
+ WR = 1'b0 ;
+ end
+
+always
+ #5 tx_clock = ~tx_clock ;
+
+always
+ #13 usb_clock = ~usb_clock ;
+
+endmodule
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_reader_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_writer_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_writer_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_writer_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,82 @@
+module usb_fifo_writer_test() ;
+
+
+reg bus_reset ;
+reg usbclk ;
+reg WR_fx2 ;
+reg [15:0]usbdata ;
+
+reg reset;
+reg txclk;
+wire [2:0] WR_channel;
+wire [31:0]ram_data ;
+wire [2:0]WR_done_channel;
+
+
+reg [15:0] i ;
+
+usb_fifo_writer writer (//FX2 Side
+ .bus_reset(bus_reset),
+ .usbclk(usbclk),
+ .WR_fx2(WR_fx2),
+ .usbdata(usbdata),
+
+ // TX Side
+ .reset(reset),
+ .txclk(txclk),
+ .WR_channel(WR_channel),
+ .ram_data(ram_data),
+ .WR_done_channel(WR_done_channel) );
+
+initial begin
+ bus_reset = 1;
+ reset = 1 ;
+ usbclk = 0 ;
+ txclk = 0;
+ WR_fx2 = 0 ;
+ usbdata = 0 ;
+ i = 0 ;
+
+ #400 reset = 0 ;
+ bus_reset = 0;
+
+ send_packet(100, 16'd0, 32'hFFFFFFFF);
+ send_packet(30, 16'd0, 32'hFFFFFFFF);
+ send_packet(120, 16'd0, 32'hFFFFFFFF);
+ send_packet(170, 16'd0, 32'hFFFFFFFF);
+
+end
+
+always
+ #64 usbclk = ~usbclk ;
+
+ always
+ #48 txclk = ~txclk ;
+
+
+ task send_packet;
+ input [8:0]length;
+ input [15:0] channel;
+ input [31:0] timestamp;
+ begin
+ repeat (256) begin
+ @(posedge usbclk)
+ WR_fx2 = 1;
+ if (i == 1) usbdata = channel;
+ else if (i == 0) usbdata = length;
+ else if (i == 3) usbdata = timestamp[31:16];
+ else if (i == 2) usbdata = timestamp[15:0];
+ else usbdata = i;//{16'hFFFF - i,i};
+ i = i + 1;
+ end
+ @(posedge usbclk)
+ WR_fx2 = 1;
+ @(posedge usbclk)
+ WR_fx2 = 0;
+
+ i = 0;
+ end
+ endtask
+
+
+endmodule
\ No newline at end of file
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_fifo_writer_test.v
___________________________________________________________________
Name: svn:executable
+ *
Added:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_packet_fifo_test.v
===================================================================
---
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_packet_fifo_test.v
(rev 0)
+++
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_packet_fifo_test.v
2008-05-15 17:51:05 UTC (rev 8431)
@@ -0,0 +1,176 @@
+module usb_packet_fifo_test() ;
+
+ // Inputs
+ reg reset;
+ reg clock_in;
+ reg [15:0] ram_data_in;
+ reg write_enable;
+ reg clock_out;
+ reg read_enable;
+ reg skip_packet;
+
+ reg [15:0] i ;
+
+
+ // Outputs
+ wire [15:0] ram_data_out;
+ wire is_packet;
+ wire have_space;
+
+ // Instantiate the UUT
+ usb_packet_fifo uut (
+ .reset(reset),
+ .clock_in(clock_in),
+ .ram_data_in(ram_data_in),
+ .write_enable(write_enable),
+ .clock_out(clock_out),
+ .ram_data_out(ram_data_out),
+ .pkt_waiting(is_packet),
+ .read_enable(read_enable),
+ .skip_packet(skip_packet),
+ .have_space(have_space)
+ );
+
+
+ // Initialize Inputs
+ initial begin
+ // Setup the initial conditions
+ reset = 1;
+ clock_in = 0;
+ ram_data_in = 0;
+ write_enable = 0;
+ clock_out = 0;
+ read_enable = 0;
+ skip_packet = 0;
+ i = 0 ;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge clock_in)
+ reset = 1'b0 ;
+ end
+
+ // Write an entire packets worth of data
+ // into the FIFO
+ repeat (256) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ @(posedge clock_in)
+ write_enable = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+
+ i = 0;
+ repeat (256) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ repeat (256) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ repeat (256) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ repeat (256) begin
+ @(posedge clock_in)
+ write_enable = 1'b1 ;
+ ram_data_in = i ;
+ i = i + 1 ;
+ end
+ @(posedge clock_in)
+ write_enable = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+ // Only read the first 10 bytes of data
+ repeat (10) begin
+ @(posedge clock_out)
+ read_enable = 1'b1 ;
+ end
+ @(posedge clock_out)
+ read_enable = 1'b0 ;
+
+ // Skip the rest of the packet
+ @(posedge clock_out)
+ skip_packet = 1'b1 ;
+ @(posedge clock_out)
+ skip_packet = 1'b0 ;
+
+ end
+
+ always
+ #5 clock_in = ~clock_in ;
+
+ always
+ #13 clock_out = ~clock_out ;
+
+
+endmodule
+
Property changes on:
gnuradio/branches/developers/gnychis/fpga/usrp/fpga/inband_lib/testbenches/usb_packet_fifo_test.v
___________________________________________________________________
Name: svn:executable
+ *
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