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[Commit-gnuradio] r8400 - usrp2/trunk/firmware/lib
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r8400 - usrp2/trunk/firmware/lib |
|
Date: |
Sun, 11 May 2008 18:25:25 -0600 (MDT) |
Author: matt
Date: 2008-05-11 18:25:21 -0600 (Sun, 11 May 2008)
New Revision: 8400
Modified:
usrp2/trunk/firmware/lib/db_rfx.c
Log:
gain control basically works, removed a lot of old python
Modified: usrp2/trunk/firmware/lib/db_rfx.c
===================================================================
--- usrp2/trunk/firmware/lib/db_rfx.c 2008-05-11 21:13:59 UTC (rev 8399)
+++ usrp2/trunk/firmware/lib/db_rfx.c 2008-05-12 00:25:21 UTC (rev 8400)
@@ -1,4 +1,3 @@
-/* -*- c++ -*- */
/*
* Copyright 2008 Free Software Foundation, Inc.
*
@@ -23,11 +22,13 @@
#include <ad9510.h>
#include <stdio.h>
#include <mdelay.h>
+#include <lsdac.h>
bool rfx_init_rx(struct db_base *db);
bool rfx_init_tx(struct db_base *db);
bool rfx_set_freq(struct db_base *db, u2_fxpt_freq_t freq, u2_fxpt_freq_t *dc);
-bool rfx_set_gain(struct db_base *db, u2_fxpt_gain_t gain);
+bool rfx_set_gain_rx(struct db_base *db, u2_fxpt_gain_t gain);
+bool rfx_set_gain_tx(struct db_base *db, u2_fxpt_gain_t gain);
bool rfx_set_tx_enable(struct db_base *, bool on);
// Control Latch Defines
@@ -149,7 +150,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_rx,
.base.set_tx_enable = 0,
.base.atr_mask = 0x00E0,
.base.atr_txval = POWER_UP,
@@ -181,7 +182,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_tx,
.base.set_tx_enable = rfx_set_tx_enable,
.base.atr_mask = 0x00E0,
.base.atr_txval = POWER_UP|MIX_EN,
@@ -212,7 +213,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_rx,
.base.set_tx_enable = 0,
.base.atr_mask = 0x00E0,
.base.atr_txval = 0,
@@ -244,7 +245,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_tx,
.base.set_tx_enable = rfx_set_tx_enable,
.base.atr_mask = 0x00E0,
.base.atr_txval = MIX_EN,
@@ -275,7 +276,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_rx,
.base.set_tx_enable = 0,
.base.atr_mask = 0x00E0,
.base.atr_txval = 0,
@@ -307,7 +308,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_tx,
.base.set_tx_enable = rfx_set_tx_enable,
.base.atr_mask = 0x00E0,
.base.atr_txval = MIX_EN,
@@ -338,7 +339,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_rx,
.base.set_tx_enable = 0,
.base.atr_mask = 0x00E0,
.base.atr_txval = 0,
@@ -370,7 +371,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_tx,
.base.set_tx_enable = rfx_set_tx_enable,
.base.atr_mask = 0x00E0,
.base.atr_txval = MIX_EN,
@@ -402,7 +403,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_rx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_rx,
.base.set_tx_enable = 0,
.base.atr_mask = 0x00E0,
.base.atr_txval = 0,
@@ -434,7 +435,7 @@
//.base.lo_offset = U2_DOUBLE_TO_FXPT_FREQ(4e6),
.base.init = rfx_init_tx,
.base.set_freq = rfx_set_freq,
- .base.set_gain = rfx_set_gain,
+ .base.set_gain = rfx_set_gain_tx,
.base.set_tx_enable = rfx_set_tx_enable,
.base.atr_mask = 0x00E0,
.base.atr_txval = MIX_EN,
@@ -466,6 +467,10 @@
ad9510_write_reg(0x43, 0x08); // enable output 7 (db_rx_clk), CMOS
ad9510_write_reg(0x57, 0x80); // Bypass Div #7, 100 MHz clock
ad9510_write_reg(0x5A, 0x01); // Update Regs
+
+ // test gain
+ db->base.set_gain(db,U2_DOUBLE_TO_FXPT_GAIN(45.0));
+ printf("set the gain\n");
return true;
}
@@ -491,7 +496,7 @@
spi_transact(SPI_TXONLY,db->common.spi_mask,R,24,SPIF_PUSH_FALL);
spi_transact(SPI_TXONLY,db->common.spi_mask,C,24,SPIF_PUSH_FALL);
- mdelay(100);
+ mdelay(10);
spi_transact(SPI_TXONLY,db->common.spi_mask,N,24,SPIF_PUSH_FALL);
printf("A = %d, B = %d, N_DIV = %d\n",A, B, N_DIV);
@@ -499,13 +504,55 @@
return true;
}
+bool
+rfx_set_gain_tx(struct db_base *dbb, u2_fxpt_gain_t gain)
+{
+ // There is no analog gain control on TX
+ return true;
+}
bool
-rfx_set_gain(struct db_base *dbb, u2_fxpt_gain_t gain)
+rfx_set_gain_rx(struct db_base *dbb, u2_fxpt_gain_t gain)
{
struct db_rfx_dummy *db = (struct db_rfx_dummy *) dbb;
- return false;
+ u2_fxpt_gain_t MAXGAIN = U2_DOUBLE_TO_FXPT_GAIN(70.0);
+
+ int offset_q8 = (int)(1.2/3.3*4096*(1<<15));
+ int slope_q8 = (int)(-1.0/45.0*4096/3.3*256);
+ int dacword = ((slope_q8 * gain) + offset_q8)>>15;
+ printf("DACWORD %d\n",dacword);
+ lsdac_write_rx(1,dacword);
+ return true;
+ /*
+ def set_gain(self, gain):
+ """
+ Set the gain.
+
+ @param gain: gain in decibels
+ @returns True/False
+ """
+ maxgain = self.gain_range()[1] - self._u.pga_max()
+ mingain = self.gain_range()[0]
+ if gain > maxgain:
+ pga_gain = gain-maxgain
+ assert pga_gain <= self._u.pga_max()
+ agc_gain = maxgain
+ else:
+ pga_gain = 0
+ agc_gain = gain
+ V_maxgain = .2
+ V_mingain = 1.2
+ V_fullscale = 3.3
+ dac_value = (agc_gain*(V_maxgain-V_mingain)/(maxgain-mingain) +
V_mingain)*4096/V_fullscale
+ assert dac_value>=0 and dac_value<4096
+ return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
+ self._set_pga(int(pga_gain))
+
+ def gain_range(self):
+ return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For
900-2400
+ return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400
+ */
}
@@ -528,299 +575,7 @@
return false;
}
-
/*
-# Tx and Rx have shared defs, but different i/o regs
-AUX_RXAGC = (1 << 8)
-ENABLE = (1 << 5) # enables mixer
-AUX_SEN = (1 << 4)
-AUX_SCLK = (1 << 3)
-PLL_LOCK_DETECT = (1 << 2)
-AUX_SDO = (1 << 1)
-CLOCK_OUT = (1 << 0)
-
-SPI_ENABLE_TX_A = usrp1.SPI_ENABLE_TX_A
-SPI_ENABLE_TX_B = usrp1.SPI_ENABLE_TX_B
-SPI_ENABLE_RX_A = usrp1.SPI_ENABLE_RX_A
-SPI_ENABLE_RX_B = usrp1.SPI_ENABLE_RX_B
-
-class flexrf_base(db_base.db_base):
- """
- Abstract base class for all flexrf boards.
-
- Derive board specific subclasses from db_flexrf_base_{tx,rx}
- """
- def __init__(self, usrp, which):
- """
- @param usrp: instance of usrp.source_c
- @param which: which side: 0 or 1 corresponding to side A or B
respectively
- @type which: int
- """
- # sets _u _which _tx and _slot
- db_base.db_base.__init__(self, usrp, which)
-
- self.first = True
- self.spi_format = usrp1.SPI_FMT_MSB | usrp1.SPI_FMT_HDR_0
-
- self._u._write_oe(self._which, 0, 0xffff) # turn off all outputs
- self._enable_refclk(False) # disable refclk
-
- g = self.gain_range() # initialize gain
- self.set_gain(float(g[0]+g[1]) / 2)
-
- self.set_auto_tr(False)
-
- if debug_using_gui:
- title = "FlexRF Debug Rx"
- if self._tx:
- title = "FlexRF Debug Tx"
- self.gui = flexrf_debug_gui.flexrf_debug_gui(self, title)
- self.gui.Show(True)
-
-
- def __del__(self):
- #print "flexrf_base.__del__"
- self._u.write_io(self._which, self.power_off, POWER_UP) # turn off
power to board
- # Power down VCO/PLL
- self.PD = 3
- self._write_control(self._compute_control_reg())
- self._enable_refclk(False) # turn off refclk
- self.set_auto_tr(False)
-
- def _write_all(self, R, control, N):
- """
- Write R counter latch, control latch and N counter latch to VCO.
-
- Adds 10ms delay between writing control and N if this is first call.
- This is the required power-up sequence.
-
- @param R: 24-bit R counter latch
- @type R: int
- @param control: 24-bit control latch
- @type control: int
- @param N: 24-bit N counter latch
- @type N: int
- """
- self._write_R(R)
- self._write_control( control)
- if self.first:
- time.sleep(0.010)
- self.first = False
- self._write_N(N)
-
- def _write_control(self, control):
- self._write_it((control & ~0x3) | 0)
-
- def _write_R(self, R):
- self._write_it((R & ~0x3) | 1)
-
- def _write_N(self, N):
- self._write_it((N & ~0x3) | 2)
-
- def _write_it(self, v):
- s = ''.join((chr((v >> 16) & 0xff),
- chr((v >> 8) & 0xff),
- chr(v & 0xff)))
- self._u._write_spi(0, self.spi_enable, self.spi_format, s)
-
- def _lock_detect(self):
- """
- @returns: the value of the VCO/PLL lock detect bit.
- @rtype: 0 or 1
- """
- if self._u.read_io(self._which) & PLL_LOCK_DETECT:
- return True
- else: # Give it a second chance
- if self._u.read_io(self._which) & PLL_LOCK_DETECT:
- return True
- else:
- return False
-
- def _compute_regs(self, freq):
- """
- Determine values of R, control, and N registers, along with actual
freq.
-
- @param freq: target frequency in Hz
- @type freq: float
- @returns: (R, control, N, actual_freq)
- @rtype: tuple(int, int, int, float)
-
- Override this in derived classes.
- """
- raise NotImplementedError
-
- def _refclk_freq(self):
- # return float(self._u.fpga_master_clock_freq())/self._refclk_divisor()
- return 64e6/self._refclk_divisor()
-
- def set_freq(self, freq):
- """
- @returns (ok, actual_baseband_freq) where:
- ok is True or False and indicates success or failure,
- actual_baseband_freq is the RF frequency that corresponds to DC in
the IF.
- """
-
- # Offsetting the LO helps get the Tx carrier leakage out of the way.
- # This also ensures that on Rx, we're not getting hosed by the
- # FPGA's DC removal loop's time constant. We were seeing a
- # problem when running with discontinuous transmission.
- # Offsetting the LO made the problem go away.
- freq += self._lo_offset
-
- R, control, N, actual_freq = self._compute_regs(freq)
- if R==0:
- return(False,0)
- self._write_all(R, control, N)
- return (self._lock_detect(), actual_freq)
-
- def gain_range(self):
- """
- Return range of gain that can be set by this d'board.
-
- @returns (min_gain, max_gain, step_size)
- Where gains are expressed in decibels (your mileage may vary)
- """
- return (self._u.pga_min(), self._u.pga_max(),
self._u.pga_db_per_step())
-
- def set_gain(self, gain):
- """
- Set the gain.
-
- @param gain: gain in decibels
- @returns True/False
- """
- return self._set_pga(gain)
-
- def _set_pga(self, pga_gain):
- if(self._which == 0):
- self._u.set_pga (0, pga_gain)
- self._u.set_pga (1, pga_gain)
- else:
- self._u.set_pga (2, pga_gain)
- self._u.set_pga (3, pga_gain)
-
- def is_quadrature(self):
- """
- Return True if this board requires both I & Q analog channels.
-
- This bit of info is useful when setting up the USRP Rx mux register.
- """
- return True
-
- def set_lo_offset(self, offset):
- """
- Set amount by which LO is offset from requested tuning frequency.
-
- @param offset: offset in Hz
- """
- self._lo_offset = offset
-
- def lo_offset(self):
- """
- Get amount by which LO is offset from requested tuning frequency.
-
- @returns Offset in Hz
- """
- return self._lo_offset
-
-# ----------------------------------------------------------------
-
-class flexrf_base_tx(flexrf_base):
- def __init__(self, usrp, which):
- """
- @param usrp: instance of usrp.sink_c
- @param which: 0 or 1 corresponding to side TX_A or TX_B respectively.
- """
- flexrf_base.__init__(self, usrp, which)
- self.spi_enable = (SPI_ENABLE_TX_A, SPI_ENABLE_TX_B)[which]
-
- # power up the transmit side, but don't enable the mixer
- self._u._write_oe(self._which,(POWER_UP|RX_TXN|ENABLE), 0xffff)
- self._u.write_io(self._which, (self.power_on|RX_TXN),
(POWER_UP|RX_TXN|ENABLE))
- self.set_lo_offset(4e6)
-
- def __del__(self):
- #print "flexrf_base_tx.__del__"
- # Power down and leave the T/R switch in the R position
- self._u.write_io(self._which, (self.power_off|RX_TXN),
(POWER_UP|RX_TXN|ENABLE))
- flexrf_base.__del__(self)
-
- def set_auto_tr(self, on):
- if on:
- self.set_atr_mask (RX_TXN | ENABLE)
- self.set_atr_txval(0 | ENABLE)
- self.set_atr_rxval(RX_TXN | 0)
- else:
- self.set_atr_mask (0)
- self.set_atr_txval(0)
- self.set_atr_rxval(0)
-
- def set_enable(self, on):
- """
- Enable transmitter if on is True
- """
- mask = RX_TXN | ENABLE
- if on:
- v = ENABLE
- else:
- v = RX_TXN
- self._u.write_io(self._which, v, mask)
-
- def gain_range(self):
- """
- Return range of gain that can be set by this d'board.
-
- @returns (min_gain, max_gain, step_size)
- Where gains are expressed in decibels (your mileage may vary)
-
- Flex Tx boards require that the PGA be maxed out to properly bias
their circuitry.
- """
- g = self._u.pga_max()
- return (g, g, 1.0)
-
- def set_gain(self, gain):
- """
- Set the gain.
-
- @param gain: gain in decibels
- @returns True/False
- """
- return self._set_pga(self._u.pga_max())
-
-class flexrf_base_rx(flexrf_base):
- def __init__(self, usrp, which):
- """
- @param usrp: instance of usrp.source_c
- @param which: 0 or 1 corresponding to side RX_A or RX_B respectively.
- """
- flexrf_base.__init__(self, usrp, which)
- self.spi_enable = (SPI_ENABLE_RX_A, SPI_ENABLE_RX_B)[which]
-
- self._u._write_oe(self._which, (POWER_UP|RX2_RX1N|ENABLE), 0xffff)
- self._u.write_io(self._which, (self.power_on|RX2_RX1N|ENABLE),
(POWER_UP|RX2_RX1N|ENABLE))
-
- # set up for RX on TX/RX port
- self.select_rx_antenna('TX/RX')
-
- self.bypass_adc_buffers(True)
- self.set_lo_offset(-4e6)
-
- def __del__(self):
- # print "flexrf_base_rx.__del__"
- # Power down
- self._u.write_io(self._which, self.power_off, (POWER_UP|ENABLE))
- flexrf_base.__del__(self)
-
- def set_auto_tr(self, on):
- if on:
- self.set_atr_mask (ENABLE)
- self.set_atr_txval( 0)
- self.set_atr_rxval(ENABLE)
- else:
- self.set_atr_mask (0)
- self.set_atr_txval(0)
- self.set_atr_rxval(0)
-
def select_rx_antenna(self, which_antenna):
"""
Specify which antenna port to use for reception.
@@ -857,212 +612,6 @@
return self._u.write_aux_dac(self._which, 0, int(dac_value)) and \
self._set_pga(int(pga_gain))
-# ----------------------------------------------------------------
-
-class _AD4360_common(object):
- def __init__(self):
- # R-Register Common Values
- self.R_RSV = 0 # bits 23,22
- self.BSC = 3 # bits 21,20 Div by 8 to be safe
- self.TEST = 0 # bit 19
- self.LDP = 1 # bit 18
- self.ABP = 0 # bit 17,16 3ns
-
- # N-Register Common Values
- self.N_RSV = 0 # bit 7
-
- # Control Register Common Values
- self.PD = 0 # bits 21,20 Normal operation
- self.PL = 0 # bits 13,12 11mA
- self.MTLD = 1 # bit 11 enabled
- self.CPG = 0 # bit 10 CP setting 1
- self.CP3S = 0 # bit 9 Normal
- self.PDP = 1 # bit 8 Positive
- self.MUXOUT = 1 # bits 7:5 Digital Lock Detect
- self.CR = 0 # bit 4 Normal
- self.PC = 1 # bits 3,2 Core power 10mA
-
- def _compute_regs(self, freq):
- """
- Determine values of R, control, and N registers, along with actual
freq.
-
- @param freq: target frequency in Hz
- @type freq: float
- @returns: (R, control, N, actual_freq)
- @rtype: tuple(int, int, int, float)
- """
-
- # Band-specific N-Register Values
- phdet_freq = self._refclk_freq()/self.R_DIV
- desired_n = round(freq*self.freq_mult/phdet_freq)
- actual_freq = desired_n * phdet_freq
- B = math.floor(desired_n/self._prescaler())
- A = desired_n - self._prescaler()*B
- self.B_DIV = int(B) # bits 20:8
- self.A_DIV = int(A) # bit 6:2
- #assert self.B_DIV >= self.A_DIV
- if self.B_DIV < self.A_DIV:
- return (0,0,0,0)
- R = (self.R_RSV<<22) | (self.BSC<<20) | (self.TEST<<19) |
(self.LDP<<18) \
- | (self.ABP<<16) | (self.R_DIV<<2)
-
- control = self._compute_control_reg()
-
- N = (self.DIVSEL<<23) | (self.DIV2<<22) | (self.CPGAIN<<21) |
(self.B_DIV<<8) | \
- (self.N_RSV<<7) | (self.A_DIV<<2)
-
- return (R,control,N,actual_freq/self.freq_mult)
-
- def _compute_control_reg(self):
- control = (self.P<<22) | (self.PD<<20) | (self.CP2<<17) |
(self.CP1<<14) | (self.PL<<12) \
- | (self.MTLD<<11) | (self.CPG<<10) | (self.CP3S<<9) |
(self.PDP<<8) | \
- (self.MUXOUT<<5) | (self.CR<<4) | (self.PC<<2)
- return control
-
- def _refclk_divisor(self):
- """
- Return value to stick in REFCLK_DIVISOR register
- """
- return 1
-
- def _prescaler(self):
- if self.P == 0:
- return 8
- elif self.P == 1:
- return 16
- else:
- return 32
-
-#----------------------------------------------------------------------
-class _2400_common(_AD4360_common):
- def __init__(self):
- _AD4360_common.__init__(self)
-
- # Band-specific R-Register Values
- self.R_DIV = 16 # bits 15:2
-
- # Band-specific C-Register values
- self.P = 1 # bits 23,22 Div by 16/17
- self.CP2 = 7 # bits 19:17
- self.CP1 = 7 # bits 16:14
-
- # Band specifc N-Register Values
- self.DIVSEL = 0 # bit 23
- self.DIV2 = 0 # bit 22
- self.CPGAIN = 0 # bit 21
- self.freq_mult = 1
-
- def freq_range(self): # FIXME
- return (2300e6, 2700e6, 4e6)
-
-#----------------------------------------------------------------------
-class _1200_common(_AD4360_common):
- def __init__(self):
- _AD4360_common.__init__(self)
-
- # Band-specific R-Register Values
- self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
-
- # Band-specific C-Register values
- self.P = 1 # bits 23,22 Div by 16/17
- self.CP2 = 7 # bits 19:17 1.25 mA
- self.CP1 = 7 # bits 16:14 1.25 mA
-
- # Band specifc N-Register Values
- self.DIVSEL = 0 # bit 23
- self.DIV2 = 1 # bit 22
- self.CPGAIN = 0 # bit 21
- self.freq_mult = 2
-
- def freq_range(self): # FIXME
- return (1150e6, 1350e6, 4e6)
-
-#-------------------------------------------------------------------------
-class _1800_common(_AD4360_common):
- def __init__(self):
- _AD4360_common.__init__(self)
-
- # Band-specific R-Register Values
- self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
-
- # Band-specific C-Register values
- self.P = 1 # bits 23,22 Div by 16/17
- self.CP2 = 7 # bits 19:17 1.25 mA
- self.CP1 = 7 # bits 16:14 1.25 mA
-
- # Band specifc N-Register Values
- self.DIVSEL = 0 # bit 23
- self.DIV2 = 0 # bit 22
- self.freq_mult = 1
- self.CPGAIN = 0 # bit 21
-
- def freq_range(self): # FIXME
- return (1600e6, 2000e6, 4e6)
-
-#-------------------------------------------------------------------------
-class _900_common(_AD4360_common):
- def __init__(self):
- _AD4360_common.__init__(self)
-
- # Band-specific R-Register Values
- self.R_DIV = 16 # bits 15:2 DIV by 16 for a 1 MHz phase detector freq
-
- # Band-specific C-Register values
- self.P = 1 # bits 23,22 Div by 16/17
- self.CP2 = 7 # bits 19:17 1.25 mA
- self.CP1 = 7 # bits 16:14 1.25 mA
-
- # Band specifc N-Register Values
- self.DIVSEL = 0 # bit 23
- self.DIV2 = 1 # bit 22
- self.freq_mult = 2
- self.CPGAIN = 0 # bit 21
-
- def freq_range(self): # FIXME
- return (800e6, 1000e6, 4e6)
-
-#-------------------------------------------------------------------------
-class _400_common(_AD4360_common):
- def __init__(self):
- _AD4360_common.__init__(self)
-
- # Band-specific R-Register Values
- self.R_DIV = 16 # bits 15:2
-
- # Band-specific C-Register values
- self.P = 0 # bits 23,22 Div by 8/9
- self.CP2 = 7 # bits 19:17 1.25 mA
- self.CP1 = 7 # bits 16:14 1.25 mA
-
- # Band specifc N-Register Values These are different for TX/RX
- self.DIVSEL = 0 # bit 23
- if self._tx:
- self.DIV2 = 1 # bit 22
- else:
- self.DIV2 = 0 # bit 22 # RX side has built-in DIV2 in AD8348
- self.freq_mult = 2
-
- self.CPGAIN = 0 # bit 21
-
- def freq_range(self):
- return (400e6, 500e6, 1e6) # final version
-
-
-#------------------------------------------------------------
-class db_flexrf_900_tx(_900_common, flexrf_base_tx):
- def __init__(self, usrp, which):
- self.power_on = 0
- self.power_off = 0 # powering it off kills the serial bus
- flexrf_base_tx.__init__(self, usrp, which)
- _900_common.__init__(self)
-
-class db_flexrf_400_tx(_400_common, flexrf_base_tx):
- def __init__(self, usrp, which):
- self.power_on = POWER_UP
- self.power_off = 0
- flexrf_base_tx.__init__(self, usrp, which)
- _400_common.__init__(self)
-
def gain_range(self):
return (self._u.pga_min(), self._u.pga_max() + 70, 0.05) -- For
900-2400
return (self._u.pga_min(), self._u.pga_max() + 45, 0.035) -- For 400
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