[Commit-gnuradio] r8330 - usrp2/trunk/fpga/control_lib

[matt]

Author: matt
Date: 2008-05-08 19:45:48 -0600 (Thu, 08 May 2008)
New Revision: 8330

Modified:
   usrp2/trunk/fpga/control_lib/atr_controller.v
   usrp2/trunk/fpga/control_lib/nsgpio.v
Log:
rearranged atr and debug lines


Modified: usrp2/trunk/fpga/control_lib/atr_controller.v
===================================================================
--- usrp2/trunk/fpga/control_lib/atr_controller.v       2008-05-09 01:44:41 UTC 
(rev 8329)
+++ usrp2/trunk/fpga/control_lib/atr_controller.v       2008-05-09 01:45:48 UTC 
(rev 8330)
@@ -7,7 +7,8 @@
   (input clk_i, input rst_i,
    input [3:0] adr_i, input [31:0] dat_i, output [31:0] dat_o,
    input we_i, input stb_i, input cyc_i, output reg ack_o,
-   input run_rx, input run_tx, output [31:0] ctrl_lines);
+   input run_rx, input run_tx, input [31:0] master_time,
+   output [31:0] ctrl_lines);
    
    reg [3:0] state;
    reg [31:0] atr_ram [0:15];  // DP distributed RAM

Modified: usrp2/trunk/fpga/control_lib/nsgpio.v
===================================================================
--- usrp2/trunk/fpga/control_lib/nsgpio.v       2008-05-09 01:44:41 UTC (rev 
8329)
+++ usrp2/trunk/fpga/control_lib/nsgpio.v       2008-05-09 01:45:48 UTC (rev 
8330)
@@ -1,3 +1,5 @@
+// Modified from code originally by Richard Herveille, his copyright is below
+
 /////////////////////////////////////////////////////////////////////
 ////                                                             ////
 ////  OpenCores Simple General Purpose IO core                   ////
@@ -37,12 +39,14 @@
   (input clk_i, input rst_i, 
    input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0] 
dat_i, 
    output reg [31:0] dat_o, output reg ack_o,
-   input [31:0] debug_0, input [31:0] debug_1, inout [31:0] gpio
+   input [31:0] atr, input [31:0] debug_0, input [31:0] debug_1, 
+   inout [31:0] gpio
    );
 
    reg [63:0]  ctrl;
    reg [31:0]  line;
    reg [31:0]  lgpio;               // LatchedGPIO pins
+   reg [31:0]  ddr;
    
    wire        wb_acc = cyc_i & stb_i;            // WISHBONE access
    wire        wb_wr  = wb_acc & we_i;            // WISHBONE write access
@@ -61,6 +65,8 @@
           ctrl[31:0] <= dat_i;
         2'b10 :
           ctrl[63:32] <= dat_i;
+        2'b11 :
+          ddr[31:0] <= dat_i;
        endcase // case( adr_i[3:2] )
    
    always @(posedge clk_i)
@@ -71,6 +77,8 @@
         dat_o <= ctrl[31:0];
        2'b10 :
         dat_o <= ctrl[63:32];
+       2'b11 :
+        dat_o <= ddr;
      endcase // case(adr_i[3:2])
    
    always @(posedge clk_i or posedge rst_i)
@@ -87,10 +95,11 @@
    integer   n;
    reg [31:0] igpio; // temporary internal signal
    
-   always @(ctrl or line or debug_1 or debug_0)
+   always @(ctrl or line or debug_1 or debug_0 or atr)
      for(n=0;n<32;n=n+1)
-       igpio[n] <= ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : debug_0[n]) : 
-          (ctrl[2*n] ?  line[n] : 1'bz);
+       igpio[n] <= ddr[n] ? (ctrl[2*n+1] ? (ctrl[2*n] ? debug_1[n] : 
debug_0[n]) : 
+                            (ctrl[2*n] ?  atr[n] : line[n]) )
+        : 1'bz;
    
    assign     gpio = igpio;