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[Commit-gnuradio] r8254 - usrp2/trunk/fpga/top/single_u2_sim
From: |
matt |
Subject: |
[Commit-gnuradio] r8254 - usrp2/trunk/fpga/top/single_u2_sim |
Date: |
Wed, 23 Apr 2008 15:03:56 -0600 (MDT) |
Author: matt
Date: 2008-04-23 15:03:56 -0600 (Wed, 23 Apr 2008)
New Revision: 8254
Modified:
usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v
Log:
use renamed u2_core instead of u2_basic
Modified: usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v
===================================================================
--- usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v 2008-04-23 21:01:46 UTC
(rev 8253)
+++ usrp2/trunk/fpga/top/single_u2_sim/single_u2_sim.v 2008-04-23 21:03:56 UTC
(rev 8254)
@@ -3,8 +3,7 @@
module single_u2_sim();
// Misc, debug
- wire led1;
- wire led2;
+ wire [7:0] leds;
wire [31:0] debug;
wire [1:0] debug_clk;
@@ -134,7 +133,7 @@
//`define CLK_DIV_3
`ifdef CLK_DIV_2
- localparam clock_divider = 2;
+ localparam clock_divider = 4'd2;
always @(posedge dsp_clk)
div_ctr <= div_ctr + 1;
assign div_clk = div_ctr[0];
@@ -222,19 +221,19 @@
// End the simulation
always @(posedge wb_clk)
- if((u2_basic.m0_we == 1'd1)&&(u2_basic.m0_adr == 16'hC2F0))
+ if((u2_core.m0_we == 1'd1)&&(u2_core.m0_adr == 16'hC2F0))
begin
$display($time, "Finish called.",);
$finish;
end
- u2_basic u2_basic(.dsp_clk (dsp_clk),
+ u2_core #(.RAM_SIZE(24576))
+ u2_core(.dsp_clk (dsp_clk),
.wb_clk (wb_clk),
.clock_ready (clock_ready),
.clk_to_mac (clk_to_mac),
.pps_in (pps_in),
- .led1 (led1),
- .led2 (led2),
+ .leds (leds),
.debug (debug[31:0]),
.debug_clk (debug_clk[1:0]),
.exp_pps_in (exp_pps_in),
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matt <=