[Commit-gnuradio] r7819 - usrp2/trunk/fpga/top/u2_basic

[matt]

Author: matt
Date: 2008-02-24 12:09:29 -0700 (Sun, 24 Feb 2008)
New Revision: 7819

Modified:
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
added serdes debugging stuff


Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-24 19:08:20 UTC (rev 
7818)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-24 19:09:29 UTC (rev 
7819)
@@ -146,7 +146,7 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc;
+   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc, 
debug_serdes0, debug_serdes1;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -566,7 +566,8 @@
       .rd_sop_i(rd0_sop),.rd_eop_i(rd0_eop),
       
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
       
.wr_dat_o(wr0_dat),.wr_write_o(wr0_write),.wr_done_o(wr0_done),.wr_error_o(wr0_error),
-      .wr_ready_i(wr0_ready),.wr_full_i(wr0_full) );
+      .wr_ready_i(wr0_ready),.wr_full_i(wr0_full),
+      .debug(debug_serdes0) );
 
    // 
///////////////////////////////////////////////////////////////////////////////////
    // External RAM Interface
@@ -602,17 +603,32 @@
                             irq[7:0],
                             proc_int,  7'b0 };
 
-                            
+   wire [31:0] debug_eth = 
+              
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+               {2'b0,iwb_adr[13:0]},
+               
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
+   /*
+   assign      debug_serdes0 = { { rd0_dat },
+                                { ser_tx_clk, ser_tkmsb, ser_tklsb, rd0_sop, 
rd0_eop, rd0_read, rd0_error, rd0_done },
+                                { ser_t[15:8] },
+                                { ser_t[7:0] } };
+   */
+   assign      debug_serdes1 = { 
{uart_tx_o,proc_int,underrun,buffer_int,wr0_ready,wr0_error,wr0_done,wr0_write},
+                                { 1'b0, ser_rx_clk, ser_rkmsb, ser_rklsb, 
ser_enable, ser_prbsen, ser_loopen, ser_rx_en },
+                                { ser_r[15:8] },
+                                { ser_r[7:0] } };
+   
    // Choose actual debug buses
-   assign      debug = debug_mac0;
+   assign      debug = debug_serdes0;
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    assign      debug_gpio_0 = 32'd0;  // Not used b/c of ATR
-   assign      debug_gpio_1 = debug_mac1;
+/*
+   assign      debug_gpio_1 = {uart_tx_o,7'd0,
+                              3'd0,rd1_sop,rd1_eop,rd1_read,rd1_done,rd1_error,
+                              debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
+*/
+   assign      debug_gpio_1 = debug_serdes1;
    
-   wire [31:0] debug_eth = 
-              
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
-               {2'b0,iwb_adr[13:0]},
-               
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
-   
 endmodule // u2_basic