[Commit-gnuradio] r7797 - in gnuradio/branches/developers/jcorgan/iqb/usrp: firmware/include fpga/sdr_lib fpga/toplevel/usrp_std

[jcorgan]

Author: jcorgan
Date: 2008-02-23 12:24:35 -0700 (Sat, 23 Feb 2008)
New Revision: 7797

Modified:
   
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
   
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
   gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v
   
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.v
Log:
Wired serial bus into block and added setting registers.

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
 2008-02-23 18:47:05 UTC (rev 7796)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.h
 2008-02-23 19:24:35 UTC (rev 7797)
@@ -182,9 +182,13 @@
 // 12 takes a bit more work, since we need to know packet alignment.
 
 // ------------------------------------------------------------------------
-// FIXME register numbers 50 to 63 are available
+// Transmitter I/Q balancer base register
+#define FR_TX_IQ_BALANCER_BASE 50
 
 // ------------------------------------------------------------------------
+// FIXME register numbers 53 to 63 are available
+
+// ------------------------------------------------------------------------
 // Registers 64 to 95 are reserved for user custom FPGA builds.
 // The standard USRP software will not touch these.
 

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
 2008-02-23 18:47:05 UTC (rev 7796)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/firmware/include/fpga_regs_standard.v
 2008-02-23 19:24:35 UTC (rev 7797)
@@ -1,5 +1,5 @@
 //
-// This file is machine generated from fpga_regs_standard.h
+// This file is machine generated from ./fpga_regs_standard.h
 // Do not edit by hand; your edits will be overwritten.
 //
 
@@ -154,9 +154,13 @@
 // 12 takes a bit more work, since we need to know packet alignment.
 
 // ------------------------------------------------------------------------
-// FIXME register numbers 50 to 63 are available
+// Transmitter I/Q balancer base register
+`define FR_TX_IQ_BALANCER_BASE    7'd50
 
 // ------------------------------------------------------------------------
+// FIXME register numbers 53 to 63 are available
+
+// ------------------------------------------------------------------------
 // Registers 64 to 95 are reserved for user custom FPGA builds.
 // The standard USRP software will not touch these.
 

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v
===================================================================
--- gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
2008-02-23 18:47:05 UTC (rev 7796)
+++ gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/iq_balancer.v    
2008-02-23 19:24:35 UTC (rev 7797)
@@ -19,18 +19,54 @@
 //  Foundation, Inc., 51 Franklin Street, Boston, MA  02110-1301  USA
 //
 
-module iq_balancer(input clock, 
-                  input enable, 
-                  input reset,
-                  input signed [15:0] i_in, 
-                  input signed [15:0] q_in,
-                  output signed [15:0] i_out, 
-                  output signed [15:0] q_out,
-                  input wire [6:0] serial_addr, 
-                  input wire [31:0] serial_data, 
-                  input serial_strobe);
+module iq_balancer
+  # (parameter REGBASE=0)
+    (input clock, 
+     input enable, 
+     input reset,
+     input signed [15:0] i_in, 
+     input signed [15:0] q_in,
+     output signed [15:0] i_out, 
+     output signed [15:0] q_out,
+     input wire [6:0] serial_addr, 
+     input wire [31:0] serial_data, 
+     input serial_strobe);
 
-    assign i_out = i_in;
-    assign q_out = q_in;
+   localparam OFFSET_ADDR = REGBASE + 0;
+   localparam MAG_ADDR    = REGBASE + 1;
+   localparam PHASE_ADDR  = REGBASE + 2;
 
+   wire [15:0] i_offset;
+   wire [15:0] q_offset;
+   wire [15:0] i_mag;
+   wire [15:0] i_phase_k;
+   wire [15:0] q_phase_k;
+   
+   setting_reg #(OFFSET_ADDR) sr_offset
+     (.clock(clock),
+      .reset(reset),
+      .strobe(serial_strobe),
+      .addr(serial_addr),
+      .in(serial_data),
+      .out({i_offset,q_offset}) );
+
+   setting_reg #(MAG_ADDR) sr_mag
+     (.clock(clock),
+      .reset(reset),
+      .strobe(serial_strobe),
+      .addr(serial_addr),
+      .in(serial_data),
+      .out(i_mag) );
+
+   setting_reg #(PHASE_ADDR) sr_phase
+     (.clock(clock),
+      .reset(reset),
+      .strobe(serial_strobe),
+      .addr(serial_addr),
+      .in(serial_data),
+      .out({i_phase_k,q_phase_k}) );
+
+   assign i_out = i_in;
+   assign q_out = q_in;
+
 endmodule // iq_balancer

Modified: gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v
===================================================================
--- gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v       
2008-02-23 18:47:05 UTC (rev 7796)
+++ gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/sdr_lib/tx_chain.v       
2008-02-23 19:24:35 UTC (rev 7797)
@@ -30,7 +30,10 @@
    input wire [15:0] i_in,
    input wire [15:0] q_in,
    output wire [15:0] i_out,
-   output wire [15:0] q_out
+   output wire [15:0] q_out,
+   input wire [6:0] serial_addr, 
+   input wire [31:0] serial_data, 
+   input serial_strobe
    );
 
    wire [15:0] bb_i, bb_q;
@@ -64,13 +67,17 @@
 `endif
 
 `ifdef TX_IQB_ON
-   iq_balancer tx_iq_balancer(.clock(clock),
-                             .enable(enable),
-                             .reset(reset),
-                             .i_in(bb_i_bal),
-                             .q_in(bb_q_bal),
-                             .i_out(i_out),
-                             .q_out(q_out) );
+   iq_balancer #(.REGBASE(`FR_TX_IQ_BALANCER_BASE)) tx_iq_balancer
+     (.clock(clock),
+      .enable(enable),
+      .reset(reset),
+      .i_in(bb_i_bal),
+      .q_in(bb_q_bal),
+      .i_out(i_out),
+      .q_out(q_out),
+      .serial_addr(serial_addr),
+      .serial_data(serial_data),
+      .serial_strobe(serial_strobe) );
 `else
     assign i_out = bb_i_bal;
     assign q_out = bb_q_bal;

Modified: 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.v
===================================================================
--- 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.v 
    2008-02-23 18:47:05 UTC (rev 7796)
+++ 
gnuradio/branches/developers/jcorgan/iqb/usrp/fpga/toplevel/usrp_std/usrp_std.v 
    2008-02-23 19:24:35 UTC (rev 7797)
@@ -146,7 +146,8 @@
      ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
        .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
        .interpolator_strobe(strobe_interp),.freq(),
-       .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0) );
+       .i_in(bb_tx_i0),.q_in(bb_tx_q0),.i_out(i_out_0),.q_out(q_out_0),
+       
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)
 );
  `else
    assign      i_out_0=16'd0;
    assign      q_out_0=16'd0;
@@ -157,7 +158,8 @@
      ( .clock(clk64),.reset(tx_dsp_reset),.enable(enable_tx),
        .interp_rate(interp_rate),.sample_strobe(tx_sample_strobe),
        .interpolator_strobe(strobe_interp),.freq(),
-       .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1) );
+       .i_in(bb_tx_i1),.q_in(bb_tx_q1),.i_out(i_out_1),.q_out(q_out_1),
+       
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)
 );
  `else
    assign      i_out_1=16'd0;
    assign      q_out_1=16'd0;