[Commit-gnuradio] r7750 - in gnuradio/branches/features/inband-usb/usrp/fpga: inband_lib toplevel/usrp_inband_usb

[gnychis]

Author: gnychis
Date: 2008-02-20 00:12:52 -0700 (Wed, 20 Feb 2008)
New Revision: 7750

Modified:
   gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
   gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
   gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
   
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
   
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Merging -r7568:7749 from developers/zhuochen/inband for dual RX and TX support
in inband code


Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v 
2008-02-20 07:10:15 UTC (rev 7749)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v 
2008-02-20 07:12:52 UTC (rev 7750)
@@ -1,4 +1,4 @@
-module packet_builder #(parameter NUM_CHAN = 1)(
+module packet_builder #(parameter NUM_CHAN = 2)(
     // System
     input rxclk,
     input reset,

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v    
2008-02-20 07:10:15 UTC (rev 7749)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v    
2008-02-20 07:12:52 UTC (rev 7750)
@@ -98,7 +98,7 @@
    assign bundle[43] = {24'd0, rxb_refclk};  
 
        reg strobe;
-       wire [31:0] out[7:0];
+       wire [31:0] out[2:1];
        assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
        assign threshhold = out[1];
        assign rssi_wait = out[2];
@@ -117,7 +117,7 @@
                     //read
                                if (addr <= 7'd43)
                                        dataout <= bundle[addr];
-                               else if (addr <= 7'd57 && addr >= 7'd50)
+                               else if (addr <= 7'd52 && addr > 7'd50)
                                        dataout <= out[addr-7'd50];
                                else
                                        dataout <= 32'hFFFFFFFF;        
@@ -134,13 +134,13 @@
           end
 
 //register declarations
-    setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
-    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));
+    /*setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[0]));*/
     setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[1]));
     setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[2]));
-    setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+    /*setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[3]));
     setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[4]));
@@ -149,5 +149,6 @@
     setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
     .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[6]));
     setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
-    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));
+    .strobe(strobe_wr),.addr(addr_wr),.in(data_wr),.out(out[7]));*/
+
 endmodule      

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v   
    2008-02-20 07:10:15 UTC (rev 7749)
+++ 
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v   
    2008-02-20 07:12:52 UTC (rev 7750)
@@ -1,201 +1,205 @@
-//`include "../../firmware/include/fpga_regs_common.v"
-//`include "../../firmware/include/fpga_regs_standard.v"
-module rx_buffer_inband
-  ( input usbclk,
-    input bus_reset,
-    input reset,  // DSP side reset (used here), do not reset registers
-    input reset_regs, //Only reset registers
-    output [15:0] usbdata,
-    input RD,
-    output wire have_pkt_rdy,
-    output reg rx_overrun,
-    input wire [3:0] channels,
-    input wire [15:0] ch_0,
-    input wire [15:0] ch_1,
-    input wire [15:0] ch_2,
-    input wire [15:0] ch_3,
-    input wire [15:0] ch_4,
-    input wire [15:0] ch_5,
-    input wire [15:0] ch_6,
-    input wire [15:0] ch_7,
-    input rxclk,
-    input rxstrobe,
-    input clear_status,
-    input [6:0] serial_addr, 
-    input [31:0] serial_data, 
-    input serial_strobe,
-    output wire [15:0] debugbus,
-       
-    //Connection with tx_inband
-    input rx_WR,
-    input [15:0] rx_databus,
-    input rx_WR_done,
-    output reg rx_WR_enabled,
-    //signal strength
-    input wire [31:0] rssi_0, input wire [31:0] rssi_1,
-    input wire [31:0] rssi_2, input wire [31:0] rssi_3,
-    input wire [1:0] tx_underrun
-    );
-    
-    parameter NUM_CHAN = 1;
-    genvar i ;
-    
-    // FX2 Bug Fix
-    reg [8:0] read_count;
-    always @(negedge usbclk)
-        if(bus_reset)
-            read_count <= #1 9'd0;
-        else if(RD & ~read_count[8])
-            read_count <= #1 read_count + 9'd1;
-        else
-            read_count <= #1 RD ? read_count : 9'b0;
-       
-       // Time counter
-       reg [31:0] adctime;
-       always @(posedge rxclk)
-               if (reset)
-                       adctime <= 0;
-               else if (rxstrobe)
-                       adctime <= adctime + 1;
-     
-  // USB side fifo
-  wire [11:0] rdusedw;
-  wire [11:0] wrusedw;
-  wire [15:0] fifodata;
-  wire [15:0] fifodata_il;
-  reg [15:0] fifodata_16;
-  wire WR;
-  wire have_space;
-
-  assign fifodata_il = fifodata_16;
-
-  fifo_4kx16_dc        rx_usb_fifo (
-    .aclr ( reset ),
-    .data ( fifodata ),
-    .rdclk ( ~usbclk ),
-    .rdreq ( RD & ~read_count[8] ),
-    .wrclk ( rxclk ),
-    .wrreq ( WR ),
-    .q ( usbdata ),
-    .rdempty (  ),
-    .rdusedw ( rdusedw ),
-    .wrfull (  ),
-    .wrusedw ( wrusedw ) );
-    
-  assign have_pkt_rdy = (rdusedw >= 12'd256);
-  assign have_space = (wrusedw < 12'd760);
-        
-  // Rx side fifos
-  wire chan_rdreq;
-  wire [15:0] chan_fifodata;
-  wire [9:0] chan_usedw;
-  wire [NUM_CHAN:0] chan_empty;
-  wire [3:0] rd_select;
-  wire [NUM_CHAN:0] rx_full;
-        
-  packet_builder #(NUM_CHAN) rx_pkt_builer (
-    .rxclk ( rxclk ),
-    .reset ( reset ),
-    .adctime ( adctime ),
-    .channels ( 4'd1 ), //need to be tested and changed to channels 
-    .chan_rdreq ( chan_rdreq ),
-    .chan_fifodata ( chan_fifodata ),
-    .chan_empty ( chan_empty ),
-    .rd_select ( rd_select ),
-    .chan_usedw ( chan_usedw ),
-    .WR ( WR ),
-    .fifodata ( fifodata ),
-    .have_space ( have_space ),
-      .rssi_0(rssi_0), .rssi_1(rssi_1),
-      .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
-      .underrun(tx_underrun));
-        
-  // Detect overrun
-  always @(posedge rxclk)
-    if(reset)
-      rx_overrun <= 1'b0;
-    else if(rx_full[0])
-      rx_overrun <= 1'b1;
-    else if(clear_status)
-      rx_overrun <= 1'b0;
-
-               
-  // TODO write this genericly
-  wire [15:0]ch[NUM_CHAN:0];
-  assign ch[0] = ch_0;
-       
-  wire cmd_empty;
-       
-  always @(posedge rxclk)
-    if(reset)
-      rx_WR_enabled <= 1;
-    else if(cmd_empty)
-      rx_WR_enabled <= 1;
-    else if(rx_WR_done)
-      rx_WR_enabled <= 0;
-
-  // Switching of channels
-  reg [3:0] store_next;
-  always @(posedge rxclk)
-  if(reset)
-    store_next <= #1 4'd0;
-  else if(rxstrobe & (store_next == 0))
-    store_next <= #1 4'd1;
-  else if(~rx_full & (store_next == 4'd2))
-    store_next <= #1 4'd0;
-  else if(~rx_full & (store_next != 0))
-    store_next <= #1 store_next + 4'd1;
-
-  always @*
-    case(store_next)
-      4'd1 : fifodata_16 = ch_0;
-      4'd2 : fifodata_16 = ch_1;
-      default: fifodata_16 = 16'hFFFF;
-    endcase
-
-  wire [15:0] dataout [0:NUM_CHAN];
-  wire [9:0]  usedw    [0:NUM_CHAN];
-  wire empty[0:NUM_CHAN];
-       
-  generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
-    begin : generate_channel_fifos
-
-      wire rdreq;
-
-      assign rdreq = (rd_select == i) & chan_rdreq;
-
-      fifo_1kx16 rx_chan_fifo (
-      .aclr ( reset ),
-      .clock ( rxclk ),
-      .data ( fifodata_il ),
-      .rdreq ( rdreq ),
-      .wrreq ( ~rx_full[i] & (store_next != 0)),
-      .empty (empty[i]),
-      .full (rx_full[i]),
-      .q ( dataout[i]),
-      .usedw ( usedw[i]),
-      .almost_empty(chan_empty[i])
-      );
-    end
-  endgenerate
-       
-  wire [7:0] debug;
-        
-  fifo_1kx16 rx_cmd_fifo (
-    .aclr ( reset ),
-    .clock ( rxclk ),
-    .data ( rx_databus ),
-    .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
-    .wrreq ( rx_WR & rx_WR_enabled),
-    .empty ( cmd_empty),
-    .full ( rx_full[NUM_CHAN] ),
-    .q ( dataout[NUM_CHAN]),
-    .usedw ( usedw[NUM_CHAN] )
-  );
-       
-  assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
-  assign chan_fifodata = dataout[rd_select];
-  assign chan_usedw = usedw[rd_select];
-  assign debugbus = {4'd0, rxclk, rxstrobe, store_next[3], store_next[1], 
store_next[0]};
-
-endmodule
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+module rx_buffer_inband
+  ( input usbclk,
+    input bus_reset,
+    input reset,  // DSP side reset (used here), do not reset registers
+    input reset_regs, //Only reset registers
+    output [15:0] usbdata,
+    input RD,
+    output wire have_pkt_rdy,
+    output reg rx_overrun,
+    input wire [3:0] channels,
+    input wire [15:0] ch_0,
+    input wire [15:0] ch_1,
+    input wire [15:0] ch_2,
+    input wire [15:0] ch_3,
+    input wire [15:0] ch_4,
+    input wire [15:0] ch_5,
+    input wire [15:0] ch_6,
+    input wire [15:0] ch_7,
+    input rxclk,
+    input rxstrobe,
+    input clear_status,
+    input [6:0] serial_addr, 
+    input [31:0] serial_data, 
+    input serial_strobe,
+    output wire [15:0] debugbus,
+       
+    //Connection with tx_inband
+    input rx_WR,
+    input [15:0] rx_databus,
+    input rx_WR_done,
+    output reg rx_WR_enabled,
+    //signal strength
+    input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+    input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+    input wire [1:0] tx_underrun
+    );
+    
+    parameter NUM_CHAN = 2;
+    genvar i ;
+    
+    // FX2 Bug Fix
+    reg [8:0] read_count;
+    always @(negedge usbclk)
+        if(bus_reset)
+            read_count <= #1 9'd0;
+        else if(RD & ~read_count[8])
+            read_count <= #1 read_count + 9'd1;
+        else
+            read_count <= #1 RD ? read_count : 9'b0;
+       
+       // Time counter
+       reg [31:0] adctime;
+       always @(posedge rxclk)
+               if (reset)
+                       adctime <= 0;
+               else if (rxstrobe)
+                       adctime <= adctime + 1;
+     
+  // USB side fifo
+  wire [11:0] rdusedw;
+  wire [11:0] wrusedw;
+  wire [15:0] fifodata;
+  wire [15:0] fifodata_il[0:NUM_CHAN];
+  wire WR;
+  wire have_space;
+  reg sel;
+  reg wr;
+
+  always@(posedge rxclk)
+    begin
+      if(reset)
+        begin
+          sel<=1;
+          wr<=0;
+        end
+      else if(rxstrobe)
+        begin
+          sel<=0;
+          wr<=1;
+        end
+      else if(wr&~sel)
+          sel<=1;
+      else if(wr&sel)
+          wr<=0;
+      else
+          wr<=0;
+    end
+
+  assign fifodata_il[0] = (sel)?ch_1:ch_0;
+  assign fifodata_il[1] = (sel)?ch_3:ch_2;
+
+  fifo_4kx16_dc        rx_usb_fifo (
+    .aclr ( reset ),
+    .data ( fifodata ),
+    .rdclk ( ~usbclk ),
+    .rdreq ( RD & ~read_count[8] ),
+    .wrclk ( rxclk ),
+    .wrreq ( WR ),
+    .q ( usbdata ),
+    .rdempty (  ),
+    .rdusedw ( rdusedw ),
+    .wrfull (  ),
+    .wrusedw ( wrusedw ) );
+    
+  assign have_pkt_rdy = (rdusedw >= 12'd256);
+  assign have_space = (wrusedw < 12'd760);
+        
+  // Rx side fifos
+  wire chan_rdreq;
+  wire [15:0] chan_fifodata;
+  wire [9:0] chan_usedw;
+  wire [NUM_CHAN:0] chan_empty;
+  wire [3:0] rd_select;
+  wire [NUM_CHAN:0] rx_full;
+        
+  packet_builder #(NUM_CHAN) rx_pkt_builer (
+    .rxclk ( rxclk ),
+    .reset ( reset ),
+    .adctime ( adctime ),
+    .channels ( 4'd2 ), //need to be tested and changed to channels 
+    .chan_rdreq ( chan_rdreq ),
+    .chan_fifodata ( chan_fifodata ),
+    .chan_empty ( chan_empty ),
+    .rd_select ( rd_select ),
+    .chan_usedw ( chan_usedw ),
+    .WR ( WR ),
+    .fifodata ( fifodata ),
+    .have_space ( have_space ),
+      .rssi_0(rssi_0), .rssi_1(rssi_1),
+      .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
+      .underrun(tx_underrun));
+        
+  // Detect overrun
+  always @(posedge rxclk)
+    if(reset)
+      rx_overrun <= 1'b0;
+    else if(rx_full[0])
+      rx_overrun <= 1'b1;
+    else if(clear_status)
+      rx_overrun <= 1'b0;
+
+               
+  // TODO write this genericly
+  wire [15:0]ch[NUM_CHAN:0];
+  assign ch[0] = ch_0;
+       
+  wire cmd_empty;
+       
+  always @(posedge rxclk)
+    if(reset)
+      rx_WR_enabled <= 1;
+    else if(cmd_empty)
+      rx_WR_enabled <= 1;
+    else if(rx_WR_done)
+      rx_WR_enabled <= 0;
+
+
+  wire [15:0] dataout [0:NUM_CHAN];
+  wire [9:0]  usedw    [0:NUM_CHAN];
+  wire empty[0:NUM_CHAN];
+       
+  generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+    begin : generate_channel_fifos
+
+      wire rdreq;
+
+      assign rdreq = (rd_select == i) & chan_rdreq;
+
+      fifo_1kx16 rx_chan_fifo (
+      .aclr ( reset ),
+      .clock ( rxclk ),
+      .data ( fifodata_il[i] ),
+      .rdreq ( rdreq ),
+      .wrreq ( ~rx_full[i] & wr),
+      .empty (empty[i]),
+      .full (rx_full[i]),
+      .q ( dataout[i]),
+      .usedw ( usedw[i]),
+      .almost_empty(chan_empty[i])
+      );
+    end
+  endgenerate
+       
+  wire [7:0] debug;
+        
+  fifo_1kx16 rx_cmd_fifo (
+    .aclr ( reset ),
+    .clock ( rxclk ),
+    .data ( rx_databus ),
+    .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+    .wrreq ( rx_WR & rx_WR_enabled),
+    .empty ( cmd_empty),
+    .full ( rx_full[NUM_CHAN] ),
+    .q ( dataout[NUM_CHAN]),
+    .usedw ( usedw[NUM_CHAN] )
+  );
+       
+  assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+  assign chan_fifodata = dataout[rd_select];
+  assign chan_usedw = usedw[rd_select];
+  assign debugbus = {4'd0, rxclk, rxstrobe, rx_full[0], rx_full[1], sel, wr};
+
+endmodule

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
===================================================================
--- 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
  2008-02-20 07:10:15 UTC (rev 7749)
+++ 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/config.vh
  2008-02-20 07:12:52 UTC (rev 7750)
@@ -31,10 +31,10 @@
 // ====================================================================
 
 // Uncomment this for 1 rx channel (w/ halfband) & 1 transmit channel
-//  `include "../include/common_config_1rxhb_1tx.vh"
+  `include "../include/common_config_1rxhb_1tx.vh"
 
 // Uncomment this for 2 rx channels (w/ halfband) & 2 transmit channels
-  `include "../include/common_config_2rxhb_2tx.vh"
+//  `include "../include/common_config_2rxhb_2tx.vh"
 
 // Uncomment this for 4 rx channels (w/o halfband) & 0 transmit channels
 //`include "../include/common_config_4rx_0tx.vh"

Modified: 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
  2008-02-20 07:10:15 UTC (rev 7749)
+++ 
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
  2008-02-20 07:12:52 UTC (rev 7750)
@@ -150,7 +150,7 @@
           .reg_data_out(reg_data_out),
           .reg_data_in(reg_data_in),
           .reg_io_enable(reg_io_enable),
-          .debugbus(tx_debugbus),
+          .debugbus(rx_debugbus),
           .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
        .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
           .stop(stop), .stop_time(stop_time));
@@ -267,7 +267,7 @@
           .rx_databus(rx_databus),
           .rx_WR_done(rx_WR_done),
           .rx_WR_enabled(rx_WR_enabled),
-          .debugbus(rx_debugbus),
+          .debugbus(tx_debugbus),
           .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
           .tx_underrun(tx_underrun));
    `else