[Commit-gnuradio] r7706 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx

[matt]

Author: matt
Date: 2008-02-15 11:39:16 -0700 (Fri, 15 Feb 2008)
New Revision: 7706

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
Log:
last ditch attempt to use the old fifo.  Double-registering the addresses to 
see if this helps


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-02-15 18:23:16 UTC 
(rev 7705)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-02-15 18:39:16 UTC 
(rev 7706)
@@ -101,11 +101,13 @@
 reg [TX_FF_DEPTH-1:0]       Add_wr_ungray   ;
 reg [TX_FF_DEPTH-1:0]       Add_wr_gray     ;
 reg [TX_FF_DEPTH-1:0]       Add_wr_gray_dl1 ;
+reg [TX_FF_DEPTH-1:0]       Add_wr_gray_dl2 ;
 
 reg [TX_FF_DEPTH-1:0]       Add_rd          ;
 reg [TX_FF_DEPTH-1:0]       Add_rd_reg      ;
 reg [TX_FF_DEPTH-1:0]       Add_rd_gray     ;
 reg [TX_FF_DEPTH-1:0]       Add_rd_gray_dl1 ;
+reg [TX_FF_DEPTH-1:0]       Add_rd_gray_dl2 ;
 reg [TX_FF_DEPTH-1:0]       Add_rd_ungray   ;
 wire[35:0]      Din             ;
 wire[35:0]      Dout            ;
@@ -262,7 +264,13 @@
         Add_rd_gray_dl1         <=0;
     else
         Add_rd_gray_dl1         <=Add_rd_gray;
-                    
+
+   always @(posedge Clk_SYS or posedge Reset)
+     if (Reset)
+       Add_rd_gray_dl2 <= 0;
+     else
+       Add_rd_gray_dl2 <= Add_rd_gray_dl1;
+   
 always @ (posedge Clk_SYS or posedge Reset)
     if (Reset)
         Add_rd_jump_wr_pl1  <=0;
@@ -275,9 +283,9 @@
     else if (!Add_rd_jump_wr_pl1)       
       begin : Add_rd_ungray_loop
         integer i;
-       Add_rd_ungray[TX_FF_DEPTH-1] = Add_rd_gray_dl1[TX_FF_DEPTH-1];
+       Add_rd_ungray[TX_FF_DEPTH-1] = Add_rd_gray_dl2[TX_FF_DEPTH-1];
        for (i=TX_FF_DEPTH-2;i>=0;i=i-1)
-         Add_rd_ungray[i] = Add_rd_ungray[i+1]^Add_rd_gray_dl1[i];
+         Add_rd_ungray[i] = Add_rd_ungray[i+1]^Add_rd_gray_dl2[i];
       end
 
 assign          Add_wr_pluse        =Add_wr+1;
@@ -521,6 +529,12 @@
         Add_wr_gray_dl1     <=0;
     else
         Add_wr_gray_dl1     <=Add_wr_gray;
+
+always @ (posedge Clk_MAC or posedge Reset)
+    if (Reset)
+        Add_wr_gray_dl2     <=0;
+    else
+        Add_wr_gray_dl2     <=Add_wr_gray_dl1;
             
 always @ (posedge Clk_MAC or posedge Reset)
     if (Reset)
@@ -528,9 +542,9 @@
     else        
       begin : Add_wr_ungray_loop
         integer i;
-       Add_wr_ungray[TX_FF_DEPTH-1] = Add_wr_gray_dl1[TX_FF_DEPTH-1];
+       Add_wr_ungray[TX_FF_DEPTH-1] = Add_wr_gray_dl2[TX_FF_DEPTH-1];
        for (i=TX_FF_DEPTH-2;i>=0;i=i-1)
-         Add_wr_ungray[i] = Add_wr_ungray[i+1]^Add_wr_gray_dl1[i];     
+         Add_wr_ungray[i] = Add_wr_ungray[i+1]^Add_wr_gray_dl2[i];     
       end           
 
 //empty