[Commit-gnuradio] r7669 - in usrp2/trunk/fpga: sdr_lib top/u2_basic

[matt]

Author: matt
Date: 2008-02-13 19:06:28 -0700 (Wed, 13 Feb 2008)
New Revision: 7669

Modified:
   usrp2/trunk/fpga/sdr_lib/rx_control.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
use new send_imm and chain flags, to allow for streaming and knowing when 
streaming fails


Modified: usrp2/trunk/fpga/sdr_lib/rx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/rx_control.v       2008-02-14 02:04:53 UTC (rev 
7668)
+++ usrp2/trunk/fpga/sdr_lib/rx_control.v       2008-02-14 02:06:28 UTC (rev 
7669)
@@ -32,7 +32,9 @@
    wire [31:0]            rcvtime_pre;
    reg [31:0]     rcvtime;
    wire [8:0]     lines_per_frame;
-   wire [22:0]            numlines;
+   wire [20:0]            numlines;
+   wire           send_imm_pre, chain_pre;
+   reg                    send_imm, chain;
    wire           full_ctrl, read_ctrl, empty_ctrl, write_ctrl;
 
    setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr_3
@@ -54,8 +56,9 @@
    
    shortfifo #(.WIDTH(64)) commandfifo
      (.clk(clk),.rst(rst),.clear(clear_overrun),
-      .datain({new_time,new_command}), .write(write_ctrl), .full(full_ctrl),
-      .dataout({rcvtime_pre,numlines,lines_per_frame}), .read(read_ctrl), 
.empty(empty_ctrl) );
+      .datain({new_command,new_time}), .write(write_ctrl), .full(full_ctrl),
+      .dataout({send_imm_pre,chain_pre,numlines,lines_per_frame,rcvtime_pre}), 
+      .read(read_ctrl), .empty(empty_ctrl) );
 
    // Buffer interface to internal FIFO
    wire    write, full, read, empty;
@@ -109,8 +112,8 @@
    reg [2:0] ibs_state;
   
    wire [32:0] delta_time = {1'b0,rcvtime}-{1'b0,master_time};
-   wire        too_late = (delta_time[32:31] == 2'b11) & ~(rcvtime == 
32'hFFFF_FFFF);
-   wire        go_now = ( master_time == rcvtime ) | (rcvtime == 
32'hFFFF_FFFF);
+   wire        too_late = (delta_time[32:31] == 2'b11) & ~send_imm;
+   wire        go_now = send_imm | ( master_time == rcvtime );
  
    always @(posedge clk)
      if(rst)
@@ -119,6 +122,8 @@
          lines_left <= 0;
          lines_left_frame <= 0;
          rcvtime <= 0;
+         send_imm <= 0;
+         chain <= 0;
        end
      else
        if(clear_overrun)
@@ -127,6 +132,8 @@
          lines_left <= 0;
          lines_left_frame <= 0;
          rcvtime <= 0;
+         send_imm <= 0;
+         chain <= 0;
         end
        else 
         case(ibs_state)
@@ -137,6 +144,8 @@
                  lines_left_frame <= lines_per_frame;
                  rcvtime <= rcvtime_pre;
                  ibs_state <= IBS_WAITING;
+                 send_imm <= send_imm_pre;
+                 chain <= chain_pre;
               end
           IBS_WAITING :
             if(go_now)
@@ -156,7 +165,19 @@
                 begin
                    lines_left <= lines_left - 1;
                    if(lines_left == 1)
-                     ibs_state <= IBS_IDLE;
+                     if(~chain)
+                       ibs_state <= IBS_IDLE;
+                     else if(empty_ctrl)
+                       ibs_state <= IBS_OVERRUN;
+                     else
+                       begin
+                          lines_left <= numlines;
+                          lines_left_frame <= lines_per_frame;
+                          rcvtime <= rcvtime_pre;
+                          ibs_state <= IBS_FIRSTLINE;
+                          send_imm <= send_imm_pre;
+                          chain <= chain_pre;
+                       end
                    else if(lines_left_frame == 1)
                      begin
                         lines_left_frame <= lines_per_frame;
@@ -173,9 +194,11 @@
    assign write = ((ibs_state == IBS_FIRSTLINE) | strobe) & ~full;  // & 
(ibs_state == IBS_RUNNING) should strobe only when running
    assign overrun = (ibs_state == IBS_OVERRUN);
    assign run = (ibs_state == IBS_RUNNING) | (ibs_state == IBS_FIRSTLINE);
-   assign read_ctrl = (ibs_state == IBS_IDLE) & ~empty_ctrl;
+   assign read_ctrl = ( (ibs_state == IBS_IDLE) | 
+                       ((ibs_state == IBS_RUNNING) & strobe & ~full & 
(lines_left==1) & chain) )
+         & ~empty_ctrl;
    
-   assign debug_rx = { 8'd0,
+   assign debug_rx = { 6'd0,send_imm,chain,
                       wr_write_o, wr_done_o, wr_ready_i, 
wr_full_i,xfer_state,eop_o, sop_o, run,
                       
write,full,read,empty,write_ctrl,full_ctrl,read_ctrl,empty_ctrl,
                       sc_pre1, clear_overrun, go_now, too_late, overrun, 
ibs_state[2:0] };

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-14 02:04:53 UTC (rev 
7668)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-14 02:06:28 UTC (rev 
7669)
@@ -608,7 +608,7 @@
    assign      debug_clk[0] = wb_clk;
    assign      debug_clk[1] = dsp_clk; 
    assign      debug_gpio_0 = 32'd0;  // Not used b/c of ATR
-   assign      debug_gpio_1 = {16'd0,debug_txc[15:0]};
+   assign      debug_gpio_1 = debug_rx;
    
    wire [31:0] debug_eth = 
               
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},