[Commit-gnuradio] r7646 - usrp2/trunk/fpga/sdr_lib

[matt]

Author: matt
Date: 2008-02-12 01:25:37 -0700 (Tue, 12 Feb 2008)
New Revision: 7646

Added:
   usrp2/trunk/fpga/sdr_lib/add2_and_round.v
   usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
Log:
only minimally tested at this point


Added: usrp2/trunk/fpga/sdr_lib/add2_and_round.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/add2_and_round.v                           (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/add2_and_round.v   2008-02-12 08:25:37 UTC (rev 
7646)
@@ -0,0 +1,11 @@
+
+module add2_and_round
+  #(parameter WIDTH=16)
+    (input [WIDTH-1:0] in1,
+     input [WIDTH-1:0] in2,
+     output [WIDTH-1:0] sum);
+
+   wire [WIDTH:0]      sum_int = {in1[WIDTH-1],in1} + {in2[WIDTH-1],in2};
+   assign              sum = sum_int[WIDTH:1] + (sum_int[WIDTH] & sum_int[0]);
+   
+endmodule // add2_and_round

Added: usrp2/trunk/fpga/sdr_lib/small_hb_dec.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/small_hb_dec.v                             (rev 0)
+++ usrp2/trunk/fpga/sdr_lib/small_hb_dec.v     2008-02-12 08:25:37 UTC (rev 
7646)
@@ -0,0 +1,86 @@
+// Short halfband decimator (intended to be followed by another stage)
+// Implements impulse responses of the form [A 0 B 0.5 B 0 A]
+//
+// These taps designed by halfgen4 from ldoolittle:
+//   2 * 131072 * halfgen4(.75/8,2)
+module small_hb_dec
+  #(parameter WIDTH=18)
+    (input clk,
+     input rst,
+     input bypass,
+     input stb_in,
+     input [WIDTH-1:0] data_in,
+     output reg stb_out,
+     output [WIDTH-1:0] data_out);
+
+   wire                go;
+   reg                         phase, go_d1, go_d2, go_d3, go_d4;
+   always @(posedge clk)
+     if(rst)
+       phase <= 0;
+     else if(stb_in)
+       phase <= ~phase;
+   assign              go = stb_in & phase;
+   always @(posedge clk) go_d1 <= go;
+   always @(posedge clk) go_d2 <= go_d1;
+   always @(posedge clk) go_d3 <= go_d2;
+   always @(posedge clk) go_d4 <= go_d3;
+
+   wire [17:0]                 coeff_a = -10690;
+   wire [17:0]                 coeff_b = 75809;
+   
+   reg [WIDTH-1:0]     d1, d2, d3, d4 , d5, d6;
+   always @(posedge clk)
+     if(stb_in | rst)
+       begin
+         d1 <= data_in;
+         d2 <= d1;
+         d3 <= d2;
+         d4 <= d3;
+         d5 <= d4;
+         d6 <= d5;
+       end
+
+   reg [17:0] sum_a, sum_b, middle, middle_d1;
+   always @(posedge clk)
+     if(go)
+       begin
+         sum_a <= data_in + d6;
+         sum_b <= d2 + d4;
+         middle <= d3;
+       end
+
+   always @(posedge clk)
+     if(go_d1)
+       middle_d1 <= middle;
+   
+   wire [17:0] sum = go_d1 ? sum_b : sum_a;
+   wire [17:0] coeff = go_d1 ? coeff_b : coeff_a;
+   wire [35:0]          prod;   
+   MULT18X18S mult(.C(clk), .CE(go_d1 | go_d2), .R(rst), .P(prod), .A(coeff), 
.B(sum) );
+   
+   reg [35:0]   accum;
+   always @(posedge clk)
+     if(rst)
+       accum <= 0;
+     else if(go_d2)
+       accum <= {middle_d1[17],middle_d1,17'd0} + {prod};
+     else if(go_d3)
+       accum <= accum + {prod};
+   
+   wire [17:0]          accum_rnd;
+   round #(.bits_in(36),.bits_out(18)) round_acc (.in(accum),.out(accum_rnd));
+
+   reg [17:0]   final_sum;
+   always @(posedge clk)
+     if(go_d4)
+       final_sum <= accum_rnd;
+
+   assign       data_out = final_sum;
+
+   always @(posedge clk)
+     if(rst)
+       stb_out <= 0;
+     else
+       stb_out <= go_d4;
+endmodule // small_hb_dec