[Commit-gnuradio] r7613 - usrp2/trunk/fpga/eth

[matt]

Author: matt
Date: 2008-02-08 14:39:16 -0700 (Fri, 08 Feb 2008)
New Revision: 7613

Modified:
   usrp2/trunk/fpga/eth/mac_rxfifo_int.v
Log:
really back out the bad changes


Modified: usrp2/trunk/fpga/eth/mac_rxfifo_int.v
===================================================================
--- usrp2/trunk/fpga/eth/mac_rxfifo_int.v       2008-02-08 21:37:49 UTC (rev 
7612)
+++ usrp2/trunk/fpga/eth/mac_rxfifo_int.v       2008-02-08 21:39:16 UTC (rev 
7613)
@@ -21,42 +21,21 @@
    //   Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err, 
Rx_mac_data/BE
    //   Controls: write, datain, Rx_mac_rd
 
-   wire  write, full;
+   wire  write, full, read, empty, sop_o, eop_o, error_o;
 
    // Write side of short FIFO
    assign write = ~full & ~Rx_mac_empty;
    assign Rx_mac_rd = write;
-
-   wire [31:0] data_ff;
-   wire        sop_ff, eop_ff, error_ff, read_ff, empty_ff;
-   
+ 
    shortfifo #(.WIDTH(35)) mac_rx_sfifo
      (.clk(clk),.rst(rst),.clear(0),
       
.datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
-      
.dataout({sop_ff,eop_ff,error_ff,data_ff}),.read(read_ff),.empty(empty_ff) );
+      .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty) );
 
-   wire       read_stage;
-   reg               empty_stage;
-   reg [31:0] data_stage;
-   reg               sop_stage;
-   
-   always @(posedge clk)
-     if(rst)
-       empty_stage <= 1;
-     else if(read_ff)
-       empty_stage <= 0;
-     else if(read_stage)
-       empty_stage <= 1;
+   // Read side of short FIFO
+   //    Inputs:    empty, dataout, wr_ready_i, wr_full_i
+   //    Controls:  read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o
 
-   always @(posedge clk)
-     if(read_ff)
-       begin
-         data_stage <= data_ff;
-         sop_stage <= sop_ff;
-       end
-
-   assign read_ff = ~empty_ff & ( empty_stage | read_stage);
-   
    reg [1:0] rd_state;
    localparam RD_IDLE = 0;
    localparam RD_HAVEPKT = 1;
@@ -69,25 +48,23 @@
      else
        case(rd_state)
         RD_IDLE :
-          if(sop_stage & ~empty_stage)
+          if(sop_o & ~empty)
             rd_state <= RD_HAVEPKT;
         RD_HAVEPKT :
           if(wr_ready_i)
             rd_state <= RD_XFER;
         RD_XFER :
-          if(eop_ff & ~empty_ff & ~empty_stage)
+          if(eop_o & ~empty)
             rd_state <= RD_IDLE;
           else if(wr_full_i)
             rd_state <= RD_HAVEPKT;
-        default :
+        RD_ERROR :
           rd_state <= RD_IDLE;
        endcase // case(rd_state)
 
-   assign     read_stage = ~empty_stage & ~empty_ff & 
-                          ((rd_state == RD_XFER) | 
((rd_state==RD_IDLE)&~sop_stage));
-   assign     wr_write_o = ~empty_stage & ~empty_ff & (rd_state == RD_XFER) & 
~eop_ff;
-   assign     wr_done_o = ~empty_ff & (rd_state == RD_XFER)  & eop_ff;
-   assign     wr_error_o = ~empty_ff & (rd_state == RD_XFER) & error_ff;
-   assign     wr_dat_o = data_stage;
-   
+   assign     read = ~empty & ((rd_state == RD_XFER) | 
((rd_state==RD_IDLE)&~sop_o));
+   assign     wr_write_o = ~empty & (rd_state == RD_XFER);
+   assign     wr_done_o = ~empty & (rd_state == RD_XFER)  & eop_o;
+   assign     wr_error_o = ~empty & (rd_state == RD_XFER) & error_o;
+
 endmodule // mac_rxfifo_int