[Commit-gnuradio] r7597 - in usrp2/trunk/fpga: sdr_lib top/u2_basic

[matt]

Author: matt
Date: 2008-02-06 23:16:00 -0700 (Wed, 06 Feb 2008)
New Revision: 7597

Modified:
   usrp2/trunk/fpga/sdr_lib/tx_control.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
debug lines for tx_control


Modified: usrp2/trunk/fpga/sdr_lib/tx_control.v
===================================================================
--- usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-02-07 04:34:32 UTC (rev 
7596)
+++ usrp2/trunk/fpga/sdr_lib/tx_control.v       2008-02-07 06:16:00 UTC (rev 
7597)
@@ -20,7 +20,9 @@
      // To DSP Core
      output [31:0] sample,
      output run,
-     output strobe
+     output strobe,
+
+     output [31:0] debug
      );
 
    // Buffer interface to internal FIFO
@@ -143,4 +145,9 @@
                         .strobe_in(run),.strobe(strobe) );
 
    assign      sample = data_o;
+
+   assign      debug = { 16'd0,
+                        {eop_o, eob, send_imm ,too_late, go_now, 
ibs_state[2:0] }, 
+                        empty_data, empty_ctrl, read_data, read_ctrl, strobe, 
clear_state, run, underrun};
+   
 endmodule // tx_control

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-07 04:34:32 UTC (rev 
7596)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-02-07 06:16:00 UTC (rev 
7597)
@@ -146,7 +146,7 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx, debug_mac0, debug_mac1;
+   wire [31:0]         debug_rx, debug_mac0, debug_mac1, debug_txc;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -545,7 +545,8 @@
       .master_time(master_time),.underrun(underrun),
       .rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
       .rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
-      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx) );
+      .sample(sample_tx), .run(run_tx), .strobe(strobe_tx),
+      .debug(debug_txc) );
    
    dsp_core_tx dsp_core_tx
      (.clk(dsp_clk),.rst(dsp_rst),
@@ -603,14 +604,15 @@
 
                             
    // Choose actual debug buses
-   assign        debug = debug_mac0;
-   assign        debug_clk[0] = wb_clk;
-   assign        debug_clk[1] = dsp_clk;       
-   assign        debug_gpio_0 = 32'd0;  // Not used b/c of ATR
-   assign        debug_gpio_1 = 
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
-                                 //GMII_TXD,
-                                 //GMII_RXD,
-                                 {2'b0,iwb_adr[13:0]},
-                                 
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
-                                 
+   assign      debug = debug_mac0;
+   assign      debug_clk[0] = wb_clk;
+   assign      debug_clk[1] = dsp_clk; 
+   assign      debug_gpio_0 = 32'd0;  // Not used b/c of ATR
+   assign      debug_gpio_1 = {16'd0,debug_txc[15:0]};
+   
+   wire [31:0] debug_eth = 
+              
{{uart_tx_o,proc_int,underrun,buffer_int,wr2_ready,wr2_error,wr2_done,wr2_write},
+               {2'b0,iwb_adr[13:0]},
+               
{GMII_TX_EN,GMII_RX_DV,Rx_mac_empty,Rx_mac_rd,Rx_mac_err,Rx_mac_sop,Rx_mac_eop,wr2_full}
 };
+   
 endmodule // u2_basic