[Commit-gnuradio] r7593 - in usrp2/trunk/fpga: eth/rtl/verilog top/u2_fpga

[matt]

Author: matt
Date: 2008-02-06 17:40:57 -0700 (Wed, 06 Feb 2008)
New Revision: 7593

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/Clk_ctrl.v
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
Log:
Now we are GIGABIT ONLY.  This makes clock routing easier, which allows the 
ethernet to work reliably.  


Modified: usrp2/trunk/fpga/eth/rtl/verilog/Clk_ctrl.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Clk_ctrl.v 2008-02-06 23:48:37 UTC (rev 
7592)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Clk_ctrl.v 2008-02-07 00:40:57 UTC (rev 
7593)
@@ -80,17 +80,22 @@
 output          MAC_rx_clk_div  ;
 
 
-//******************************************************************************
-//internal signals                                                             
 
-//******************************************************************************
+// 
******************************************************************************
+// internal signals                                                            
  
+// 
******************************************************************************
 wire            Rx_clk_div2 ;
 wire            Tx_clk_div2 ;
-//******************************************************************************
+// 
******************************************************************************
 //                                                              
-//******************************************************************************
-assign Gtx_clk      =Clk_125M                   ;
-assign MAC_rx_clk   =Rx_clk                     ;
+// 
******************************************************************************
+   assign      Gtx_clk          = Clk_125M                   ;
+   assign      MAC_rx_clk       = Rx_clk                     ;
+   assign      MAC_rx_clk_div   = Rx_clk                     ;
+   assign      MAC_tx_clk       = Clk_125M;
+   assign      MAC_tx_clk_div   = Clk_125M;
+   
 
+   /* 
 eth_clk_div2 U_0_CLK_DIV2(
 .Reset          (Reset          ),
 .IN             (Rx_clk         ),
@@ -124,4 +129,5 @@
 .OUT            (MAC_tx_clk_div )
 );
 
+    */
 endmodule

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf    2008-02-06 23:48:37 UTC (rev 
7592)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf    2008-02-07 00:40:57 UTC (rev 
7593)
@@ -217,14 +217,10 @@
 TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
-TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
 NET "cpld_clk" TNM_NET = "cpld_clk";
 TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
 NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
 TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
-TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
 NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
 #PACE: Start of Constraints generated by PACE

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2008-02-06 23:48:37 UTC 
(rev 7592)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2008-02-07 00:40:57 UTC 
(rev 7593)
@@ -23,8 +23,6 @@
 verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
 verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
 verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
-verilog work "../../eth/rtl/verilog/TECH/eth_clk_switch.v"
-verilog work "../../eth/rtl/verilog/TECH/eth_clk_div2.v"
 verilog work "../../eth/rtl/verilog/Reg_int.v"
 verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
 verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"