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[Commit-gnuradio] r7580 - usrp2/trunk/fpga/eth
From: |
matt |
Subject: |
[Commit-gnuradio] r7580 - usrp2/trunk/fpga/eth |
Date: |
Tue, 5 Feb 2008 19:58:26 -0700 (MST) |
Author: matt
Date: 2008-02-05 19:58:25 -0700 (Tue, 05 Feb 2008)
New Revision: 7580
Modified:
usrp2/trunk/fpga/eth/mac_rxfifo_int.v
Log:
I think this removes the extra 2 lines at the end of the packets, will check in
hardware tomorrow
Modified: usrp2/trunk/fpga/eth/mac_rxfifo_int.v
===================================================================
--- usrp2/trunk/fpga/eth/mac_rxfifo_int.v 2008-02-06 00:59:29 UTC (rev
7579)
+++ usrp2/trunk/fpga/eth/mac_rxfifo_int.v 2008-02-06 02:58:25 UTC (rev
7580)
@@ -21,21 +21,42 @@
// Inputs: full, Rx_mac_empty, Rx_mac_sop, Rx_mac_eop, Rx_mac_err,
Rx_mac_data/BE
// Controls: write, datain, Rx_mac_rd
- wire write, full, read, empty, sop_o, eop_o, error_o;
+ wire write, full;
// Write side of short FIFO
assign write = ~full & ~Rx_mac_empty;
assign Rx_mac_rd = write;
-
+
+ wire [31:0] data_ff;
+ wire sop_ff, eop_ff, error_ff, read_ff, empty_ff;
+
shortfifo #(.WIDTH(35)) mac_rx_sfifo
(.clk(clk),.rst(rst),.clear(0),
.datain({Rx_mac_sop,Rx_mac_eop,Rx_mac_err,Rx_mac_data}),.write(write),.full(full),
- .dataout({sop_o,eop_o,error_o,wr_dat_o}),.read(read),.empty(empty) );
+
.dataout({sop_ff,eop_ff,error_ff,data_ff}),.read(read_ff),.empty(empty_ff) );
- // Read side of short FIFO
- // Inputs: empty, dataout, wr_ready_i, wr_full_i
- // Controls: read, wr_dat_o, wr_write_o, wr_done_o, wr_error_o
+ wire read_stage;
+ reg empty_stage;
+ reg [31:0] data_stage;
+ reg sop_stage;
+
+ always @(posedge clk)
+ if(rst)
+ empty_stage <= 1;
+ else if(read_ff)
+ empty_stage <= 0;
+ else if(read_stage)
+ empty_stage <= 1;
+ always @(posedge clk)
+ if(read_ff)
+ begin
+ data_stage <= data_ff;
+ sop_stage <= sop_ff;
+ end
+
+ assign read_ff = ~empty_ff & ( empty_stage | read_stage);
+
reg [1:0] rd_state;
localparam RD_IDLE = 0;
localparam RD_HAVEPKT = 1;
@@ -48,23 +69,25 @@
else
case(rd_state)
RD_IDLE :
- if(sop_o & ~empty)
+ if(sop_stage & ~empty_stage)
rd_state <= RD_HAVEPKT;
RD_HAVEPKT :
if(wr_ready_i)
rd_state <= RD_XFER;
RD_XFER :
- if(eop_o & ~empty)
+ if(eop_ff & ~empty_ff & ~empty_stage)
rd_state <= RD_IDLE;
else if(wr_full_i)
rd_state <= RD_HAVEPKT;
- RD_ERROR :
+ default :
rd_state <= RD_IDLE;
endcase // case(rd_state)
- assign read = ~empty & ((rd_state == RD_XFER) |
((rd_state==RD_IDLE)&~sop_o));
- assign wr_write_o = ~empty & (rd_state == RD_XFER);
- assign wr_done_o = ~empty & (rd_state == RD_XFER) & eop_o;
- assign wr_error_o = ~empty & (rd_state == RD_XFER) & error_o;
-
+ assign read_stage = ~empty_stage & ~empty_ff &
+ ((rd_state == RD_XFER) |
((rd_state==RD_IDLE)&~sop_stage));
+ assign wr_write_o = ~empty_stage & ~empty_ff & (rd_state == RD_XFER) &
~eop_ff;
+ assign wr_done_o = ~empty_ff & (rd_state == RD_XFER) & eop_ff;
+ assign wr_error_o = ~empty_ff & (rd_state == RD_XFER) & error_ff;
+ assign wr_dat_o = data_stage;
+
endmodule // mac_rxfifo_int
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