[Commit-gnuradio] r7557 - usrp2/trunk/fpga/top/u2

commit-gnuradio

[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]

[Commit-gnuradio] r7557 - usrp2/trunk/fpga/top/u2_fpga

From:	matt
Subject:	[Commit-gnuradio] r7557 - usrp2/trunk/fpga/top/u2_fpga
Date:	Mon, 4 Feb 2008 17:43:33 -0700 (MST)

Author: matt
Date: 2008-02-04 17:43:32 -0700 (Mon, 04 Feb 2008)
New Revision: 7557

Modified:
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
Log:
proper source-synchronous IOBs for GMII_TX


Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf    2008-02-04 22:01:47 UTC (rev 
7556)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ucf    2008-02-05 00:43:32 UTC (rev 
7557)
@@ -213,6 +213,23 @@
 NET "ser_t[7]"  LOC = "AA5"  ;
 NET "ser_t[8]"  LOC = "W6"  ;
 NET "ser_t[9]"  LOC = "V6"  ;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
+NET "clk_to_mac" TNM_NET = "clk_to_mac";
+TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
+TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
+NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
+TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
+NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
+TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
+NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
+TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
+#PACE: Start of Constraints generated by PACE
+
+#PACE: Start of PACE I/O Pin Assignments
 NET "adc_oen_a"  LOC = "E19"  ; 
 NET "adc_oen_b"  LOC = "C17"  ; 
 NET "adc_ovf_a"  LOC = "F18"  ; 
@@ -235,13 +252,21 @@
 NET "exp_pps_out_p"  LOC = "V1"  ; 
 NET "GMII_COL"  LOC = "U16"  ; 
 NET "GMII_CRS"  LOC = "U17"  ; 
-NET "GMII_GTX_CLK"  LOC = "AA17"  ; 
+NET "GMII_GTX_CLK"  LOC = "AA17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW 
= FAST ; 
 NET "GMII_RX_CLK"  LOC = "W16"  ; 
 NET "GMII_RX_DV"  LOC = "AB16"  ; 
 NET "GMII_RX_ER"  LOC = "AA16"  ; 
 NET "GMII_TX_CLK"  LOC = "W13"  ; 
-NET "GMII_TX_EN"  LOC = "Y17"  ; 
-NET "GMII_TX_ER"  LOC = "V16"  ; 
+NET "GMII_TX_EN"  LOC = "Y17" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
+NET "GMII_TX_ER"  LOC = "V16" | IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = 
FAST ; 
+NET "GMII_TXD<0>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<1>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<2>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<3>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<4>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<5>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<6>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
+NET "GMII_TXD<7>" IOSTANDARD = LVCMOS25  | DRIVE = 12  | SLEW = FAST ;
 NET "led1"  LOC = "V11"  ; 
 NET "led2"  LOC = "Y12"  ; 
 NET "MDC"  LOC = "V18"  ; 
@@ -298,19 +323,8 @@
 NET "ser_tkmsb"  LOC = "U11"  ; 
 NET "ser_tx_clk"  LOC = "U7"  ; 
 
+#PACE: Start of PACE Area Constraints
+
+#PACE: Start of PACE Prohibit Constraints
+
 #PACE: End of Constraints generated by PACE
-
-NET "clk_muxed" TNM_NET = "clk_muxed";
-TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
-NET "clk_to_mac" TNM_NET = "clk_to_mac";
-TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
-NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
-TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
-NET "cpld_clk" TNM_NET = "cpld_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
-TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
-NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
-TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
-NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
-TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2008-02-04 22:01:47 UTC 
(rev 7556)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2008-02-05 00:43:32 UTC 
(rev 7557)
@@ -39,7 +39,6 @@
 verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/ss_rcvr.v"
 verilog work "../../control_lib/cascadefifo2.v"
-verilog work "../../control_lib/cascadefifo.v"
 verilog work "../../control_lib/CRC16_D16.v"
 verilog work "../../timing/time_sender.v"
 verilog work "../../timing/time_receiver.v"

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-02-04 22:01:47 UTC (rev 
7556)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.v  2008-02-05 00:43:32 UTC (rev 
7557)
@@ -21,9 +21,9 @@
    input GMII_CRS,
 
    //   GMII-TX
-   output [7:0] GMII_TXD,
-   output GMII_TX_EN,
-   output GMII_TX_ER,
+   output reg [7:0] GMII_TXD,
+   output reg GMII_TX_EN,
+   output reg GMII_TX_ER,
    output GMII_GTX_CLK,
    input GMII_TX_CLK,  // 100mbps clk
 
@@ -239,7 +239,29 @@
    assign      miso = (~sen_clk & sdo) | (~sen_dac & sdo) | 
                (~sen_tx_db & sdo_tx_db) | (~sen_tx_adc & sdo_tx_adc) |
                (~sen_rx_db & sdo_rx_db) | (~sen_rx_adc & sdo_rx_adc);
-      
+
+   wire        GMII_TX_EN_unreg, GMII_TX_ER_unreg;
+   wire [7:0]  GMII_TXD_unreg;
+   wire        GMII_GTX_CLK_int;
+   
+   always @(posedge GMII_GTX_CLK_int)
+     begin
+       GMII_TX_EN <= GMII_TX_EN_unreg;
+       GMII_TX_ER <= GMII_TX_ER_unreg;
+       GMII_TXD <= GMII_TXD_unreg;
+     end
+
+   OFDDRRSE OFDDRRSE_inst 
+     (.Q(GMII_GTX_CLK),      // Data output (connect directly to top-level 
port)
+      .C0(GMII_GTX_CLK_int),    // 0 degree clock input
+      .C1(~GMII_GTX_CLK_int),    // 180 degree clock input
+      .CE(1),    // Clock enable input
+      .D0(0),    // Posedge data input
+      .D1(1),    // Negedge data input
+      .R(0),      // Synchronous reset input
+      .S(0)       // Synchronous preset input
+      );
+   
    u2_basic u2_basic(.dsp_clk           (dsp_clk),
                     .wb_clk            (wb_clk),
                     .clock_ready       (clock_ready),
@@ -253,10 +275,10 @@
                     .exp_pps_out       (exp_pps_out),
                     .GMII_COL          (GMII_COL),
                     .GMII_CRS          (GMII_CRS),
-                    .GMII_TXD          (GMII_TXD[7:0]),
-                    .GMII_TX_EN        (GMII_TX_EN),
-                    .GMII_TX_ER        (GMII_TX_ER),
-                    .GMII_GTX_CLK      (GMII_GTX_CLK),
+                    .GMII_TXD          (GMII_TXD_unreg[7:0]),
+                    .GMII_TX_EN        (GMII_TX_EN_unreg),
+                    .GMII_TX_ER        (GMII_TX_ER_unreg),
+                    .GMII_GTX_CLK      (GMII_GTX_CLK_int),
                     .GMII_TX_CLK       (GMII_TX_CLK),
                     .GMII_RXD          (GMII_RXD[7:0]),
                     .GMII_RX_CLK       (GMII_RX_CLK),

[Prev in Thread]

Current Thread

[Next in Thread]

[Commit-gnuradio] r7557 - usrp2/trunk/fpga/top/u2_fpga, matt <=

Prev by Date: [Commit-gnuradio] r7556 - gnuradio/branches/developers/gnychis/matched_filter/gnuradio-core/src/lib/filter
Next by Date: [Commit-gnuradio] r7558 - usrp2/branches/developers/matt/newfifo/fpga/top/u2_fpga
Previous by thread: [Commit-gnuradio] r7556 - gnuradio/branches/developers/gnychis/matched_filter/gnuradio-core/src/lib/filter
Next by thread: [Commit-gnuradio] r7558 - usrp2/branches/developers/matt/newfifo/fpga/top/u2_fpga
Index(es):
- Date
- Thread