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[Commit-gnuradio] r7552 - in usrp2/branches/developers/matt/protengine:
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From: |
matt |
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Subject: |
[Commit-gnuradio] r7552 - in usrp2/branches/developers/matt/protengine: firmware/apps firmware/lib fpga/control_lib fpga/top/u2_basic |
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Date: |
Sun, 3 Feb 2008 21:37:06 -0700 (MST) |
Author: matt
Date: 2008-02-03 21:37:05 -0700 (Sun, 03 Feb 2008)
New Revision: 7552
Modified:
usrp2/branches/developers/matt/protengine/firmware/apps/gen_eth_packets.c
usrp2/branches/developers/matt/protengine/firmware/lib/eth_mac.c
usrp2/branches/developers/matt/protengine/firmware/lib/ethernet.c
usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_int.v
usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_pool.v
usrp2/branches/developers/matt/protengine/fpga/top/u2_basic/u2_basic.v
Log:
first cut at the protocol engine
Modified:
usrp2/branches/developers/matt/protengine/firmware/apps/gen_eth_packets.c
===================================================================
--- usrp2/branches/developers/matt/protengine/firmware/apps/gen_eth_packets.c
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/firmware/apps/gen_eth_packets.c
2008-02-04 04:37:05 UTC (rev 7552)
@@ -32,7 +32,6 @@
#include "print_rmon_regs.h"
#include <stddef.h>
#include <stdlib.h>
-#include <string.h>
// ----------------------------------------------------------------
@@ -101,12 +100,11 @@
{
u2_eth_packet_t pkt __attribute__((aligned (4)));
- memset(&pkt, 0, sizeof(pkt));
-
pkt.ehdr.dst = dst_mac_addr;
// src address filled in by mac
pkt.ehdr.ethertype = U2_ETHERTYPE;
+ pkt.ehdr._pad = 0x5555;
pkt.fixed.word0 = 0x01234567;
pkt.fixed.timestamp = 0xffffffff;
@@ -121,6 +119,30 @@
u2_init();
+ unsigned int volatile *tx_prot_engine;
+ tx_prot_engine = 0xD080;
+ *tx_prot_engine = 0x01; // Channel number
+ tx_prot_engine = 0xD084;
+ *tx_prot_engine = 0xFFFFFFFF; // 4 bytes of Dest MAC addr
+ tx_prot_engine = 0xD088;
+ *tx_prot_engine = 0xFFFF0000; // 2 bytes of Dest MAC, 2 of SRC
+ tx_prot_engine = 0xD08C;
+ *tx_prot_engine = 0x00000000; // 4 bytes of SRC MAC
+ tx_prot_engine = 0xD090;
+ *tx_prot_engine = 0; // To initialize the sequence number. It
autoincrements.
+
+ unsigned int volatile *rx_prot_engine;
+ rx_prot_engine = 0xD0C0;
+ *rx_prot_engine = 0x01; // Channel number
+ rx_prot_engine = 0xD0C4;
+ *rx_prot_engine = 0xFFFFFFFF; // 4 bytes of Dest MAC addr
+ rx_prot_engine = 0xD0C8;
+ *rx_prot_engine = 0xFFFF0000; // 2 bytes of Dest MAC, 2 of SRC
+ rx_prot_engine = 0xD0CC;
+ *rx_prot_engine = 0x00000000; // 4 bytes of SRC MAC
+ rx_prot_engine = 0xD0D0;
+ *rx_prot_engine = 0xBEEF0000; // Eth type in top 16 bits
+
// setup tx gpio bits for GPIOM_FPGA_1 -- fpga debug output
hal_gpio_set_tx_mode(15, 0, GPIOM_FPGA_1);
hal_gpio_set_rx_mode(15, 0, GPIOM_FPGA_1);
Modified: usrp2/branches/developers/matt/protengine/firmware/lib/eth_mac.c
===================================================================
--- usrp2/branches/developers/matt/protengine/firmware/lib/eth_mac.c
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/firmware/lib/eth_mac.c
2008-02-04 04:37:05 UTC (rev 7552)
@@ -40,7 +40,7 @@
eth_mac->mac_tx_add_prom_wr = 0;
mdelay(1);
}
- eth_mac->mac_tx_add_en = 1; // overwrite pkt src addr field with this stuff
+ eth_mac->mac_tx_add_en = 0; // overwrite pkt src addr field with this stuff
// set up receive destination address filter
eth_mac->mac_rx_add_prom_wr = 0; // just in case
@@ -69,10 +69,6 @@
eth_mac->fc_lwmark = 400; // there is currently 1024 lines in the
fifo
eth_mac->fc_hwmark = 800;
-
- //eth_mac->tx_pause_en = 0; // pay attn to pause frames sent to us
- //eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512
+ fudge
- //eth_mac->pause_frame_send_en = 0; // enable sending pause frames
}
int
Modified: usrp2/branches/developers/matt/protengine/firmware/lib/ethernet.c
===================================================================
--- usrp2/branches/developers/matt/protengine/firmware/lib/ethernet.c
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/firmware/lib/ethernet.c
2008-02-04 04:37:05 UTC (rev 7552)
@@ -171,10 +171,10 @@
eth_mac->rx_max_length = 2048;
// configure PAUSE frame stuff
- eth_mac->tx_pause_en = 1; // pay attn to pause frames sent to us
+ eth_mac->tx_pause_en = 0; // pay attn to pause frames sent to us
eth_mac->pause_quanta_set = 38; // a bit more than 1 max frame 16kb/512
+ fudge
- eth_mac->pause_frame_send_en = 1; // enable sending pause frames
+ eth_mac->pause_frame_send_en = 0; // enable sending pause frames
// setup PHY to interrupt on changes
@@ -256,26 +256,3 @@
return ok;
}
-
-int
-ethernet_check_errors(void)
-{
- // these registers are reset when read
-
- int r = 0;
- if (eth_mac_read_rmon(0x05) != 0)
- r |= RME_RX_CRC;
- if (eth_mac_read_rmon(0x06) != 0)
- r |= RME_RX_FIFO_FULL;
- if (eth_mac_read_rmon(0x07) != 0)
- r |= RME_RX_2SHORT_2LONG;
-
- if (eth_mac_read_rmon(0x25) != 0)
- r |= RME_TX_JAM_DROP;
- if (eth_mac_read_rmon(0x26) != 0)
- r |= RME_TX_FIFO_UNDER;
- if (eth_mac_read_rmon(0x27) != 0)
- r |= RME_TX_FIFO_OVER;
-
- return r;
-}
Modified:
usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_int.v
===================================================================
--- usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_int.v
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_int.v
2008-02-04 04:37:05 UTC (rev 7552)
@@ -13,6 +13,7 @@
output done,
output error,
output idle,
+ output reg flag,
// Buffer Interface
output en_o,
@@ -28,6 +29,7 @@
input wr_error_i,
output reg wr_ready_o,
output reg wr_full_o,
+ input wr_flag_i,
// Read FIFO Interface
output [31:0] rd_dat_o,
@@ -80,6 +82,7 @@
rd_eop_o <= 0;
wr_ready_o <= 0;
wr_full_o <= 0;
+ flag <= 0;
end
else
if(clear)
@@ -89,6 +92,7 @@
rd_eop_o <= 0;
wr_ready_o <= 0;
wr_full_o <= 0;
+ flag <= 0;
end
else
case(state)
@@ -145,11 +149,15 @@
if(addr_o == (lastline-1))
wr_full_o <= 1;
if(addr_o == lastline)
- state <= DONE;
+ begin
+ state <= DONE;
+ flag <= wr_flag_i;
+ end
end
if(wr_done_i)
begin
state <= DONE;
+ flag <= wr_flag_i;
wr_ready_o <= 0;
end
end // else: !if(wr_error_i)
@@ -175,17 +183,3 @@
assign error = (state == ERROR);
assign idle = (state == IDLE);
endmodule // buffer_int
-
-// Unused old code
- //assign rd_empty_o = (state != READING); // && (state != PRE_READ);
- //assign rd_empty_o = rd_empty_reg; // timing fix?
- //assign rd_ready_o = (state == READING);
- //assign rd_ready_o = ~rd_empty_reg; // timing fix?
-
- //wire rd_en = (state == PRE_READ) || ((state == READING) &&
rd_read_i);
- //wire wr_en = (state == WRITING) && wr_write_i; // IF this is a
timing problem, we could always enable when in this state
- //assign en_o = rd_en | wr_en;
-
- // assign wr_full_o = (state != WRITING);
- // assign wr_ready_o = (state == WRITING);
-
Modified:
usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_pool.v
===================================================================
--- usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_pool.v
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/fpga/control_lib/buffer_pool.v
2008-02-04 04:37:05 UTC (rev 7552)
@@ -34,10 +34,10 @@
output [31:0] s4, output [31:0] s5, output [31:0] s6, output [31:0] s7,
// Write Interfaces
- input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input
wr0_error_i, output wr0_ready_o, output wr0_full_o,
- input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input
wr1_error_i, output wr1_ready_o, output wr1_full_o,
- input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input
wr2_error_i, output wr2_ready_o, output wr2_full_o,
- input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input
wr3_error_i, output wr3_ready_o, output wr3_full_o,
+ input [31:0] wr0_dat_i, input wr0_write_i, input wr0_done_i, input
wr0_error_i, output wr0_ready_o, output wr0_full_o, input wr0_flag_i,
+ input [31:0] wr1_dat_i, input wr1_write_i, input wr1_done_i, input
wr1_error_i, output wr1_ready_o, output wr1_full_o, input wr1_flag_i,
+ input [31:0] wr2_dat_i, input wr2_write_i, input wr2_done_i, input
wr2_error_i, output wr2_ready_o, output wr2_full_o, input wr2_flag_i,
+ input [31:0] wr3_dat_i, input wr3_write_i, input wr3_done_i, input
wr3_error_i, output wr3_ready_o, output wr3_full_o, input wr3_flag_i,
// Read Interfaces
output [31:0] rd0_dat_o, input rd0_read_i, input rd0_done_i, input
rd0_error_i, output rd0_sop_o, output rd0_eop_o,
@@ -64,6 +64,7 @@
wire [7:0] done;
wire [7:0] error;
wire [7:0] idle;
+ wire [7:0] flag;
wire [31:0] buf_doa[0:7];
@@ -79,6 +80,7 @@
wire [7:0] wr_error_i;
wire [7:0] wr_ready_o;
wire [7:0] wr_full_o;
+ wire [7:0] wr_flag_i;
wire [31:0] rd_dat_o[0:7];
wire [7:0] rd_read_i;
@@ -87,7 +89,7 @@
wire [7:0] rd_sop_o;
wire [7:0] rd_eop_o;
- assign status = {8'd0,idle[7:0],error[7:0],done[7:0]};
+ assign status = {flag[7:0],idle[7:0],error[7:0],done[7:0]};
assign s0 = {23'd0,buf_addrb[0]};
assign s1 = {23'd0,buf_addrb[1]};
@@ -146,10 +148,10 @@
.clkb(stream_clk),.enb(buf_enb[i]),.web(buf_web[i]),
.addrb(buf_addrb[i]),.dib(buf_dib[i]),.dob(buf_dob[i])); */
- buffer_int #(.BUFF_NUM(i)) fifo_int
+ buffer_int #(.BUFF_NUM(i)) buffer_int
(.clk(stream_clk),.rst(stream_rst),
.ctrl_word(fifo_ctrl),.go(go & (fifo_ctrl[31:28]==i)),
- .done(done[i]),.error(error[i]),.idle(idle[i]),
+ .done(done[i]),.error(error[i]),.idle(idle[i]),.flag(flag[i]),
.en_o(buf_enb[i]),
.we_o(buf_web[i]),
.addr_o(buf_addrb[i]),
@@ -161,12 +163,13 @@
.wr_error_i(wr_error_i[i]),
.wr_ready_o(wr_ready_o[i]),
.wr_full_o(wr_full_o[i]),
+ .wr_flag_i(wr_flag_i[i]),
.rd_dat_o(rd_dat_o[i]),
.rd_read_i(rd_read_i[i]),
.rd_done_i(rd_done_i[i]),
.rd_error_i(rd_error_i[i]),
.rd_sop_o(rd_sop_o[i]),
- .rd_eop_o(rd_eop_o[i])
+ .rd_eop_o(rd_eop_o[i])
);
// FIXME -- if it is a problem, maybe we don't need enables on these
muxes
@@ -183,6 +186,9 @@
mux4_wrerror_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_error_i),.i1(wr1_error_i),
.i2(wr2_error_i),.i3(wr3_error_i),.o(wr_error_i[i]));
mux4 #(.WIDTH(1))
+ mux4_wrflag_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(wr0_flag_i),.i1(wr1_flag_i),
+ .i2(wr2_flag_i),.i3(wr3_flag_i),.o(wr_flag_i[i]));
+ mux4 #(.WIDTH(1))
mux4_read_i
(.en(~port[i][2]),.sel(port[i][1:0]),.i0(rd0_read_i),.i1(rd1_read_i),
.i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
mux4 #(.WIDTH(1))
Modified: usrp2/branches/developers/matt/protengine/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/branches/developers/matt/protengine/fpga/top/u2_basic/u2_basic.v
2008-02-04 04:28:12 UTC (rev 7551)
+++ usrp2/branches/developers/matt/protengine/fpga/top/u2_basic/u2_basic.v
2008-02-04 04:37:05 UTC (rev 7552)
@@ -277,10 +277,10 @@
wire rd3_read, rd3_sop, rd3_error, rd3_done, rd3_eop;
wire [31:0] rd0_dat, rd1_dat, rd2_dat, rd3_dat;
- wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full;
- wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full;
- wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full;
- wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full;
+ wire wr0_write, wr0_done, wr0_error, wr0_ready, wr0_full, wr0_flag;
+ wire wr1_write, wr1_done, wr1_error, wr1_ready, wr1_full, wr1_flag;
+ wire wr2_write, wr2_done, wr2_error, wr2_ready, wr2_full, wr2_flag;
+ wire wr3_write, wr3_done, wr3_error, wr3_ready, wr3_full, wr3_flag;
wire [31:0] wr0_dat, wr1_dat, wr2_dat, wr3_dat;
buffer_pool buffer_pool
@@ -297,13 +297,13 @@
// Write Interfaces
.wr0_dat_i(wr0_dat), .wr0_write_i(wr0_write), .wr0_done_i(wr0_done),
- .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
+ .wr0_error_i(wr0_error), .wr0_ready_o(wr0_ready), .wr0_full_o(wr0_full),
.wr0_flag_i(0),
.wr1_dat_i(wr1_dat), .wr1_write_i(wr1_write), .wr1_done_i(wr1_done),
- .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
+ .wr1_error_i(wr1_error), .wr1_ready_o(wr1_ready), .wr1_full_o(wr1_full),
.wr1_flag_i(0),
.wr2_dat_i(wr2_dat), .wr2_write_i(wr2_write), .wr2_done_i(wr2_done),
- .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
+ .wr2_error_i(wr2_error), .wr2_ready_o(wr2_ready), .wr2_full_o(wr2_full),
.wr2_flag_i(wr2_flag),
.wr3_dat_i(wr3_dat), .wr3_write_i(wr3_write), .wr3_done_i(wr3_done),
- .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
+ .wr3_error_i(wr3_error), .wr3_ready_o(wr3_ready), .wr3_full_o(wr3_full),
.wr3_flag_i(0),
// Read Interfaces
.rd0_dat_o(rd0_dat), .rd0_read_i(rd0_read), .rd0_done_i(rd0_done),
.rd0_error_i(rd0_error), .rd0_sop_o(rd0_sop), .rd0_eop_o(rd0_eop),
@@ -406,7 +406,7 @@
wire [31:0] Tx_mac_data, Rx_mac_data;
wire [1:0] Tx_mac_BE, Rx_mac_BE;
- MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(11))
+ MAC_top #(.TX_FF_DEPTH(9), .RX_FF_DEPTH(9))
MAC_top
(.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
@@ -420,24 +420,33 @@
.Crs(GMII_CRS),.Col(GMII_COL),
.Mdio(MDIO),.Mdc(MDC),
.debug0(debug_mac0),.debug1(debug_mac1) );
-
assign s6_err = 1'b0;
assign s6_rty = 1'b0;
- mac_rxfifo_int mac_rxfifo_int
+ wire [15:0] rx_fifo_status;
+ wire [7:0] rx_seqnum, tx_channel, rx_channel, rx_flags, tx_flags;
+ rx_prot_engine rx_prot_engine
(.clk(dsp_clk),.rst(dsp_rst),
.Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
.Rx_mac_BE(Rx_mac_BE),.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),
.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
.wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
- .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full) );
+
.wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full),.wr_flag_o(wr2_flag),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .rx_fifo_status(rx_fifo_status),.rx_seqnum(rx_seqnum),
+ .rx_channel(rx_channel) );
+ // .rx_flags() );
- mac_txfifo_int mac_txfifo_int
+ //assign tx_channel = 8'h8E;
+ tx_prot_engine tx_prot_engine
(.clk(dsp_clk),.rst(dsp_rst),
.Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
.Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
.rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
- .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop) );
+ .rd_error_o(rd2_error),.rd_sop_i(rd2_sop),.rd_eop_i(rd2_eop),
+ .set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
+ .rx_fifo_status(rx_fifo_status),.rx_seqnum(rx_seqnum) );
+ //.tx_channel(tx_channel),.tx_flags() );
// /////////////////////////////////////////////////////////////////////////
// Interrupt Controller, Slave #8
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- [Commit-gnuradio] r7552 - in usrp2/branches/developers/matt/protengine: firmware/apps firmware/lib fpga/control_lib fpga/top/u2_basic,
matt <=