[Commit-gnuradio] r7448 - in usrp2/trunk/fpga: eth/rtl/verilog top/u2_basic

[matt]

Author: matt
Date: 2008-01-16 00:21:27 -0700 (Wed, 16 Jan 2008)
New Revision: 7448

Modified:
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
new debug ports


Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-01-16 05:35:20 UTC (rev 
7447)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-01-16 07:21:27 UTC (rev 
7448)
@@ -102,7 +102,11 @@
 
   // MDIO interface (to PHY)
   inout         Mdio,
-  output        Mdc
+  output        Mdc,
+
+     // Debug Interface
+     output [31:0] debug0,
+     output [31:0] debug1
 );
 
   //-------------------------------------------------------------------------
@@ -500,4 +504,8 @@
     .UpdateMIIRX_DATAReg      ( UpdateMIIRX_DATAReg       )
   );
 
+   assign debug0 = {{tx_pause_en,pause_apply, pause_quanta_sub, 
pause_quanta_val, xon_gen, xon_gen_complete, xoff_gen, xoff_gen_complete},
+                   
{Rx_mac_err,Rx_mac_ra,Rx_mac_rd,Rx_mac_pa,Rx_mac_sop,Rx_mac_eop,Rx_mac_BE[1:0]},
+                   {rx_fifo_space}};
+   assign debug1 = 32'd0;
 endmodule

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-16 05:35:20 UTC (rev 
7447)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-16 07:21:27 UTC (rev 
7448)
@@ -146,7 +146,7 @@
    wire [31:0]         debug_gpio_0, debug_gpio_1;
    wire [31:0]         atr_lines;
 
-   wire [31:0]         debug_rx;
+   wire [31:0]         debug_rx, debug_mac0, debug_mac1;
    // 
///////////////////////////////////////////////////////////////////////////////////////////////
    // Wishbone Single Master INTERCON
    parameter   dw = 32;  // Data bus width
@@ -418,7 +418,8 @@
        
.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
        
.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
        .Crs(GMII_CRS),.Col(GMII_COL),
-       .Mdio(MDIO),.Mdc(MDC) );
+       .Mdio(MDIO),.Mdc(MDC),
+       .debug0(debug_mac0),.debug1(debug_mac1) );
 
    assign       s6_err = 1'b0;
    assign       s6_rty = 1'b0;
@@ -604,10 +605,13 @@
 
                             
    // Choose actual debug buses
-   assign        debug = master_time;
+   assign        debug = debug_mac0;
    assign        debug_clk[0] = wb_clk;
    assign        debug_clk[1] = dsp_clk;       
    assign        debug_gpio_0 = 32'd0;  // Not used b/c of ATR
-   assign        debug_gpio_1 = debug_irq;
-   
+   assign        debug_gpio_1 = 
{{uart_tx_o,proc_int,overrun,underrun,timer_int,buffer_int,pps_int,PHY_INTn},
+                                 GMII_TXD,
+                                 GMII_RXD,
+                                 {GMII_TX_EN,GMII_RX_DV,6'b0} };
+                                 
 endmodule // u2_basic