[Commit-gnuradio] r7430 - in usrp2/trunk: firmware/lib fpga/eth/rtl/verilog fpga/top/u2_basic

[matt]

Author: matt
Date: 2008-01-14 00:06:40 -0700 (Mon, 14 Jan 2008)
New Revision: 7430

Modified:
   usrp2/trunk/firmware/lib/eth_mac.c
   usrp2/trunk/firmware/lib/eth_mac_regs.h
   usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
   usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
   usrp2/trunk/fpga/top/u2_basic/u2_basic.v
Log:
read rmon as one 32-bit word


Modified: usrp2/trunk/firmware/lib/eth_mac.c
===================================================================
--- usrp2/trunk/firmware/lib/eth_mac.c  2008-01-14 04:43:08 UTC (rev 7429)
+++ usrp2/trunk/firmware/lib/eth_mac.c  2008-01-14 07:06:40 UTC (rev 7430)
@@ -69,6 +69,10 @@
 
   eth_mac->fc_lwmark = 400;            // there is currently 1024 lines in the 
fifo
   eth_mac->fc_hwmark = 800;
+
+  //eth_mac->tx_pause_en = 0;          // pay attn to pause frames sent to us
+  //eth_mac->pause_quanta_set = 38;    // a bit more than 1 max frame 16kb/512 
+ fudge
+  //eth_mac->pause_frame_send_en = 0;  // enable sending pause frames
 }
 
 int
@@ -81,7 +85,7 @@
   while(eth_mac->rmon_rd_grant == 0)
     ;
 
-  t = (eth_mac->rmon_rd_dout_hi << 16) | (eth_mac->rmon_rd_dout_lo & 0xffff);
+  t = eth_mac->rmon_rd_dout;
   eth_mac->rmon_rd_apply = 0;
   return t;
 }

Modified: usrp2/trunk/firmware/lib/eth_mac_regs.h
===================================================================
--- usrp2/trunk/firmware/lib/eth_mac_regs.h     2008-01-14 04:43:08 UTC (rev 
7429)
+++ usrp2/trunk/firmware/lib/eth_mac_regs.h     2008-01-14 07:06:40 UTC (rev 
7430)
@@ -71,8 +71,8 @@
   volatile int rmon_rd_addr;           // performance counter access
   volatile int rmon_rd_apply;          
   volatile int rmon_rd_grant;          // READONLY
-  volatile int rmon_rd_dout_lo;        // READONLY
-  volatile int rmon_rd_dout_hi;        // READONLY
+  volatile int rmon_rd_dout;           // READONLY
+  volatile int dummy;  // READONLY
   volatile int line_loop_en;
   volatile int speed;
   volatile int miimoder;

Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-01-14 04:43:08 UTC (rev 
7429)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_top.v  2008-01-14 07:06:40 UTC (rev 
7430)
@@ -66,8 +66,8 @@
   input         CYC_I, // Active high cycle-enable
   input [6:0]   ADR_I, // Module register address
   input         WE_I,  // Active high for writes, low for reads
-  input [15:0]  DAT_I, // Write data
-  output [15:0] DAT_O, // Read data
+  input [31:0]  DAT_I, // Write data
+  output [31:0] DAT_O, // Read data
   output        ACK_O, // Acknowledge output � single high pulse
 
   // User (packet) interface
@@ -111,7 +111,6 @@
 
   // Translate Wishbone specific naming to internal 'generic' names
   wire Reset   = RST_I;
-  wire Clk_reg = CLK_I;
 
   // RMON interface
   wire [15:0] Rx_pkt_length_rmon;
@@ -406,7 +405,7 @@
   );
 
   eth_miim U_eth_miim(
-    .Clk                ( Clk_reg             ),
+    .Clk                ( CLK_I               ),
     .Reset              ( Reset               ),
     .Divider            ( Divider             ),
     .NoPre              ( NoPre               ),

Modified: usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v  2008-01-14 04:43:08 UTC (rev 
7429)
+++ usrp2/trunk/fpga/eth/rtl/verilog/Reg_int.v  2008-01-14 07:06:40 UTC (rev 
7430)
@@ -6,8 +6,8 @@
   input             CYC_I, // Active high cycle-enable
   input  [6:0]      ADR_I, // Module register address
   input             WE_I,  // Active high for writes, low for reads
-  input  [15:0]     DAT_I, // Write data
-  output reg [15:0] DAT_O, // Read data
+  input  [31:0]     DAT_I, // Write data
+  output reg [31:0] DAT_O, // Read data
   output reg        ACK_O, // Acknowledge output � single high pulse
 
   // Tx host interface 
@@ -181,9 +181,6 @@
       ACK_O <= Access;
 
   always @ ( posedge RST_I or posedge CLK_I )
-    if ( RST_I )
-      DAT_O <=0;
-    else
       begin
         DAT_O <=0;
         if ( Access & ~WE_I )
@@ -219,8 +216,8 @@
             7'd28: DAT_O <= CPU_rd_addr;
             7'd29: DAT_O <= CPU_rd_apply;
             7'd30: DAT_O <= CPU_rd_grant;
-            7'd31: DAT_O <= CPU_rd_dout[15:0];
-            7'd32: DAT_O <= CPU_rd_dout[31:16];
+            7'd31: DAT_O <= CPU_rd_dout;
+            //7'd32: DAT_O <= CPU_rd_dout[31:16];
             7'd33: DAT_O <= Line_loop_en;
             7'd34: DAT_O <= Speed;
 

Modified: usrp2/trunk/fpga/top/u2_basic/u2_basic.v
===================================================================
--- usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-14 04:43:08 UTC (rev 
7429)
+++ usrp2/trunk/fpga/top/u2_basic/u2_basic.v    2008-01-14 07:06:40 UTC (rev 
7430)
@@ -410,7 +410,7 @@
      MAC_top
        (.Clk_125M(clk_to_mac),.Clk_user(dsp_clk),.Speed(),
        
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
-       
.WE_I(s6_we),.DAT_I(s6_dat_o[15:0]),.DAT_O(s6_dat_i[15:0]),.ACK_O(s6_ack),
+       .WE_I(s6_we),.DAT_I(s6_dat_o),.DAT_O(s6_dat_i),.ACK_O(s6_ack),
        
.Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),.Rx_mac_BE(Rx_mac_BE),
        
.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),.Rx_mac_err(Rx_mac_err),
        .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
@@ -419,8 +419,7 @@
        
.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
        .Crs(GMII_CRS),.Col(GMII_COL),
        .Mdio(MDIO),.Mdc(MDC) );
-   
-   assign       s6_dat_i[31:16] = 0;
+
    assign       s6_err = 1'b0;
    assign       s6_rty = 1'b0;