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[Commit-gnuradio] r7410 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx
From: |
matt |
Subject: |
[Commit-gnuradio] r7410 - usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx |
Date: |
Sat, 12 Jan 2008 20:50:09 -0700 (MST) |
Author: matt
Date: 2008-01-12 20:50:07 -0700 (Sat, 12 Jan 2008)
New Revision: 7410
Modified:
usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
Log:
reformatting
Modified: usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v
===================================================================
--- usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-13 00:56:29 UTC
(rev 7409)
+++ usrp2/trunk/fpga/eth/rtl/verilog/MAC_tx/MAC_tx_FF.v 2008-01-13 03:50:07 UTC
(rev 7410)
@@ -61,60 +61,33 @@
`include "header.vh"
-module MAC_tx_FF (
-Reset ,
-Clk_MAC ,
-Clk_SYS ,
-//MAC_rx_ctrl interface
-Fifo_data ,
-Fifo_rd ,
-Fifo_rd_finish ,
-Fifo_rd_retry ,
-Fifo_eop ,
-Fifo_da ,
-Fifo_ra ,
-Fifo_data_err_empty ,
-Fifo_data_err_full ,
-//user interface
-Tx_mac_wa ,
-Tx_mac_wr ,
-Tx_mac_data ,
-Tx_mac_BE ,
-Tx_mac_sop ,
-Tx_mac_eop ,
-//host interface
-FullDuplex ,
-Tx_Hwmark ,
-Tx_Lwmark
-
-);
-input Reset ;
-input Clk_MAC ;
-input Clk_SYS ;
- //MAC_tx_ctrl
-output [7:0] Fifo_data ;
-input Fifo_rd ;
-input Fifo_rd_finish ;
-input Fifo_rd_retry ;
-output Fifo_eop ;
-output Fifo_da ;
-output Fifo_ra ;
-output Fifo_data_err_empty ;
-output Fifo_data_err_full ;
- //user interface
-output Tx_mac_wa ;
-input Tx_mac_wr ;
-input [31:0] Tx_mac_data ;
-input [1:0] Tx_mac_BE ;//big endian
-input Tx_mac_sop ;
-input Tx_mac_eop ;
- //host interface
-input FullDuplex ;
-input [4:0] Tx_Hwmark ;
-input [4:0] Tx_Lwmark ;
-
- parameter TX_FF_DEPTH = 9;
-
+module MAC_tx_FF
+ #(parameter TX_FF_DEPTH = 9)
+ (input Reset ,
+ input Clk_MAC ,
+ input Clk_SYS ,
+ //MAC_tx_ctrl
+ output [7:0] Fifo_data ,
+ input Fifo_rd ,
+ input Fifo_rd_finish ,
+ input Fifo_rd_retry ,
+ output Fifo_eop ,
+ output Fifo_da ,
+ output Fifo_ra ,
+ output Fifo_data_err_empty ,
+ output Fifo_data_err_full ,
+ //user interface
+ output Tx_mac_wa ,
+ input Tx_mac_wr ,
+ input [31:0] Tx_mac_data ,
+ input [1:0] Tx_mac_BE ,//big endian
+ input Tx_mac_sop ,
+ input Tx_mac_eop ,
+ //host interface
+ input FullDuplex ,
+ input [4:0] Tx_Hwmark ,
+ input [4:0] Tx_Lwmark );
+
//******************************************************************************
//internal signals
//******************************************************************************
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