[Commit-gnuradio] r7334 - gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src

[jcorgan]

Author: jcorgan
Date: 2008-01-03 21:03:45 -0700 (Thu, 03 Jan 2008)
New Revision: 7334

Modified:
   gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py
Log:
Work in progress.  Lock detect at 2.448G @ 22 dBm, 5.480G @ 14 dBm.

Modified: 
gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py
===================================================================
--- gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py    
2008-01-03 22:53:23 UTC (rev 7333)
+++ gnuradio/branches/developers/jcorgan/xcvr2450/gr-usrp/src/db_xcvr2450.py    
2008-01-04 04:03:45 UTC (rev 7334)
@@ -19,7 +19,7 @@
 # Boston, MA 02110-1301, USA.
 # 
 
-from gnuradio import usrp1
+from gnuradio import usrp1, gru
 import time,math, weakref
 
 from usrpm import usrp_dbid
@@ -35,6 +35,9 @@
 ANTSEL_TX1_RX2 = (1 << 13)  # 1 = Ant 1 to TX, Ant 2 to RX
 ANTSEL_TX2_RX1 = (1 << 12)    # 1 = Ant 2 to TX, Ant 1 to RX
 TX_EN = (1 << 11)           # 1 = TX on, 0 = TX off
+TX_OE_MASK = HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2|ANTSEL_TX2_RX1|TX_EN
+TX_SAFE_IO = HB_PA_OFF|LB_PA_OFF|ANTSEL_TX1_RX2
+TX_TEST_IO = LB_PA_OFF|ANTSEL_TX1_RX2|TX_EN
 
 # RX IO Pins
 LOCKDET = (1 << 15)         # This is an INPUT!!!
@@ -48,7 +51,10 @@
 B5 = (1 << 7)
 B6 = (1 << 6)
 B7 = (1 << 5)
+RX_OE_MASK = EN|RX_EN|RX_HP|B1|B2|B3|B4|B5|B6|B7
+RX_SAFE_IO = EN
 
+
 """
 A few comments about the XCVR2450:
   It is half-duplex.  I.e., transmit and receive are mutually exclusive.
@@ -92,7 +98,6 @@
         self.mimo = 1              # 0 = OFF, 1 = ON
         self.int_div = 192         # 128 = min, 255 = max
         self.frac_div = 0          # 0 = min, 65535 = max
-        self.auto_bsw = 1          # 0 = OFF, 1 = ON
         self.cp_current = 0        # 0 = 2mA, 1 = 4mA
         self.ref_div = 4           # 1 to 7
         self.rssi_hbw = 0          # 0 = 2 MHz, 1 = 6 MHz
@@ -112,7 +117,7 @@
         self.pabias_delay = 15     # 0 = 0, 15 = 7uS
         self.pabias = 0            # 0 = 0 uA, 63 = 315uA
         self.rxgain = 64           # 0 = min, 127 = max
-        self.txgain = 32           # 0 = min, 63 = max
+        self.txgain = 63           # 0 = min, 63 = max
 
         # Initialize chipset
         # TODO: perform reset sequence to ensure power up defaults
@@ -142,7 +147,9 @@
     def set_reg_int_divider(self):
         self.reg_int_divider = (
             ((self.frac_div & 0x03)<<16) | 
-            (self.int_div<<4)            | 3)
+             (self.int_div<<4)           | 3)
+        print "int_div=",self.int_div
+        print "reg_int_divider=",self.reg_int_divider
         self._send_reg(self.reg_int_divider)
 
     # Fractional-Divider Ratio (4)
@@ -167,7 +174,7 @@
             (self.mimo<<17)      |
             (1<<16)              |
             (1<<15)              |
-            (self.auto_bsw<<11)  |
+            (1<<11)              |
             (self.highband<<10)  |
             (self.cp_current<<9) |
             (self.ref_div<<5)    |
@@ -262,12 +269,10 @@
         db_base.db_base.__init__(self, usrp, which)
         self._xcvr = _get_or_make_MAX2829(usrp, which)
 
-        # FIXME -- the write reg functions don't work with 0xffff for masks
-        #self._rx_write_oe(int(), 0x7fff)
-        #self._rx_write_io((), ())
-        #self._tx_write_oe((), 0x7fff)
-        #self._tx_write_io((), ())
-        #self.set_auto_tr(True)
+        self._rx_write_io(RX_SAFE_IO, RX_OE_MASK)
+        self._tx_write_io(TX_TEST_IO, TX_OE_MASK)
+        self._rx_write_oe(RX_OE_MASK, ~0)
+        self._tx_write_oe(TX_OE_MASK, ~0)
         
     def __del__(self):
         pass
@@ -293,19 +298,19 @@
 
     def _tx_write_oe(self, value, mask):
         return self._u._write_fpga_reg((FR_OE_0, FR_OE_2)[self._which],
-                                       ((mask & 0xffff) << 16) | (value & 
0xffff))
+                                       gru.hexint((mask << 16) | value))
 
+    def _tx_write_io(self, value, mask):
+        return self._u._write_fpga_reg((FR_IO_0, FR_IO_2)[self._which],
+                                       gru.hexint((mask << 16) | value))
+
     def _rx_write_oe(self, value, mask):
         return self._u._write_fpga_reg((FR_OE_1, FR_OE_3)[self._which],
-                                       ((mask & 0xffff) << 16) | (value & 
0xffff))
+                                       gru.hexint((mask << 16) | value))
 
-    def _tx_write_io(self, value, mask):
-        return self._u._write_fpga_reg((FR_IO_0, FR_IO_2)[self._which],
-                                       ((mask & 0xffff) << 16) | (value & 
0xffff))
-
     def _rx_write_io(self, value, mask):
         return self._u._write_fpga_reg((FR_IO_1, FR_IO_3)[self._which],
-                                       ((mask & 0xffff) << 16) | (value & 
0xffff))
+                                       gru.hexint((mask << 16) | value))
 
     def _tx_read_io(self):
         t = self._u._read_fpga_reg((FR_RB_IO_RX_A_IO_TX_A, 
FR_RB_IO_RX_B_IO_TX_B)[self._which])
@@ -343,12 +348,25 @@
         """
         return True
 
-    #FIXME: temporary for debugging
+
     def freq_range(self):
-       return (2.4e9, 2.5e9, 1e6)
+       return (2.4e9, 6e9, 1e6)
 
-    #FIXME: temporary for debugging
+
     def set_freq(self, freq):
+        if freq < 2.4e9 or freq > 6e9:
+            raise ValueError("Frequency out of range")
+
+        self._xcvr.freq = freq
+        self._xcvr.ref_div = 2
+        self._xcvr.frac_div = 0
+        self._xcvr.int_div = 137
+        
+        self._xcvr.set_reg_int_divider()
+        self._xcvr.set_reg_frac_divider()
+        self._xcvr.set_reg_bandselpll()
+
+        print self._lock_detect()
        return (True, freq)
        
     #FIXME: temporary for debugging