[Commit-gnuradio] r7273 - usrp2/trunk/fpga/top/u2_fpga

[matt]

Author: matt
Date: 2007-12-26 16:21:39 -0700 (Wed, 26 Dec 2007)
New Revision: 7273

Modified:
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
   usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
Log:
new files, moved around others


Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-26 23:21:14 UTC 
(rev 7272)
+++ usrp2/trunk/fpga/top/u2_fpga/u2_fpga_top.prj        2007-12-26 23:21:39 UTC 
(rev 7273)
@@ -17,6 +17,8 @@
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ibuf.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_bpcu.v"
+verilog work "../../opencores/8b10b/encode_8b10b.v"
+verilog work "../../opencores/8b10b/decode_8b10b.v"
 verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
 verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
 verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
@@ -39,6 +41,8 @@
 verilog work "../../control_lib/cascadefifo2.v"
 verilog work "../../control_lib/cascadefifo.v"
 verilog work "../../control_lib/CRC16_D16.v"
+verilog work "../../timing/time_sender.v"
+verilog work "../../timing/time_receiver.v"
 verilog work "../../serdes/serdes_tx.v"
 verilog work "../../serdes/serdes_rx.v"
 verilog work "../../serdes/serdes_fc_tx.v"
@@ -72,7 +76,7 @@
 verilog work "../../control_lib/dcache.v"
 verilog work "../../control_lib/buffer_int.v"
 verilog work "../../timing/timer.v"
-verilog work "../../timing/pps.v"
+verilog work "../../timing/time_sync.v"
 verilog work "../../serdes/serdes.v"
 verilog work "../../sdr_lib/tx_control.v"
 verilog work "../../sdr_lib/rx_control.v"