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[Commit-gnuradio] r6709 - in gnuradio/branches/developers/matt/u2f/openc
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6709 - in gnuradio/branches/developers/matt/u2f/opencores/ucsys: . src src/tb src/uart/tb src/ucore src/ucore/tb tools |
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Date: |
Fri, 26 Oct 2007 16:21:32 -0600 (MDT) |
Author: matt
Date: 2007-10-26 16:21:30 -0600 (Fri, 26 Oct 2007)
New Revision: 6709
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/README_meehan
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/Makefile
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/data_mem.data
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/inst_mem.code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/Makefile
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/Makefile
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/data_mem.data
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/debug.sav
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/inst_mem.code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/meehanNotes
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/wavefile.sav
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile.orig
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/init.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort.s
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code_sw
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_timtest
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data.data
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code.asm
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code.code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz.s
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.s
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sortlib.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_sort
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code_sw
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_timtest
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.asm
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem.data
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem.asm
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem.code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.asm
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.s
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.c
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.o
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.s
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/data_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/inst_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/uart_tb.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/pps_rf.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/regfile.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ram.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/rom.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ucore_tb.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore_defines.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem.data
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.asm
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.code
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem_init.v
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.c
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.s
Log:
changes from Tim Meehan, 10/25/07
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/README_meehan
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/README_meehan
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/README_meehan
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,79 @@
+
+This tree contains some minor modifications to ucore to compile and simulate
+under Icarus Verilog.
+
+******Simple directions:
+
+#UART
+cd ucsys-0.0.1/src/uart/tb
+make
+./uart_tb
+
+let run for a bit then stop
+
+now compare uart.send and uart.receive. It would be nice to have
+a "make check" but
+
+
+#UCORE
+cd ucsys-0.0.1/src/ucore/tb
+make
+./ucore_tb
+
+let run for a bit then stop
+Take a look at log.ram you should
+see Move ... Load ... and lots of ABC...
+
+The images that are there inst_mem.code and data_mem.code are for
+the authors test_code.asm file in the tools directory
+
+# Compiling C code
+
+cd ucsys-0.0.1/tools/
+I have a very simple example tim_test.c
+
+you must have the mips cross tools installed
+and you must change the Makefile to the correct
+location of the tools (first 6 lines of Makefile)
+
+make tim_test
+
+this creates new inst_mem.code and data_mem.code files and places them in
+the src/ucore/tb directory.
+
+In order the simulate the gcc compiled code
+you must change the ucore_defines to set the ram in the
+correct location (the simulator does not model all of the
+32 bit space). open src/ucore/ucore_defines and uncomment the
+correct line around line 103 (search for tjm). NOTE inorder to
+run the test_code.asm file again you will have to change this back.
+It is very awkward but for now it works.
+
+
+
+
+
+******Things to do if we are going to move forward with ucore
+
+Synth and PAR
+
+write some automatic "go/ no go" test benches that are called
+with make check.
+
+fix issues with ucsys ( why won't it compile)
+
+fix tool chain so we don't have to manually change defines
+
+Lots of testing
+
+
+******Things that don't work
+
+The ucsys code will not compile see output from "make" below. It generates an
internal error in the icarus compiler. I started
+down the path of going through vvp_process.c to try to figure it out and quit
+
+iverilog -o ucsys_tb ucsys_tb.v -I ../ -I ../ucore/
../data_mem/data_mem_single.v ../inst_mem/inst_mem_single.v -y ../uart/ -y ../
-y ./ -y ../misc/ -y ../ucore/ ../misc/glbl.v
+ivl: vvp_process.c:129: set_to_lvariable: Assertion `!word_ix' failed.
+sh: line 1: 3479 Done /usr/local/lib/ivl/ivlpp -L
-F/tmp/ivrlg289b1c65 -f/tmp/ivrlg89b1c65
+ 3480 Aborted | /usr/local/lib/ivl/ivl
-C/tmp/ivrlh89b1c65 -C/usr/local/lib/ivl/vvp.conf -- -
+make: *** [all] Error 134
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/data_mem_init.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/data_mem_init.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/data_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,78 +1,7 @@
-/////////////////////////////////////////////////////////////////////
-//// Author: Zhangfeifei ////
-//// ////
-//// Advance Test Technology Laboratory, ////
-//// Institute of Computing Technology, ////
-//// Chinese Academy of Sciences ////
-//// ////
-//// If you encountered any problem, please contact : ////
-//// Email: address@hidden or address@hidden ////
-//// Tel: +86-10-6256 5533 ext. 5673 ////
-//// ////
-//// Downloaded from: ////
-//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2005-2006 Zhangfeifei ////
-//// address@hidden ////
-//// ////
-//// ////
-//// This source file may be used and distributed freely without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and any derivative work contains the ////
-//// original copyright notice and the associated disclaimer. ////
-//// ////
-//// Please let the author know if it is used ////
-//// for commercial purpose. ////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Date of Creation: 2005.12.3 ////
-//// ////
-//// Version: 0.0.1 ////
-//// ////
-//// Description: define the init value of the data_mem, ////
-//// which is generated using block_ram ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Change log: ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-`ifndef __DATA_INIT__
-`define __DATA_INIT__
-
-`define INIT_DATA_MEM \
-defparam bank0.INIT_00 = 256'h9400000 ;\
-defparam bank1.INIT_00 = 256'hb344000 ;\
-defparam bank2.INIT_00 = 256'h1910000 ;\
-defparam bank3.INIT_00 = 256'h158c000 ;\
-defparam bank4.INIT_00 = 256'h1fbc000 ;\
-defparam bank5.INIT_00 = 256'h3800000 ;\
-defparam bank6.INIT_00 = 256'h3400000 ;\
-defparam bank7.INIT_00 = 256'h0400000 ;\
-defparam bank8.INIT_00 = 256'h0000000 ;\
-defparam bank9.INIT_00 = 256'h0000000 ;\
-defparam banka.INIT_00 = 256'h0000000 ;\
-defparam bankb.INIT_00 = 256'h0000000 ;\
-defparam bankc.INIT_00 = 256'h0000000 ;\
-defparam bankd.INIT_00 = 256'h0000020 ;\
-defparam banke.INIT_00 = 256'h0000000 ;\
-defparam bankf.INIT_00 = 256'h0000008
-
-`endif
+`ifndef __DATA_INIT__
+`define __DATA_INIT__
+
+`define INIT_DATA_MEM defparam bank0.bank0.INIT_00 = 256'h0
+
+
+`endif
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/inst_mem_init.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/inst_mem_init.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/inst_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,111 +1,134 @@
-/////////////////////////////////////////////////////////////////////
-//// Author: Zhangfeifei ////
-//// ////
-//// Advance Test Technology Laboratory, ////
-//// Institute of Computing Technology, ////
-//// Chinese Academy of Sciences ////
-//// ////
-//// If you encountered any problem, please contact : ////
-//// Email: address@hidden or address@hidden ////
-//// Tel: +86-10-6256 5533 ext. 5673 ////
-//// ////
-//// Downloaded from: ////
-//// http://www.opencores.org/pdownloads.cgi/list/ucore ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Copyright (C) 2005-2006 Zhangfeifei ////
-//// address@hidden ////
-//// ////
-//// ////
-//// This source file may be used and distributed freely without ////
-//// restriction provided that this copyright statement is not ////
-//// removed from the file and any derivative work contains the ////
-//// original copyright notice and the associated disclaimer. ////
-//// ////
-//// Please let the author know if it is used ////
-//// for commercial purpose. ////
-//// ////
-//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
-//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
-//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
-//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
-//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
-//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
-//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
-//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
-//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
-//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
-//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
-//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
-//// POSSIBILITY OF SUCH DAMAGE. ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// ////
-//// Date of Creation: 2005.12.3 ////
-//// ////
-//// Version: 0.0.1 ////
-//// ////
-//// Description: define the init value of the inst_mem, ////
-//// which is generated using block_ram ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-//// ////
-//// Change log: ////
-//// ////
-/////////////////////////////////////////////////////////////////////
-
-`ifndef __INST_INIT__
-`define __INST_INIT__
-
-`define INIT_INST_MEM \
-defparam bank0.INIT_00 =
256'h4004014104252400402240040040141042580120e848e8400000100000c02040 ;\
-defparam bank0.INIT_01 =
256'h3800102f0c34040c0ef200810430200040c05ac9e23529680000000001022400 ;\
-defparam bank0.INIT_02 = 256'h000430d0f0cebc ;\
-defparam bank1.INIT_00 =
256'h8808008c3820286282008108808008c3820aaa96505f0a006c6c800900cc1080 ;\
-defparam bank1.INIT_01 =
256'h9420f05004930c100edcc8400c037023c102304c2300380488286c6c2a000810 ;\
-defparam bank1.INIT_02 = 256'h007c0000012540 ;\
-defparam bank2.INIT_00 =
256'h08708406608a409708240b508708406608aa03e9faf5f5f7fc01ac04000c0004 ;\
-defparam bank2.INIT_01 =
256'h68033024c40f0c00c001c0c00c000000c000a0cc232a08840013fc015c2240b5 ;\
-defparam bank2.INIT_02 = 256'h008c03a0841ae1 ;\
-defparam bank3.INIT_00 =
256'h00000000000000000030000000000000000003c0f0f0f0f001558800000c0004 ;\
-defparam bank3.INIT_01 =
256'h14003010c40f0c000000c0c00c000000c00030cc030000000010015500030000 ;\
-defparam bank3.INIT_02 = 256'h00cc000720c5c8 ;\
-defparam bank4.INIT_00 =
256'h0000000000000000003000000000000000000000000000000000cc00000c0000 ;\
-defparam bank4.INIT_01 =
256'h28003022e00f0c0a0000c2c00c280000c0a030cc030000000000000000030000 ;\
-defparam bank4.INIT_02 = 256'h00cc280000cac0 ;\
-defparam bank5.INIT_00 =
256'h8008008008020800803080080080080080800000000000000000ce00080c00a0 ;\
-defparam bank5.INIT_01 =
256'h14003011d00f0c0f0000c3c00c3c0000c05030cc032200000000000002030800 ;\
-defparam bank5.INIT_02 = 256'h00cc140200c5c0 ;\
-defparam bank6.INIT_00 =
256'hc00c00c20c000c00c030c00c00c00c20c0000000000000000000ec00000c00c0 ;\
-defparam bank6.INIT_01 =
256'h28003021d01f0c050010c2c00c280000c0a070cc130104400000000003030c00 ;\
-defparam bank6.INIT_02 = 256'h00cc3c5554cae5 ;\
-defparam bank7.INIT_00 =
256'hc00c00c00c0a0c00c030c00c00c00c00c0a00000000000000000fc00080c02c0 ;\
-defparam bank7.INIT_01 =
256'h14003010c00f0c000000c0c00c000000c00030cc031400000000000003030c00 ;\
-defparam bank7.INIT_02 = 256'h00cc00000005c0 ;\
-defparam bank8.INIT_00 =
256'h04004004006010400621041040040040060ec7bbeeeeeee06c6f500100040115 ;\
-defparam bank8.INIT_01 =
256'haa0f82e22805c0ae838c4208409ac2020b00237823a0060002106c6f20121041 ;\
-defparam bank8.INIT_02 = 256'h0030aabae12a38 ;\
-defparam bank9.INIT_00 =
256'h09d08c08d080d09d090c09d09d08c08d080014010000000c0157ef0388ac033a ;\
-defparam bank9.INIT_01 =
256'h01000000001100100014400140110004005024961160061100300157c420c09d ;\
-defparam bank9.INIT_02 = 256'h00001000414010 ;\
-defparam banka.INIT_00 =
256'h86c84d84e852c86c851f86c86c84d84e858a542b0a0a0a0fffffd503802c039d ;\
-defparam banka.INIT_01 =
256'h0220020000aa800008228800008000200802222020a0000a883bffffe211f86c ;\
-defparam banka.INIT_02 = 256'h00008000000000 ;\
-defparam bankb.INIT_00 =
256'h08a08808a08380ab0a0809808a08808a08caa82a0a0a0a0aaaaaa80288280200 ;\
-defparam bankb.INIT_01 =
256'h9134110804eac4c045628c4ac4401234440369187262152ace2eaaaaac208098 ;\
-defparam bankb.INIT_02 = 256'h00048190402490 ;\
-defparam bankc.INIT_00 =
256'hceecceceecc2ccfecf2ececceecceceecc8ffc3f0f0f0f0ffffffc0bc03c03cc ;\
-defparam bankc.INIT_01 =
256'h0030000000c0000000000c00000000300003404100000400cc3ffffffb32ecec ;\
-defparam bankc.INIT_02 = 256'h00000000000000 ;\
-defparam bankd.INIT_00 =
256'h0dd0cd0cd0d0d0dd0f1d0dd0dd0cd0cd0d05fd555555555fffff4701c0742137 ;\
-defparam bankd.INIT_01 =
256'h1f0d53740405c4d042054041c4c1400d4d0015550140011b0313ffffd431d0dd ;\
-defparam bankd.INIT_02 = 256'h0014c100010700 ;\
-defparam banke.INIT_00 =
256'h00200200202020220012022002002002020a02aaaaaaaaaaaaaa8b0200a8033b ;\
-defparam banke.INIT_01 =
256'h3e0a90b44802842086c880428402900a42001a6a400012260020000008012022 ;\
-defparam banke.INIT_02 = 256'h00640200020f40 ;\
-defparam bankf.INIT_00 =
256'h0a808808808080880a080880a8088088080aa8280a0a0a0aaaaa000484200000 ;\
-defparam bankf.INIT_01 =
256'h0208020000008080000000088080020808000028028000020202aaaaa0208088 ;\
-defparam bankf.INIT_02 = 256'h00008000000000
-
-`endif
+`ifndef __INST_INIT__
+`define __INST_INIT__
+
+`define INIT_INST_MEM \
+defparam bank0.INIT_00 =
256'h48082d100c4cd000c3d3020d20234400840c0b40014c0b480144048c41200000 ;\
+defparam bank0.INIT_01 =
256'h2920daf28920da428920daf108920da610010038c04200110001210123002123 ;\
+defparam bank0.INIT_02 =
256'h0a0880080230200880a0b08a0a08840854008090d83cda0d2681c814c089e520 ;\
+defparam bank0.INIT_03 =
256'h8000204031391002081cc0e400081f0e4c0002044e4800a4400c848809880984 ;\
+defparam bank0.INIT_04 =
256'h2044e400009300207c39200008100c4e440082043139000208130e4c008130e4 ;\
+defparam bank0.INIT_05 =
256'h480014408094008094c0c8402480c840244004c0013000024800020404e44000 ;\
+defparam bank0.INIT_06 =
256'hc00acc0420141033b0024c0d200d10313300321002480c840244040900130001 ;\
+defparam bank0.INIT_07 = 256'h0002 ;\
+defparam bank1.INIT_00 =
256'h0400001004840100000000600000000448800004000000000000044cd3a00000 ;\
+defparam bank1.INIT_01 =
256'h0301f8300301f8b00301f81200301f87100d1030007000d00212000133101210 ;\
+defparam bank1.INIT_02 =
256'h020b8c020e2008388061b182020b8800b4808a5800880021000b80b440038f10 ;\
+defparam bank1.INIT_03 =
256'h40201042794010000019d90040001a5000020106500000000080c000014c014c ;\
+defparam bank1.INIT_04 =
256'h102500c0020200006940200804109e5008000004754020000017500400017500 ;\
+defparam bank1.INIT_05 =
256'h44000440000440000400000044000000440040cc003002c80c02010b2500c020 ;\
+defparam bank1.INIT_06 =
256'h0804040010101013f10000000010000213300000044800000448000120010000 ;\
+defparam bank1.INIT_07 = 256'h0100 ;\
+defparam bank2.INIT_00 =
256'h0800002000410200000200002000080c8884050805080508050808c800440000 ;\
+defparam bank2.INIT_01 =
256'h1400c4f24400c4924400c44144400c4d202c200c803202c20232300222000104 ;\
+defparam bank2.INIT_02 =
256'h02080800002000008020b082c20808044080d724257c295c0a54c44080444020 ;\
+defparam bank2.INIT_03 =
256'h80000000f4002000000fe40080000f800800000100080000808888c008080808 ;\
+defparam bank2.INIT_04 =
256'h001000800d0200003e00200000003d0008000000f8002000000f80080000f800 ;\
+defparam bank2.INIT_05 =
256'h8804488045088045088044450880444508808880002000440800000110008000 ;\
+defparam bank2.INIT_06 =
256'h080808002020202c3200080c202c202222001111508804445088045220020144 ;\
+defparam bank2.INIT_07 = 256'h0000 ;\
+defparam bank3.INIT_00 =
256'h4404051020005102405100051001440444440044004400440044044448422000 ;\
+defparam bank3.INIT_01 =
256'h0000c0d00000c0c00000c00000000c0710001000400100010111110111100001 ;\
+defparam bank3.INIT_02 =
256'h041004041010104040413104c410040000404238003c000c0000c00040000110 ;\
+defparam bank3.INIT_03 =
256'h40000000355510000004d5544000055544000001554400144044444400440044 ;\
+defparam bank3.INIT_04 =
256'h00955440055100001555100000000d5544000000355510000003554400003554 ;\
+defparam bank3.INIT_05 =
256'h0400104000504000504000005040000050404444011000854400000115544000 ;\
+defparam bank3.INIT_06 =
256'h4400440110011000b100440d100d101111100000050400000504000410110001 ;\
+defparam bank3.INIT_07 = 256'h0200 ;\
+defparam bank4.INIT_00 =
256'h000808003000800380800208002a000000000000000000000000000000000000 ;\
+defparam bank4.INIT_01 =
256'h0000c0c00000c0e00000c03000000c0100000000000000000000000000000002 ;\
+defparam bank4.INIT_02 =
256'h000000000000000000003000c000000000004128003c000c0000c00000000300 ;\
+defparam bank4.INIT_03 =
256'h00000000b00000000002c0000000000000000000000000000000000000000000 ;\
+defparam bank4.INIT_04 =
256'h00800000080000000000000000002c0000000000b0000000000b00000000b000 ;\
+defparam bank4.INIT_05 =
256'h000000000000000000000000d0000000d0000000000000800000000200000000 ;\
+defparam bank4.INIT_06 =
256'h000000000000000f0000000300030000000000000d0000000d00000400000000 ;\
+defparam bank4.INIT_07 = 256'h0300 ;\
+defparam bank5.INIT_00 =
256'h000d300039080003d30003800038000000000800080008000800000000000000 ;\
+defparam bank5.INIT_01 =
256'h0000c0f00000c0d00000c02000000c0300000000000000000000000000002400 ;\
+defparam bank5.INIT_02 =
256'h000000000000000000003000c00000000000830c023c008c0020c00000000000 ;\
+defparam bank5.INIT_03 =
256'h00000000300000000000c0000000000000000000000000000000000000000000 ;\
+defparam bank5.INIT_04 =
256'h00000000000000000000000000000c0000000000300000000003000000003000 ;\
+defparam bank5.INIT_05 =
256'h0000000000000000000000000000000000000000000000800000000a00000000 ;\
+defparam bank5.INIT_06 =
256'h000000000000000f000300010001000000000000000000000000000000000000 ;\
+defparam bank5.INIT_07 = 256'h0000 ;\
+defparam bank6.INIT_00 =
256'h0004100034040003410001400014000000000400040004000400000000000000 ;\
+defparam bank6.INIT_01 =
256'h2400c0f28400c0c28400c03088400c0100100000000001000000000000001020 ;\
+defparam bank6.INIT_02 =
256'h02080000000000000020b082c20800080000302c2a3c2a8c0aa0c80000840000 ;\
+defparam bank6.INIT_03 =
256'h00000000700000000001c0000000000000000000000000000000000004000400 ;\
+defparam bank6.INIT_04 =
256'h00000000000000000000000000001c0000000000700000000007000000007000 ;\
+defparam bank6.INIT_05 =
256'h4000040000040000040000000400000004000000000000000000000c00000000 ;\
+defparam bank6.INIT_06 =
256'hc00bc00000200020f00100080028000000000000004000000040000200000000 ;\
+defparam bank6.INIT_07 = 256'h0003 ;\
+defparam bank7.INIT_00 =
256'h4002050032005003205000050001400000000000000000000000000000000000 ;\
+defparam bank7.INIT_01 =
256'h0008c0f00008c0c00008c03000008c0000000000000000000000000000000801 ;\
+defparam bank7.INIT_02 =
256'h000000000000000000003000c00000000000021c003c000c0000c00000000000 ;\
+defparam bank7.INIT_03 =
256'h00000000300000000000c0000000000000000000000000000000000000000000 ;\
+defparam bank7.INIT_04 =
256'h00000000000000000000000000000c0000000000300000000003000000003000 ;\
+defparam bank7.INIT_05 =
256'h0000000000000000000000005000000050000000000000000000000c00000000 ;\
+defparam bank7.INIT_06 =
256'hc003c00000000000f00000040004000000000000050000000500000400000000 ;\
+defparam bank7.INIT_07 = 256'h0003 ;\
+defparam bank8.INIT_00 =
256'ha9faeaa7fafbaa7faeaa7fbaa7faa9eaaaa9f0a9f0a9f0a9f0a9eaaa83905500 ;\
+defparam bank8.INIT_01 =
256'h02157ce002157ce002157ce0002157cea783a7529e8a783a7aaaaa7aaaa7eb2e ;\
+defparam bank8.INIT_02 =
256'hd65fa9d452a7514a9d65f597965fa9c0fa9fc54010f8103e040f80fa9c03cea7 ;\
+defparam bank8.INIT_03 =
256'h9e0f8461fe4ea7718793ed3a9d83b393a9e0f86793a9fa3a9eaaaaa9e0e9e0e9 ;\
+defparam bank8.INIT_04 =
256'h86393a9fe3ea763e0e4ea783e1083f93a9e420e0fa4ea760838f93a9d838f93a ;\
+defparam bank8.INIT_05 =
256'h29ebf29e83f29e83f29e8003f29e8003f29eaaa9e2a7f8ffa9e0f863f93a9e0f ;\
+defparam bank8.INIT_06 =
256'ha9cfa9c2a73ea73faa7ea9c2a73ea7aaaaa7a000ff29e8003f29ebe8a7aa7abf ;\
+defparam bank8.INIT_07 = 256'h0070 ;\
+defparam bank9.INIT_00 =
256'h014000050000005000005000050001400001400140014001400140002955f55f ;\
+defparam bank9.INIT_01 =
256'h4100100501001005010010051010010005140554141051405000005000050040 ;\
+defparam bank9.INIT_02 =
256'h5450015554055550154505141450015000154555500154005500100015010005 ;\
+defparam bank9.INIT_03 =
256'h15cbcc200ffa05f072840fe81776843e815cbce3fe8166281400000145014501 ;\
+defparam bank9.INIT_04 =
256'hce3fe816e3a05dca50fa0572f30803fe817c1ca103fa05d072803e81772803e8 ;\
+defparam bank9.INIT_05 =
256'h81400814140814140814155408141554081400014005b80e815cbce03fe815cb ;\
+defparam bank9.INIT_06 =
256'h0150015405400540005001540540050000050555008141554081400205005000 ;\
+defparam bank9.INIT_07 = 256'h0055 ;\
+defparam banka.INIT_00 =
256'h014000052808005200005080050001400001400140014001400140001555d805 ;\
+defparam banka.INIT_01 =
256'h0002020000020200000202000000202005200500140052005000005000052020 ;\
+defparam banka.INIT_02 =
256'h4200014000050000142000800200014000140200000000000000000014002005 ;\
+defparam banka.INIT_03 =
256'h1520004380000500402200001448000001520004000144001400000148014801 ;\
+defparam banka.INIT_04 =
256'h0000001400005100800005480030600001401200800005104808000144028000 ;\
+defparam banka.INIT_05 =
256'h4140041400841400841400008414000084140001400502800152000a00001520 ;\
+defparam banka.INIT_06 =
256'h0140014005000508005001400500050000050000084140000841400105005000 ;\
+defparam banka.INIT_07 = 256'h0050 ;\
+defparam bankb.INIT_00 =
256'h22a0848a942448a90848a8448a8122a22222a122a122a122a122a22200088888 ;\
+defparam bankb.INIT_01 =
256'h80110508001105080011050a200110508a908aa22a88a908a88888a8888a9091 ;\
+defparam bankb.INIT_02 =
256'ha9a422a9a48aa6922a9a4a6929a422a0422aca22a042a010a80420422a00508a ;\
+defparam bankb.INIT_03 =
256'h2aba882140008aa0a69100022aa6900022aba8a00022aa022a222222a422a422 ;\
+defparam bankb.INIT_04 =
256'h8a00022aa008aa9a40008aaea218100022a8a9a440008aa0a6940022aa694002 ;\
+defparam bankb.INIT_05 =
256'h22a4422a65422a65422a6665422a6665422a2222a08aa94022aba8a500022aba ;\
+defparam bankb.INIT_06 =
256'h22a422a48a908a9448a822a48a908a88888a99995422a6665422aaa08a88a944 ;\
+defparam bankb.INIT_07 = 256'h00a9 ;\
+defparam bankc.INIT_00 =
256'h22a0808a802008a80808a8008a8022a22222a022a022a022a022a2223008c00c ;\
+defparam bankc.INIT_01 =
256'h800000080000000800000008200000008a808a822a08a808a88888a8888a8080 ;\
+defparam bankc.INIT_02 =
256'ha08022a0808a82022a080820208022a0022a000200020000800020022a00008a ;\
+defparam bankc.INIT_03 =
256'h2aba882000008aa0a28000022aa2800022aba8a00022aa022a222222a022a022 ;\
+defparam bankc.INIT_04 =
256'h8a00022aa008aa8a00008aaea208000022a828a000008aa0a2800022aa280002 ;\
+defparam bankc.INIT_05 =
256'h22a0022a20022a20022a2220022a2220022a2222a08aa80022aba8a000022aba ;\
+defparam bankc.INIT_06 =
256'h22a022a08a808a8008a822a08a808a88888a88880022a2220022a2008a88a800 ;\
+defparam bankc.INIT_07 = 256'h00a8 ;\
+defparam bankd.INIT_00 =
256'hc403071003417100307100171001c4044444004400440044004404445d577777 ;\
+defparam bankd.INIT_01 =
256'h001d4150001d4150001d41500001d41510051014401100510111110111100d05 ;\
+defparam bankd.INIT_02 =
256'h000144030d1008244000100040014400144041dc001400050001401440001510 ;\
+defparam bankd.INIT_03 =
256'h40000041755510010415d5544000055544000005554400144044444401440144 ;\
+defparam bankd.INIT_04 =
256'h00d55440095100105555100000105d5544004105755510020827554400c37554 ;\
+defparam bankd.INIT_05 =
256'h040dd040477040477040000370400003704044440110007544000001d5544000 ;\
+defparam bankd.INIT_06 =
256'h44014405100510077100c4011005101111100000a7040000370400141011029d ;\
+defparam bankd.INIT_07 = 256'h0202 ;\
+defparam banke.INIT_00 =
256'heea38fbaa3e3fbaa38fba83fba83eeaeeeeea0eea0eea0eea0eeaeeeffffffff ;\
+defparam banke.INIT_01 =
256'h801d81a8001d81b8001d81ea2001d81fba8fbaaeeabba8fbabbbbbabbbba8f8f ;\
+defparam banke.INIT_02 =
256'ha8a3eeaaabbaaaaeea8a2a28a8a3eea03eea83fe802a800ba003a03eea001fba ;\
+defparam banke.INIT_03 =
256'hea8a9820ffffbaa0a28ffffeeaa69fffeea8a9a3ffeeaa7eeaeeeeeea3eea3ee ;\
+defparam banke.INIT_04 =
256'h9a3ffeeaa3fbaa9a7fffbaa2a6083fffeea828a3ffffbaa1a69fffeeaa69fffe ;\
+defparam banke.INIT_05 =
256'h2ea3a2ea22f2ea22f2ea2222f2ea2222f2eaeeeea3baa8bfeea8a9a2fffeea8a ;\
+defparam banke.INIT_06 =
256'heea3eeafba8fba8ffba8eeafba8fbabbbbba8888ef2ea2222f2ea22cbabba93a ;\
+defparam banke.INIT_07 = 256'h00ab ;\
+defparam bankf.INIT_00 =
256'h22a0808a802008a80808a8008a8022a22222a022a022a022a022a22200000000 ;\
+defparam bankf.INIT_01 =
256'h800000080000000800000008200000008a808a822a08a808a88888a8888a8080 ;\
+defparam bankf.INIT_02 =
256'ha08022a0808a82022a080820208022a0022a000200020000800020022a00008a ;\
+defparam bankf.INIT_03 =
256'h2a8a882000008aa0a28000022aa2800022a8a8a00022aa022a222222a022a022 ;\
+defparam bankf.INIT_04 =
256'h8a00022aa008aa8a00008aa2a208000022a828a000008aa0a2800022aa280002 ;\
+defparam bankf.INIT_05 =
256'h22a8822aaa022aaa022aaaaa022aaaaa022a2222a08aa80022a8a8a000022a8a ;\
+defparam bankf.INIT_06 =
256'h22a022a08a808a8008a822a08a808a88888aaaaaa022aaaaa022aaa08a88aa88 ;\
+defparam bankf.INIT_07 = 256'h00a8
+
+`endif
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/Makefile
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/Makefile
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/Makefile
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,4 @@
+all:
+ iverilog -o ucsys_tb ucsys_tb.v -I ../ -I ../ucore/
../data_mem/data_mem_single.v ../inst_mem/inst_mem_single.v -y ../uart/ -y ../
-y ./ -y ../misc/ -y ../ucore/ ../misc/glbl.v
+clean:
+ rm ucsys_tb log.excute log.inst log.ram log.reg log.uart
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/data_mem.data
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/data_mem.data
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/data_mem.data
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,15 @@
+00000000
+80000000
+08000000
+00000000
+00000000
+00000000
+00000000
+000003c4
+00000310
+00000284
+0000035c
+00005b61
+00003d5d
+0000000a
+000a0a0a
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/inst_mem.code
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/inst_mem.code
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/tb/inst_mem.code
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,284 @@
+3c190000
+27390050
+3c1d0800
+0320f809
+37bd8000
+00000000
+08000006
+00000000
+00000000
+27bdfffc
+afa80000
+2408000f
+00000000
+40888800
+00000000
+8fa80000
+27bd0004
+42000018
+00000000
+00000000
+3c1c0800
+279cffb0
+0399e021
+27bdffa8
+afbf0050
+afb7004c
+afb60048
+afb50044
+afb40040
+afb3003c
+afb20038
+afb10034
+afb00030
+afbc0010
+240200f0
+240300f1
+a7a20018
+a7a3001a
+240200f2
+240300f3
+a7a2001c
+a7a3001e
+240200f4
+240300f5
+a7a20020
+a7a30022
+240200f6
+240300f7
+27b70018
+a7a20024
+a7a30026
+240200f8
+240300f9
+8f950008
+8f940008
+8f930008
+a7a20028
+a7a3002a
+00008021
+02e08821
+2412000a
+8f990020
+00000000
+0320f809
+26a4002c
+8fbc0010
+02002021
+8f99001c
+00000000
+0320f809
+26100001
+8fbc0010
+00000000
+8f990020
+00000000
+0320f809
+26840030
+8fbc0010
+86240000
+8f990028
+00000000
+0320f809
+24050010
+8fbc0010
+26640034
+8f990020
+00000000
+0320f809
+26310002
+8fbc0010
+1612ffe2
+00000000
+8f960008
+8f990020
+00000000
+0320f809
+26c40038
+8fbc0010
+27a40018
+8f990024
+00000000
+0320f809
+2405000a
+8fbc0010
+02e08821
+00008021
+2412000a
+8f990020
+00000000
+0320f809
+26a4002c
+8fbc0010
+02002021
+8f99001c
+00000000
+0320f809
+26100001
+8fbc0010
+00000000
+8f990020
+00000000
+0320f809
+26840030
+8fbc0010
+86240000
+8f990028
+00000000
+0320f809
+24050010
+8fbc0010
+26640034
+8f990020
+00000000
+0320f809
+26310002
+8fbc0010
+1612ffe2
+00000000
+8f990020
+00000000
+0320f809
+26c40038
+87a20018
+8fbc0010
+8fbf0050
+8fb7004c
+8fb60048
+8fb50044
+8fb40040
+8fb3003c
+8fb20038
+8fb10034
+8fb00030
+03e00008
+27bd0058
+00000000
+8c820000
+03e00008
+00000000
+03e00008
+aca40000
+18a00016
+24840002
+00001021
+244a0001
+0145102a
+1040000e
+00000000
+00801821
+00004021
+00aa4823
+84660000
+8487fffe
+00000000
+00e6102a
+10400003
+25080001
+a486fffe
+a4670000
+1509fff7
+24630002
+24840002
+14aaffed
+01401021
+03e00008
+00000000
+00042600
+00042603
+24030004
+8c620000
+00000000
+1440fffd
+2402000c
+ac440000
+03e00008
+00000000
+80820000
+00000000
+1040000e
+24030004
+2406000c
+00022e00
+00052e03
+8c620000
+00000000
+1440fffd
+00000000
+acc50000
+24840001
+80820000
+00000000
+1440fff6
+00022e00
+03e00008
+00000000
+24a5fffc
+04a00012
+2407000c
+00a41007
+3042000f
+2843000a
+1060000f
+00000000
+24420030
+00021e00
+00031e03
+24060004
+8cc20000
+00000000
+1440fffd
+00000000
+ace30000
+24a5fffc
+04a1fff1
+00a41007
+03e00008
+00000000
+24420057
+00021600
+1000fff0
+00021603
+14800013
+3c026666
+24030004
+8c620000
+00000000
+1440fffd
+2402000c
+24030030
+ac430000
+03e00008
+00000000
+ac660000
+3c026666
+34426667
+00820018
+00001010
+00021083
+00472023
+1080fff6
+3c026666
+34426667
+00820018
+00043fc3
+24050004
+00001010
+00021083
+00471023
+000218c0
+00021040
+00431021
+00821023
+24420030
+00023600
+00063603
+8ca20000
+00000000
+1440fffd
+2403000c
+1000ffe4
+00000000
+00000000
+00000000
+00000000
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/Makefile
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/Makefile
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/Makefile
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,4 @@
+all:
+ iverilog -o uart_tb uart_tb.v -I ../../ -y ../
+clean:
+ rm uart_tb uart.send uart.receive
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/uart_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/uart_tb.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/uart/tb/uart_tb.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -94,7 +94,7 @@
uart_int_reged <= uart_int;
end
- integer flag,i;
+ integer flag,i,done_tx;
integer sendfile,receivefile;
initial
begin
@@ -126,43 +126,52 @@
rst = 0;
flag = 1;
i = 0;
+ done_tx = 0;
// testing the uart module
while(1)
begin
@(posedge clk);
+// if(done_tx == 0)
+ // begin
flag = 1;
//read the busy signal
while(flag)
begin
- uart_addr <= `UART_ADDR_BUSY;
- uart_req <= 1'b1;
- uart_wen <= 1'b0;
- uart_data_i <= 8'bx;
- //$display($time, , ,"checking the busy signal!");
- @(posedge clk);
- while(~uart_ack) @(posedge clk);
- if(uart_data_o[0] == 1'b1)
- begin
- uart_req = 0;
- flag = 0;//iddle
- end
+ uart_addr <= `UART_ADDR_BUSY;
+ uart_req <= 1'b1;
+ uart_wen <= 1'b0;
+ uart_data_i <= 8'bx;
+// $display($time, , ,"checking the busy signal!");
+ @(posedge clk);
+ while(~uart_ack) @(posedge clk);
+ if(uart_data_o[0] == 0'b1)
+ begin
+ uart_req = 0;
+ flag = 0;//iddle
+ end
end
//send data
- uart_addr <= `UART_ADDR_TXDATA;
- uart_req <= 1'b1;
- uart_wen <= 1'b1;
+// if(done_tx == 0)
+ if(1)
+ begin
+ uart_addr <= `UART_ADDR_TXDATA;
+ uart_req <= 1'b1;
+ uart_wen <= 1'b1;
+ end
if(string[i] != 0)
begin
- uart_data_i = string[i];
- i= i+1;
- end
- else begin
- uart_data_i = string[0];
- i= 1;
- end
- $display($time, , ,"sending txdata,data=%h,char =%c
,i=%d",uart_data_i,uart_data_i,i-1);
- $fwrite(sendfile,"%c",uart_data_i);
+ uart_data_i = string[i];
+ i= i+1;
+ end
+ else begin
+ done_tx = 1;
+ uart_data_i = string[0];
+ i= 1;
+ end
+ $display($time, , ,"sending txdata,data=%h,char =%c
,i=%d",uart_data_i,uart_data_i,i-1);
+ $fwrite(sendfile,"%c",uart_data_i);
+
@(posedge clk);
uart_req <= 1'b0;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/pps_rf.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/pps_rf.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/pps_rf.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -313,8 +313,7 @@
EX_it_ok_o <= #Tp ID_it_ok_i;
EX_inst_o <= #Tp ID_inst_i;
//EX_addr_o <= #Tp ID_addr_i;
- EX_addrA4_o <= #Tp ID_addr_i + 4;
-
+ EX_addrA4_o <= #Tp ID_addr_i + 4;
BP_depra_o <= #Tp dep_ra;
BP_deprb_o <= #Tp dep_rb;
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/regfile.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/regfile.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/regfile.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -57,6 +57,7 @@
`include "ucore_defines.v"
`define BLOCK_RAM
+//`undef BLOCK_RAM
module regfile
(
@@ -80,25 +81,17 @@
input [5:0] portc;
input [31:0] dinc;
- //porta
- input ena;
- input [5:0] porta;
- output [31:0] douta;
- //portb
- input enb;
- input [5:0] portb;
- output [31:0] doutb;
`ifndef BLOCK_RAM
//porta
- //input ena;
- //input [5:0] porta;
- //output reg [31:0] douta;
+ input ena;
+ input [5:0] porta;
+ output reg [31:0] douta;
//portb
- //input enb;
- //input [5:0] portb;
- //output reg [31:0] doutb;
+ input enb;
+ input [5:0] portb;
+ output reg [31:0] doutb;
// The register bank
reg [63:0] mem[31:0];
@@ -122,6 +115,17 @@
end
`else
+
+ //porta
+ input ena;
+ input [5:0] porta;
+ output [31:0] douta;
+ //portb
+ input enb;
+ input [5:0] portb;
+ output [31:0] doutb;
+
+
wire [31 : 0] tempa, tempb;
wire collision_a, collision_b;
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/Makefile
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/Makefile
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/Makefile
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,4 @@
+all:
+ iverilog -o ucore_tb ucore_tb.v -I ../../ -I ../ -y ../ -y ./ -y
../../misc/ ../../misc/glbl.v
+clean:
+ rm ucore_tb log.excute log.inst log.ram log.reg log.uart test.vcd
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/data_mem.data
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/debug.sav
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/debug.sav
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/debug.sav
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,97 @@
+[size] 1219 686
+[pos] 56 -319
+*-14.045819 3588690 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1 -1
address@hidden
+ucore_tb.my_ucore.IF_addr[31:0]
address@hidden
+ucore_tb.my_ucore.IF_bra_target
address@hidden
+ucore_tb.my_ucore.CTRL_inst[31:0]
address@hidden
+ucore_tb.my_ucore.clk_i
address@hidden
+ucore_tb.my_ucore.imem_inst_i[31:0]
+ucore_tb.my_ucore.imem_addr_o[31:0]
+ucore_tb.my_ucore.ID_inst[31:0]
address@hidden
+ucore_tb.my_ucore.dmem_data_i[31:0]
+ucore_tb.my_ucore.EX_mem_addr[31:0]
address@hidden
+ucore_tb.my_ucore.EX_mem_we
address@hidden
+ucore_tb.my_ucore.EX_mem_data[31:0]
+ucore_tb.my_ucore.dmem_data_o[31:0]
address@hidden
+ucore_tb.my_ucore.my_regfile.enc
+ucore_tb.my_ucore.my_regfile.enb
+ucore_tb.my_ucore.my_regfile.ena
address@hidden
+ucore_tb.my_ucore.my_regfile.portc[5:0]
+ucore_tb.my_ucore.my_regfile.portb[5:0]
address@hidden
+ucore_tb.my_ucore.my_regfile.porta[5:0]
+ucore_tb.my_ucore.my_regfile.dinc[31:0]
address@hidden
+ucore_tb.my_ucore.my_bypass.dina[31:0]
+ucore_tb.my_ucore.my_bypass.RF_dataa_o[31:0]
+ucore_tb.my_ucore.my_bypass.WB_reg_data_i[31:0]
+ucore_tb.my_ucore.my_bypass.MEM_reg_data_i[31:0]
+ucore_tb.my_ucore.my_bypass.EX_reg_data_i[31:0]
address@hidden
+ucore_tb.my_ucore.clk_i
address@hidden
+ucore_tb.my_ucore.my_rf.pre_op1[31:0]
+ucore_tb.my_ucore.my_rf.BP_datab_i[31:0]
+ucore_tb.my_ucore.my_rf.BP_dataa_i[31:0]
+ucore_tb.my_ucore.my_rf.EX_op2_o[31:0]
+ucore_tb.my_ucore.my_rf.EX_op1_o[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.op2[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.op1[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.shift_val[4:0]
+ucore_tb.my_ucore.my_ex.my_alu.res_shr[31:0]
+ucore_tb.my_ucore.dmem_raddr_o[31:0]
address@hidden
+ucore_tb.my_ucore.dmem_stb_o
address@hidden
+ucore_tb.my_ucore.dmem_waddr_o[31:0]
address@hidden
+ucore_tb.my_ucore.dmem_we_o
address@hidden
+ucore_tb.my_ucore.my_ctrl.ID_inst_o[31:0]
address@hidden
+ucore_tb.my_ucore.my_id.rst_i
address@hidden
+ucore_tb.my_ucore.my_id.RF_inst_o[31:0]
address@hidden
+ucore_tb.my_ucore.my_id.dmem_rdy_i
+ucore_tb.my_ucore.my_id.EX_rdy_i
+ucore_tb.my_ucore.my_id.alea_i
+ucore_tb.my_ucore.my_id.clk_i
address@hidden
+ucore_tb.my_ucore.my_id.CTRL_inst_i[31:0]
+ucore_tb.my_ucore.my_rf.ID_inst_i[31:0]
address@hidden
+ucore_tb.my_ucore.ID_inst_valid
address@hidden
+ucore_tb.my_ucore.ID_addr[31:0]
+ucore_tb.my_ucore.RF_op1[31:0]
+ucore_tb.my_ucore.RF_op2[31:0]
+ucore_tb.my_ucore.my_regfile.dinc[31:0]
+ucore_tb.my_ucore.my_regfile.porta[5:0]
+ucore_tb.my_ucore.my_ex.my_alu.res_add[32:0]
address@hidden
+ucore_tb.my_ucore.ID_imm_sela
+ucore_tb.my_ucore.ID_imm_selb
address@hidden
+ucore_tb.my_ucore.my_rf.pre_op1[31:0]
+ucore_tb.my_ucore.my_rf.pre_op2[31:0]
address@hidden
+ucore_tb.my_ucore.my_rf.ID_use_regb_i
address@hidden
+ucore_tb.my_ucore.my_rf.BP_datab_i[31:0]
address@hidden
+ucore_tb.my_ucore.my_rf.ID_imm_selb_i
address@hidden
+ucore_tb.my_ucore.my_rf.inst_imm[15:0]
address@hidden
+ucore_tb.my_ucore.my_id.RF_imm_selb_o
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/inst_mem.code
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/inst_mem.code
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/inst_mem.code
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,904 @@
+3c1c0000
+379c0000
+3c040000
+34840000
+3c050000
+34a50000
+3c1d0080
+37bd0000
+3c140080
+36940010
+3415000a
+34160058
+3417000d
+3c180080
+37180004
+3402004d
+a2820000
+3402006f
+a2820000
+34020076
+a2820000
+34020065
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34020041
+00400011
+00001810
+a2830000
+a2970000
+a2950000
+34020062
+a2820000
+34020041
+00400013
+00001812
+a2830000
+a2970000
+a2950000
+34020063
+a2820000
+34020041
+00400011
+00001810
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+34020041
+00400013
+00001812
+a2830000
+a2970000
+a2950000
+34020053
+a2820000
+34020068
+a2820000
+34020069
+a2820000
+34020066
+a2820000
+34020074
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+3c024041
+34424243
+00021a00
+00031e02
+a2830000
+a2970000
+a2950000
+34020062
+a2820000
+3c024041
+34424243
+34030008
+00621804
+00031e02
+a2830000
+a2970000
+a2950000
+34020063
+a2820000
+3c024041
+34424243
+00021c03
+a2830000
+3c028400
+00021e43
+2063ff80
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+3c024041
+34424243
+34030010
+00621807
+a2830000
+34030019
+3c028400
+00621807
+2063ff80
+a2830000
+a2970000
+a2950000
+34020065
+a2820000
+3c024041
+34424243
+00021c02
+a2830000
+3c028400
+00021e42
+a2830000
+a2970000
+a2950000
+34020066
+a2820000
+3c024041
+34424243
+34030010
+00622006
+a2840000
+34030019
+3c028400
+00621806
+a2830000
+a2970000
+a2950000
+34020044
+a2820000
+3402006f
+a2820000
+3402006e
+a2820000
+34020065
+a2820000
+a2970000
+a2950000
+34020041
+a2820000
+34020072
+a2820000
+34020069
+a2820000
+34020074
+a2820000
+34020068
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34030005
+3404003c
+00641020
+a2820000
+a2970000
+a2950000
+34020062
+a2820000
+3404003c
+20820005
+a2820000
+a2970000
+a2950000
+34020063
+a2820000
+34040032
+2485000f
+a2850000
+a2970000
+a2950000
+34020064
+a2820000
+34030005
+3404003c
+00641020
+a2820000
+a2970000
+a2950000
+34020065
+a2820000
+34021dde
+34030075
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+a2840000
+00002010
+20840019
+a2840000
+2402fb07
+34030013
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+00042022
+a2840000
+3402061c
+2403ffe9
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+00042022
+a2840000
+2402fc7f
+2403fff3
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00002012
+a2840000
+a2970000
+a2950000
+34020066
+a2820000
+3402034d
+3403000d
+14600002
+0043001b
+0007000d
+00001012
+00000000
+00002012
+a2840000
+a2970000
+a2950000
+34020067
+a2820000
+34020005
+3403000d
+00430018
+00000000
+00002012
+a2840000
+2402fffb
+3403000d
+00430018
+00002810
+00002012
+00042022
+00852021
+20840002
+a2840000
+34020005
+2403fff3
+00430018
+00002810
+00002012
+00042022
+00852021
+20840003
+a2840000
+2402fffb
+2403fff3
+00430018
+00002810
+00002012
+00852021
+20840003
+a2840000
+3c04fe98
+348462e5
+3c050006
+34a58db8
+00850018
+00003010
+24c7097a
+a2870000
+a2970000
+a2950000
+34020068
+a2820000
+34020005
+3403000d
+00430019
+00000000
+00002012
+a2840000
+a2970000
+a2950000
+34020069
+a2820000
+3402000a
+3403000c
+0043202a
+20850040
+a2850000
+0062202a
+20850042
+a2850000
+2402fff0
+0043202a
+20850042
+a2850000
+0062202a
+20850044
+a2850000
+2403ffff
+0043202a
+20850044
+a2850000
+0062202a
+20850046
+a2850000
+a2970000
+a2950000
+3402006a
+a2820000
+3402000a
+2844000c
+20850040
+a2850000
+28440008
+20850042
+a2850000
+a2970000
+a2950000
+3402006b
+a2820000
+3402000a
+2c44000c
+20850040
+a2850000
+2c440008
+20850042
+a2850000
+a2970000
+a2950000
+3402006c
+a2820000
+3402000a
+3403000c
+0043202a
+20850040
+a2850000
+0062202a
+20850042
+a2850000
+a2970000
+a2950000
+3402006d
+a2820000
+34030046
+34040005
+00641022
+a2820000
+a2970000
+a2950000
+3402006e
+a2820000
+34030046
+34040005
+00641022
+a2820000
+a2970000
+a2950000
+34020042
+a2820000
+34020072
+a2820000
+34020061
+a2820000
+3402006e
+a2820000
+34020063
+a2820000
+34020068
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+340a0041
+340b0042
+10000002
+a28a0000
+a2960000
+a28b0000
+a2970000
+a2950000
+34020062
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+04110005
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+34020063
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3403007b
+3404007b
+10430005
+a28a0000
+a28b0000
+10640002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020064
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340f0058
+34020064
+3c03ffff
+34631234
+3404007b
+04610005
+a28a0000
+a28b0000
+04410002
+a28c0000
+a2960000
+04010002
+00000000
+a28f0000
+a28d0000
+a2970000
+a2950000
+34020065
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c03ffff
+34631234
+04710008
+00000000
+a28a0000
+04110005
+00000000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+34020066
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3c03ffff
+34631234
+1c600005
+a28a0000
+a28b0000
+1c400002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020067
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3c03ffff
+34631234
+18400005
+a28a0000
+a28b0000
+18600002
+a28c0000
+a2960000
+18000002
+00000000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020068
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+34020064
+3c03ffff
+34631234
+34040000
+04400005
+a28a0000
+a28b0000
+04600002
+a28c0000
+a2960000
+04800002
+00000000
+a28d0000
+a28e0000
+a2970000
+a2950000
+34020069
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c03ffff
+34631234
+04100008
+00000000
+a28a0000
+04700005
+00000000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006a
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3403007b
+3404007b
+14640005
+a28a0000
+a28b0000
+14430002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+3402006b
+a2820000
+340a0041
+340b0042
+340f0058
+08000270
+a28a0000
+a28f0000
+a28b0000
+a2970000
+a2950000
+3402006c
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+0c000281
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006d
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c030000
+24630a5c
+0060f809
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006e
+a2820000
+340a0041
+340b0042
+340f0058
+3c030000
+24630a9c
+00600008
+a28a0000
+a28f0000
+a28b0000
+a2970000
+a2950000
+3402006f
+a2820000
+34020041
+00000000
+a2820000
+a2970000
+a2950000
+3402004c
+a2820000
+3402006f
+a2820000
+34020061
+a2820000
+34020064
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+34020062
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+34020063
+a2820000
+00181025
+3c030041
+34630042
+ac430010
+84440010
+a2840000
+84420012
+a2820000
+a2970000
+a2950000
+34020064
+a2820000
+00181025
+3c030041
+34630042
+ac430010
+84440010
+a2840000
+84420012
+a2820000
+a2970000
+a2950000
+34020065
+a2820000
+00181025
+24030041
+ac430010
+34030000
+8c420010
+a2820000
+a2970000
+a2950000
+34020066
+a2820000
+00181025
+24030041
+ac430010
+34030000
+88420010
+98420010
+a2820000
+a2970000
+a2950000
+34020067
+a2820000
+34020041
+a2820000
+a2970000
+a2950000
+34020068
+a2820000
+00182025
+34024142
+a4820010
+80830010
+a2830000
+80820011
+a2820000
+a2970000
+a2950000
+34020069
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+3402006a
+a2820000
+00181025
+3c034142
+34634344
+a8430010
+b8430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+3402004c
+a2820000
+3402006f
+a2820000
+34020067
+a2820000
+34020069
+a2820000
+34020063
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34020741
+340360f3
+00432024
+a2840000
+a2970000
+a2950000
+34020062
+a2820000
+34020741
+304460f3
+a2840000
+a2970000
+a2950000
+34020063
+a2820000
+3c020041
+00021c02
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+3c02f0ff
+3442f08e
+3c030f0f
+34630f30
+00432027
+a2840000
+a2970000
+a2950000
+34020065
+a2820000
+34020040
+34030001
+00432025
+a2840000
+a2970000
+a2950000
+34020066
+a2820000
+34020040
+34440001
+a2840000
+a2970000
+a2950000
+34020067
+a2820000
+3402f043
+3403f002
+00432026
+a2840000
+a2970000
+a2950000
+34020068
+a2820000
+3402f043
+3844f002
+a2840000
+a2970000
+a2950000
+08000384
+00000000
+00000000
+00000000
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/meehanNotes
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/meehanNotes
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/meehanNotes
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,36 @@
+
+Look at the sim that is up and running.
+try to figure out where the nmi / interuption is comming from? Maybe we need
+to delay the ack in the memory read?
+
+Confusing
+
+ I commented out the lui 08000 from teh asm code to make the memory
+ work
+
+ Turns out there was an interrupt from a timer in the test bench.
+ I commented out the timer :-)
+
+ Looking at the SRAV instruction. It seems to not be working.
+ i.e. shifts by wrong amount not making sense. First call
+ works with a shift of 0x10 second call with shift of 0x25 fails.
+
+ seems the ALU may be getting loaded with the wrong ops
+ op1 should be 0x19 but it is 0x41 look at signal BP_dataa_i
+
+ switched to use blockram in regfile.v and it works !!!
+
+ changed ucoredefines so that ram starts at 7ffffff
+ with a mask of the same value. This allows for
+ memory at fffffff to be mapped down
+
+
+ Summary of changes:
+
+ wrote Makefiles for Icarus Verilog compile
+ added Latency to ram model in testbench
+ removed call to $random() (would not compile)
+ removed timer interupt from testbench (test_code did not have ISR)
+ changed ucore_defines.v to match memory location from gcc
+
+
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ram.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ram.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ram.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -132,25 +132,25 @@
dmem_addr = addr_i & MASK;
ack_o = 0 ;
- if (dmem_addr<MEM_SIZE*4+START&& dmem_addr>=START)
- begin
- if(we_i)
- begin:WRITE_SECTION
- if(bwsel_i[0]) mem[dmem_addr+0] = data_i[7:0];
- if(bwsel_i[1]) mem[dmem_addr+1] = data_i[15:8];
- if(bwsel_i[2]) mem[dmem_addr+2] = data_i[23:16];
- if(bwsel_i[3]) mem[dmem_addr+3] = data_i[31:24];
- $fdisplay(fout,$time , , , "write to ram, addr =
%0h,data=%h,bwsel=%b ,ramdata =
%h.",dmem_addr,data_i,bwsel_i,{mem[dmem_addr+3],mem[dmem_addr+2],mem[dmem_addr+1],mem[dmem_addr+0]});
- end
- else begin
- data_o = 32'b0;
- if(bwsel_i[0]) data_o[7:0] = mem[dmem_addr+0];
- if(bwsel_i[1]) data_o[15:8] = mem[dmem_addr+1];
- if(bwsel_i[2]) data_o[23:16] = mem[dmem_addr+2];
- if(bwsel_i[3]) data_o[31:24] = mem[dmem_addr+3];
- $fdisplay(fout,$time , , , "Read ram, addr = %0h,data=%h,bwsel=%b
,ramdata =
%h.",dmem_addr,data_o,bwsel_i,{mem[dmem_addr+3],mem[dmem_addr+2],mem[dmem_addr+1],mem[dmem_addr+0]});
- end
- end
+ if (dmem_addr<MEM_SIZE*4+START&& dmem_addr>=START)
+ begin
+ if(we_i)
+ begin:WRITE_SECTION
+ if(bwsel_i[0]) mem[dmem_addr+0] = data_i[7:0];
+ if(bwsel_i[1]) mem[dmem_addr+1] = data_i[15:8];
+ if(bwsel_i[2]) mem[dmem_addr+2] = data_i[23:16];
+ if(bwsel_i[3]) mem[dmem_addr+3] = data_i[31:24];
+ $fdisplay(fout,$time , , , "write to ram, addr =
%0h,data=%h,bwsel=%b ,ramdata = %h. last 8 ascii
%c",dmem_addr,data_i,bwsel_i,{mem[dmem_addr+3],mem[dmem_addr+2],mem[dmem_addr+1],mem[dmem_addr+0]},mem[dmem_addr+0]);
+ end
+ else begin
+ data_o = 32'b0;
+ if(bwsel_i[0]) data_o[7:0] = mem[dmem_addr+0];
+ if(bwsel_i[1]) data_o[15:8] = mem[dmem_addr+1];
+ if(bwsel_i[2]) data_o[23:16] = mem[dmem_addr+2];
+ if(bwsel_i[3]) data_o[31:24] = mem[dmem_addr+3];
+ $fdisplay(fout,$time , , , "Read ram, addr = %0h,data=%h,bwsel=%b
,ramdata = %h. last 8 ascii
%c",dmem_addr,data_o,bwsel_i,{mem[dmem_addr+3],mem[dmem_addr+2],mem[dmem_addr+1],mem[dmem_addr+0]},mem[dmem_addr+0]);
+ end
+ end
else if(we_i && addr_i == `UART_TX_DATA)
begin
$fwrite(fuart,"%c",data_i[7:0]);
@@ -162,13 +162,14 @@
end
else begin
if(we_i )
- $fdisplay(fout,$time , , , "write to addr = %h, data=%h
.\n",addr_i,data_i);
+ $fdisplay(fout,$time , , , "write to addr = %h, data=%h . ascii %c
\n",addr_i,data_i,data_i );
else begin
$fdisplay(fout,$time , , , "read addr = %h .\n",addr_i);
data_o = 32'b0;
end
end
//# LATENCY;
+ # 11;
ack_o = 1;
end
else ack_o = 0;
@@ -228,4 +229,4 @@
else ack_o = 0;
end
*/
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/rom.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/rom.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/rom.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -99,14 +99,15 @@
inst_o = 0;
end
else begin
- //seed = 0;
- seed = $random();
+ seed = 0;
+ //seed = $random();
//$display($time, , ,"in rom ,seed =%d ",seed);
if(addr_i<MEM_SIZE*4+START&&addr_i>=START && seed%2 == 0)//not a ideal
mem
begin
ack_o = 0;
- //# LATENCY;
+// # LATENCY;
+ #11 // tjm a bit of latency
inst_o = mem[addr_i>>2];
ack_o = 1;
@@ -255,4 +256,4 @@
end
endtask
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ucore_tb.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ucore_tb.v
2007-10-26 22:10:05 UTC (rev 6708)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/ucore_tb.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -57,6 +57,7 @@
`include "ucore_defines.v"
+
module ucore_tb();
reg clk;
reg reset;
@@ -77,7 +78,9 @@
wire [31:0] imem_inst;
assign dmem_addr = dmem_we?dmem_waddr:dmem_raddr;
+
+
ucore my_ucore
(
@@ -104,12 +107,13 @@
.it_hw_i(it_hw)
);
- timer my_timer
- (
- .clk_i(clk),
- .rst_i(reset),
- .timeout_o(it_hw[0])
- );
+// timer my_timer timdebug tjm remove the hw interupt temporarily so we don't
+// have to worrry about installing an ISR
+// (
+// .clk_i(clk),
+// .rst_i(reset),
+// .timeout_o(it_hw[0])
+// );
ram my_ram
(
@@ -142,6 +146,8 @@
integer log_excute;
initial
begin
+ $dumpfile("test.vcd");
+ $dumpvars(0,my_ucore);
log_excute = $fopen("log.excute");
#2;
my_rom.fout = my_rom.fout | log_excute;
@@ -217,6 +223,8 @@
end
`endif
+
+
endmodule
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/wavefile.sav
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/wavefile.sav
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/tb/wavefile.sav
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,43 @@
+[size] 1148 700
+[pos] 123 31
+*-14.444517 77100 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
-1 -1 -1 -1 -1 -1
address@hidden
+ucore_tb.my_ucore.my_cop0.BP_reg_raddr_o[4:0]
+ucore_tb.my_ucore.my_cop0.BP_reg_rdata_i[31:0]
+ucore_tb.my_ucore.my_id.my_decoder.inst_code[31:0]
+ucore_tb.my_ucore.my_id.my_decoder.inst_func[5:0]
+ucore_tb.my_ucore.my_id.my_decoder.inst_op[5:0]
+ucore_tb.my_ucore.my_id.my_decoder.inst_regimm[4:0]
address@hidden
+ucore_tb.my_ucore.my_ex.my_alu.branch_flag
address@hidden
+ucore_tb.my_ucore.my_ex.IF_bra_addr_o[31:0]
+ucore_tb.my_ucore.my_ex.BRA_offset[31:0]
+ucore_tb.my_ucore.my_if.pc_inter[31:0]
address@hidden
+ucore_tb.my_ucore.my_if.bra_reged
address@hidden
+ucore_tb.my_ucore.my_if.bra_addr_reged[31:0]
address@hidden
+ucore_tb.my_ucore.my_if.bra_i
address@hidden
+ucore_tb.my_ucore.my_ex.op1[31:0]
address@hidden
+ucore_tb.my_ucore.my_ex.pre_bra_addr[31:0]
address@hidden
+ucore_tb.my_ucore.my_if.bra_reged
address@hidden
+ucore_tb.my_ucore.my_ex.my_alu.mem_addr[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.res_shl[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.res[31:0]
address@hidden
+ucore_tb.my_ucore.my_regfile.ram0.DIA[31:0]
address@hidden
+ucore_tb.my_ucore.my_rf.ID_imm_selb_i
+ucore_tb.my_ucore.my_rf.ID_use_regb_i
address@hidden
+ucore_tb.my_ucore.my_rf.pre_op2[31:0]
+ucore_tb.my_ucore.my_ex.RF_op2_i[31:0]
+ucore_tb.my_ucore.my_ex.my_alu.op2[31:0]
+ucore_tb.my_ucore.my_regfile.dinc_reged[31:0]
+ucore_tb.my_ucore.my_regfile.dinc[31:0]
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -255,7 +255,7 @@
//wire [31:0] PR_bra_adr; // New PC
//wire PR_clear_IF; // Clear the pipeline stage : IF
//wire PR_clear_ID; // Clear the pipeline stage : ID
-
+
pps_if my_if
(
.clk_i (clk_i),
@@ -282,7 +282,7 @@
.ID_it_ok_o (IF_it_ok), // Allow hardware interruptions
.ID_bra_target_o (IF_bra_target)
);
-
+
pps_id my_id
(
.clk_i (clk_i),
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore_defines.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore_defines.v
2007-10-26 22:10:05 UTC (rev 6708)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/src/ucore/ucore_defines.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -99,7 +99,10 @@
`define DATA_RAM_SIZE (4*1024) //4k word //256
`define DATA_RAM_ADDR_WIDTH `INST_ROM_DATA_WIDTH
`define DATA_RAM_DATA_WIDTH `INST_ROM_ADDR_WIDTH
-`define DATA_RAM_START 32'h00000000
+//tjm timdebug
+//`define DATA_RAM_START 32'h00000000
+`define DATA_RAM_START 32'h00800000 // use this one for test_code.asm
+//`define DATA_RAM_START 32'h7fffC000 // use this one for compiled c code
`define DATA_RAM_MASK 32'h7fffffff
`define DATA_RAM_LATENCY 10
Modified: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,13 +1,22 @@
-all: sort
-clean: clean_sort
+all: test_code
+ROOT = /opt/crosstool/gcc-3.4.5-glibc-2.3.6/mipsel-unknown-linux-gnu/bin
+CC = $(ROOT)/mipsel-unknown-linux-gnu-gcc
+LD = $(ROOT)/mipsel-unknown-linux-gnu-ld
+OBJDUMP = $(ROOT)/mipsel-unknown-linux-gnu-objdump
+STRIP = $(ROOT)/mipsel-unknown-linux-gnu-strip
+AS = $(ROOT)/mipsel-unknown-linux-gnu-as
+
+#all: sort
+#clean: clean_sort
+
#all: ucsys_test
#clean: clean_test
########################init file generation##############################
init.o : init.s Makefile
- mipsel-linux-as -EL -mips1 init.s -o init.o
+ $(AS) -EL -mips1 init.s -o init.o
##########################ucsys_test###################################
#note: the init.s has been included into test_code_el_ucsys.s
@@ -33,22 +42,73 @@
######################## sort test###########################
sort.o : sort.c sortlib.h Makefile
- mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sort.c
+ $(CC) -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs -Wall -I.
sort.c
sortlib.o : sortlib.c sortlib.h Makefile
- mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sortlib.c
+ $(CC) -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs -Wall -I.
sortlib.c
ld_sort: init.o sort.o sortlib.o elf32ltsmip.x
- mipsel-linux-ld -N -S -T ./elf32ltsmip.x init.o sort.o sortlib.o -o
ld_sort
- mipsel-linux-objdump -Dz ld_sort > ld_sort.s
+ $(LD) -N -S -T ./elf32ltsmip.x init.o sort.o sortlib.o -o ld_sort
+ $(OBJDUMP) -Dz ld_sort > ld_sort.s
strip_sort: ld_sort
- mipsel-linux-strip -s -R .reginfo -R .pdr -R .comment ld_sort -o
strip_sort
+ $(STRIP) -s -R .reginfo -R .pdr -R .comment ld_sort -o strip_sort
sort.s: strip_sort
- mipsel-linux-objdump -Dz strip_sort > sort.s
+ $(OBJDUMP) -Dz strip_sort > sort.s
sort: sort.s
perl tocoe.pl sort.s inst_mem data_mem
- cp inst_mem.code ../sim
- cp data_mem.data ../sim
+ cp data_mem.data ../src/ucore/tb/
+ cp inst_mem.code ../src/ucore/tb/
cp inst_mem_init.v ../src
cp data_mem_init.v ../src
clean_sort:
rm init.o sort.o sortlib.o ld_sort ld_sort.s strip_sort sort.s
+
+
+### timtest ###
+timtest.o: timtest.c
+ $(CC) -c -mips1 -Wa,-xgot -O0 -nostartfiles -nodefultlibs -Wall
timtest.c
+ld_timtest: timtest.o
+ $(LD) -N -S -T ./elf32ltsmip.x timtest.o -o ld_timtest
+# $(LD) -N -S -T ./elf32btsmip.x timtest.o -o ld_timtest
+strip_timtest: ld_timtest
+ $(STRIP) -s -R .reginfo -R .pdf -R .comment ld_timtest -o strip_timtest
+timtest.s: strip_timtest
+ $(OBJDUMP) -Dz strip_timtest > timtest.s
+timtest: timtest.s
+ perl tocoe.pl timtest.s inst_mem data_mem
+ cp data_mem.data ../src/ucore/tb/
+ cp inst_mem.code ../src/ucore/tb/
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
+### test_code ###
+test_code.o: test_code.asm
+ $(AS) -EL -mips1 test_code.asm -o test_code.o
+ld_test_code: test_code.o
+ $(LD) -N -S -T ./elf32ltsmip.x test_code.o -o ld_test_code
+strip_test_code: ld_test_code
+ $(STRIP) -s -R .reginfo -R .pdf -R .comment ld_test_code -o
strip_test_code
+test_code.s: strip_test_code
+ $(OBJDUMP) -Dz strip_test_code > test_code.s
+test_code: test_code.s
+ perl tocoe.pl test_code.s inst_mem data_mem
+ cp data_mem.data ../src/ucore/tb/
+ cp inst_mem.code ../src/ucore/tb/
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
+### test_code_sw ###
+test_code_sw.o: test_code_sw.asm
+ $(AS) -EL -mips1 test_code_sw.asm -o test_code_sw.o
+ld_test_code_sw: test_code_sw.o
+ $(LD) -N -S -T ./elf32ltsmip.x test_code_sw.o -o ld_test_code_sw
+strip_test_code_sw: ld_test_code_sw
+ $(STRIP) -s -R .reginfo -R .pdf -R .comment ld_test_code_sw -o
strip_test_code_sw
+test_code_sw.s: strip_test_code_sw
+ $(OBJDUMP) -Dz strip_test_code_sw > test_code_sw.s
+test_code_sw: test_code_sw.s
+ perl tocoe.pl test_code_sw.s inst_mem data_mem
+ cp data_mem.data ../src/ucore/tb/
+ cp inst_mem.code ../src/ucore/tb/
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile.orig
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile.orig
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/Makefile.orig
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,77 @@
+
+all: timtest
+#all: sort
+#clean: clean_sort
+
+#all: ucsys_test
+#clean: clean_test
+
+########################init file generation##############################
+init.o : init.s Makefile
+ mipsel-linux-as -EL -mips1 init.s -o init.o
+
+##########################ucsys_test###################################
+#note: the init.s has been included into test_code_el_ucsys.s
+ucsys_test.o: test_code_el_ucsys.s init.s Makefile
+ mipsel-linux-as -EL -mips1 test_code_el_ucsys.s -o ucsys_test.o
+ld_test: ucsys_test.o elf32ltsmip.x
+ mipsel-linux-ld -N -S -T ./elf32ltsmip.x ucsys_test.o -o ld_test
+ mipsel-linux-objdump -Dz ld_test > ld_test.s
+strip_test: ld_test
+ mipsel-linux-strip -s -R .reginfo -R .pdr -R .comment ld_test -o
strip_test
+test.s: strip_test
+ mipsel-linux-objdump -Dz strip_test > test.s
+
+ucsys_test: test.s
+ perl tocoe.pl test.s inst_mem data_mem
+ cp inst_mem.code ../sim
+ cp data_mem.data ../sim
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
+clean_test:
+ rm init.o ucsys_test.o ld_test ld_test.s strip_test test.s
+
+######################## sort test###########################
+sort.o : sort.c sortlib.h Makefile
+ mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sort.c
+sortlib.o : sortlib.c sortlib.h Makefile
+ mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sortlib.c
+ld_sort: init.o sort.o sortlib.o elf32ltsmip.x
+ mipsel-linux-ld -N -S -T ./elf32ltsmip.x init.o sort.o sortlib.o -o
ld_sort
+ mipsel-linux-objdump -Dz ld_sort > ld_sort.s
+strip_sort: ld_sort
+ mipsel-linux-strip -s -R .reginfo -R .pdr -R .comment ld_sort -o
strip_sort
+sort.s: strip_sort
+ mipsel-linux-objdump -Dz strip_sort > sort.s
+sort: sort.s
+ perl tocoe.pl sort.s inst_mem data_mem
+ cp inst_mem.code ../sim
+ cp data_mem.data ../sim
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
+clean_sort:
+ rm init.o sort.o sortlib.o ld_sort ld_sort.s strip_sort sort.s
+
+######################## timtest###########################
+timtest.o : timtest.c sortlib.h Makefile
+ mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sort.c
+sortlib.o : sortlib.c sortlib.h Makefile
+ mipsel-linux-gcc -c -mips1 -Wa,-xgot -O2 -nostartfiles -nodefaultlibs
-Wall -I. sortlib.c
+ld_sort: init.o sort.o sortlib.o elf32ltsmip.x
+ mipsel-linux-ld -N -S -T ./elf32ltsmip.x init.o sort.o sortlib.o -o
ld_sort
+ mipsel-linux-objdump -Dz ld_sort > ld_sort.s
+strip_sort: ld_sort
+ mipsel-linux-strip -s -R .reginfo -R .pdr -R .comment ld_sort -o
strip_sort
+sort.s: strip_sort
+ mipsel-linux-objdump -Dz strip_sort > sort.s
+sort: sort.s
+ perl tocoe.pl sort.s inst_mem data_mem
+ cp inst_mem.code ../sim
+ cp data_mem.data ../sim
+ cp inst_mem_init.v ../src
+ cp data_mem_init.v ../src
+
+clean_sort:
+ rm init.o sort.o sortlib.o ld_sort ld_sort.s strip_sort sort.s
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem.data
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem.data
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem.data
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,15 +0,0 @@
-00000000
-80000000
-08000000
-00000000
-00000000
-00000000
-00000000
-000003c4
-00000310
-00000284
-0000035c
-00005b61
-00003d5d
-0000000a
-000a0a0a
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem_init.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem_init.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/data_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,22 +1,7 @@
-`ifndef __DATA_INIT__
-`define __DATA_INIT__
-
-`define INIT_DATA_MEM \
-defparam bank0.INIT_00 = 256'h9400000 ;\
-defparam bank1.INIT_00 = 256'hb344000 ;\
-defparam bank2.INIT_00 = 256'h1910000 ;\
-defparam bank3.INIT_00 = 256'h158c000 ;\
-defparam bank4.INIT_00 = 256'h1fbc000 ;\
-defparam bank5.INIT_00 = 256'h3800000 ;\
-defparam bank6.INIT_00 = 256'h3400000 ;\
-defparam bank7.INIT_00 = 256'h0400000 ;\
-defparam bank8.INIT_00 = 256'h0000000 ;\
-defparam bank9.INIT_00 = 256'h0000000 ;\
-defparam banka.INIT_00 = 256'h0000000 ;\
-defparam bankb.INIT_00 = 256'h0000000 ;\
-defparam bankc.INIT_00 = 256'h0000000 ;\
-defparam bankd.INIT_00 = 256'h0000020 ;\
-defparam banke.INIT_00 = 256'h0000000 ;\
-defparam bankf.INIT_00 = 256'h0000008
-
-`endif
+`ifndef __DATA_INIT__
+`define __DATA_INIT__
+
+`define INIT_DATA_MEM defparam bank0.bank0.INIT_00 = 256'h0
+
+
+`endif
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/init.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/init.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.asm
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.asm
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.asm
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,284 +1,904 @@
-0: lui t9,0x0
-4: addiu t9,t9,80
-8: lui sp,0x800
-c: jalr t9
-10: ori sp,sp,0x8000
-14: nop
-18: j 0x18
-1c: nop
-20: nop
-24: addiu sp,sp,-4
-28: sw t0,0(sp)
-2c: li t0,15
-30: nop
-34: mtc0 t0,$17
-38: nop
-3c: lw t0,0(sp)
-40: addiu sp,sp,4
-44: c0 0x18
-48: nop
-4c: nop
-50: lui gp,0x800
-54: addiu gp,gp,-80
-58: addu gp,gp,t9
-5c: addiu sp,sp,-88
-60: sw ra,80(sp)
-64: sw s7,76(sp)
-68: sw s6,72(sp)
-6c: sw s5,68(sp)
-70: sw s4,64(sp)
-74: sw s3,60(sp)
-78: sw s2,56(sp)
-7c: sw s1,52(sp)
-80: sw s0,48(sp)
-84: sw gp,16(sp)
-88: li v0,240
-8c: li v1,241
-90: sh v0,24(sp)
-94: sh v1,26(sp)
-98: li v0,242
-9c: li v1,243
-a0: sh v0,28(sp)
-a4: sh v1,30(sp)
-a8: li v0,244
-ac: li v1,245
-b0: sh v0,32(sp)
-b4: sh v1,34(sp)
-b8: li v0,246
-bc: li v1,247
-c0: addiu s7,sp,24
-c4: sh v0,36(sp)
-c8: sh v1,38(sp)
-cc: li v0,248
-d0: li v1,249
-d4: lw s5,8(gp)
-d8: lw s4,8(gp)
-dc: lw s3,8(gp)
-e0: sh v0,40(sp)
-e4: sh v1,42(sp)
-e8: move s0,zero
-ec: move s1,s7
-f0: li s2,10
-f4: lw t9,32(gp)
-f8: nop
-fc: jalr t9
-100: addiu a0,s5,44
-104: lw gp,16(sp)
-108: move a0,s0
-10c: lw t9,28(gp)
-110: nop
-114: jalr t9
-118: addiu s0,s0,1
-11c: lw gp,16(sp)
-120: nop
-124: lw t9,32(gp)
-128: nop
-12c: jalr t9
-130: addiu a0,s4,48
-134: lw gp,16(sp)
-138: lh a0,0(s1)
-13c: lw t9,40(gp)
-140: nop
-144: jalr t9
-148: li a1,16
-14c: lw gp,16(sp)
-150: addiu a0,s3,52
-154: lw t9,32(gp)
-158: nop
-15c: jalr t9
-160: addiu s1,s1,2
-164: lw gp,16(sp)
-168: bne s0,s2,0xf4
-16c: nop
-170: lw s6,8(gp)
-174: lw t9,32(gp)
-178: nop
-17c: jalr t9
-180: addiu a0,s6,56
-184: lw gp,16(sp)
-188: addiu a0,sp,24
-18c: lw t9,36(gp)
-190: nop
-194: jalr t9
-198: li a1,10
-19c: lw gp,16(sp)
-1a0: move s1,s7
-1a4: move s0,zero
-1a8: li s2,10
-1ac: lw t9,32(gp)
-1b0: nop
-1b4: jalr t9
-1b8: addiu a0,s5,44
-1bc: lw gp,16(sp)
-1c0: move a0,s0
-1c4: lw t9,28(gp)
-1c8: nop
-1cc: jalr t9
-1d0: addiu s0,s0,1
-1d4: lw gp,16(sp)
-1d8: nop
-1dc: lw t9,32(gp)
-1e0: nop
-1e4: jalr t9
-1e8: addiu a0,s4,48
-1ec: lw gp,16(sp)
-1f0: lh a0,0(s1)
-1f4: lw t9,40(gp)
-1f8: nop
-1fc: jalr t9
-200: li a1,16
-204: lw gp,16(sp)
-208: addiu a0,s3,52
-20c: lw t9,32(gp)
-210: nop
-214: jalr t9
-218: addiu s1,s1,2
-21c: lw gp,16(sp)
-220: bne s0,s2,0x1ac
-224: nop
-228: lw t9,32(gp)
-22c: nop
-230: jalr t9
-234: addiu a0,s6,56
-238: lh v0,24(sp)
-23c: lw gp,16(sp)
-240: lw ra,80(sp)
-244: lw s7,76(sp)
-248: lw s6,72(sp)
-24c: lw s5,68(sp)
-250: lw s4,64(sp)
-254: lw s3,60(sp)
-258: lw s2,56(sp)
-25c: lw s1,52(sp)
-260: lw s0,48(sp)
-264: jr ra
-268: addiu sp,sp,88
-26c: nop
-270: lw v0,0(a0)
-274: jr ra
-278: nop
-27c: jr ra
-280: sw a0,0(a1)
-284: blez a1,0x2e0
-288: addiu a0,a0,2
-28c: move v0,zero
-290: addiu t2,v0,1
-294: slt v0,t2,a1
-298: beqz v0,0x2d4
-29c: nop
-2a0: move v1,a0
-2a4: move t0,zero
-2a8: subu t1,a1,t2
-2ac: lh a2,0(v1)
-2b0: lh a3,-2(a0)
-2b4: nop
-2b8: slt v0,a3,a2
-2bc: beqz v0,0x2cc
-2c0: addiu t0,t0,1
-2c4: sh a2,-2(a0)
-2c8: sh a3,0(v1)
-2cc: bne t0,t1,0x2ac
-2d0: addiu v1,v1,2
-2d4: addiu a0,a0,2
-2d8: bne a1,t2,0x290
-2dc: move v0,t2
-2e0: jr ra
-2e4: nop
-2e8: sll a0,a0,0x18
-2ec: sra a0,a0,0x18
-2f0: li v1,4
-2f4: lw v0,0(v1)
-2f8: nop
-2fc: bnez v0,0x2f4
-300: li v0,12
-304: sw a0,0(v0)
-308: jr ra
-30c: nop
-310: lb v0,0(a0)
-314: nop
-318: beqz v0,0x354
-31c: li v1,4
-320: li a2,12
-324: sll a1,v0,0x18
-328: sra a1,a1,0x18
-32c: lw v0,0(v1)
-330: nop
-334: bnez v0,0x32c
-338: nop
-33c: sw a1,0(a2)
-340: addiu a0,a0,1
-344: lb v0,0(a0)
-348: nop
-34c: bnez v0,0x328
-350: sll a1,v0,0x18
-354: jr ra
-358: nop
-35c: addiu a1,a1,-4
-360: bltz a1,0x3ac
-364: li a3,12
-368: srav v0,a0,a1
-36c: andi v0,v0,0xf
-370: slti v1,v0,10
-374: beqz v1,0x3b4
-378: nop
-37c: addiu v0,v0,48
-380: sll v1,v0,0x18
-384: sra v1,v1,0x18
-388: li a2,4
-38c: lw v0,0(a2)
-390: nop
-394: bnez v0,0x38c
-398: nop
-39c: sw v1,0(a3)
-3a0: addiu a1,a1,-4
-3a4: bgez a1,0x36c
-3a8: srav v0,a0,a1
-3ac: jr ra
-3b0: nop
-3b4: addiu v0,v0,87
-3b8: sll v0,v0,0x18
-3bc: b 0x380
-3c0: sra v0,v0,0x18
-3c4: bnez a0,0x414
-3c8: lui v0,0x6666
-3cc: li v1,4
-3d0: lw v0,0(v1)
-3d4: nop
-3d8: bnez v0,0x3d0
-3dc: li v0,12
-3e0: li v1,48
-3e4: sw v1,0(v0)
-3e8: jr ra
-3ec: nop
-3f0: sw a2,0(v1)
-3f4: lui v0,0x6666
-3f8: ori v0,v0,0x6667
-3fc: mult a0,v0
-400: mfhi v0
-404: sra v0,v0,0x2
-408: subu a0,v0,a3
-40c: beqz a0,0x3e8
-410: lui v0,0x6666
-414: ori v0,v0,0x6667
-418: mult a0,v0
-41c: sra a3,a0,0x1f
-420: li a1,4
-424: mfhi v0
-428: sra v0,v0,0x2
-42c: subu v0,v0,a3
-430: sll v1,v0,0x3
-434: sll v0,v0,0x1
-438: addu v0,v0,v1
-43c: subu v0,a0,v0
-440: addiu v0,v0,48
-444: sll a2,v0,0x18
-448: sra a2,a2,0x18
-44c: lw v0,0(a1)
-450: nop
-454: bnez v0,0x44c
-458: li v1,12
-45c: b 0x3f0
-460: nop
-464: nop
-468: nop
-46c: nop
+0: lui gp,0x0
+4: ori gp,gp,0x0
+8: lui a0,0x0
+c: ori a0,a0,0x0
+10: lui a1,0x0
+14: ori a1,a1,0x0
+18: lui sp,0x80
+1c: ori sp,sp,0x0
+20: lui s4,0x80
+24: ori s4,s4,0x10
+28: li s5,0xa
+2c: li s6,0x58
+30: li s7,0xd
+34: lui t8,0x80
+38: ori t8,t8,0x4
+3c: li v0,0x4d
+40: sb v0,0(s4)
+44: li v0,0x6f
+48: sb v0,0(s4)
+4c: li v0,0x76
+50: sb v0,0(s4)
+54: li v0,0x65
+58: sb v0,0(s4)
+5c: sb s7,0(s4)
+60: sb s5,0(s4)
+64: li v0,0x61
+68: sb v0,0(s4)
+6c: li v0,0x41
+70: mthi v0
+74: mfhi v1
+78: sb v1,0(s4)
+7c: sb s7,0(s4)
+80: sb s5,0(s4)
+84: li v0,0x62
+88: sb v0,0(s4)
+8c: li v0,0x41
+90: mtlo v0
+94: mflo v1
+98: sb v1,0(s4)
+9c: sb s7,0(s4)
+a0: sb s5,0(s4)
+a4: li v0,0x63
+a8: sb v0,0(s4)
+ac: li v0,0x41
+b0: mthi v0
+b4: mfhi v1
+b8: sb v1,0(s4)
+bc: sb s7,0(s4)
+c0: sb s5,0(s4)
+c4: li v0,0x64
+c8: sb v0,0(s4)
+cc: li v0,0x41
+d0: mtlo v0
+d4: mflo v1
+d8: sb v1,0(s4)
+dc: sb s7,0(s4)
+e0: sb s5,0(s4)
+e4: li v0,0x53
+e8: sb v0,0(s4)
+ec: li v0,0x68
+f0: sb v0,0(s4)
+f4: li v0,0x69
+f8: sb v0,0(s4)
+fc: li v0,0x66
+100: sb v0,0(s4)
+104: li v0,0x74
+108: sb v0,0(s4)
+10c: sb s7,0(s4)
+110: sb s5,0(s4)
+114: li v0,0x61
+118: sb v0,0(s4)
+11c: lui v0,0x4041
+120: ori v0,v0,0x4243
+124: sll v1,v0,0x8
+128: srl v1,v1,0x18
+12c: sb v1,0(s4)
+130: sb s7,0(s4)
+134: sb s5,0(s4)
+138: li v0,0x62
+13c: sb v0,0(s4)
+140: lui v0,0x4041
+144: ori v0,v0,0x4243
+148: li v1,0x8
+14c: sllv v1,v0,v1
+150: srl v1,v1,0x18
+154: sb v1,0(s4)
+158: sb s7,0(s4)
+15c: sb s5,0(s4)
+160: li v0,0x63
+164: sb v0,0(s4)
+168: lui v0,0x4041
+16c: ori v0,v0,0x4243
+170: sra v1,v0,0x10
+174: sb v1,0(s4)
+178: lui v0,0x8400
+17c: sra v1,v0,0x19
+180: addi v1,v1,-128
+184: sb v1,0(s4)
+188: sb s7,0(s4)
+18c: sb s5,0(s4)
+190: li v0,0x64
+194: sb v0,0(s4)
+198: lui v0,0x4041
+19c: ori v0,v0,0x4243
+1a0: li v1,0x10
+1a4: srav v1,v0,v1
+1a8: sb v1,0(s4)
+1ac: li v1,0x19
+1b0: lui v0,0x8400
+1b4: srav v1,v0,v1
+1b8: addi v1,v1,-128
+1bc: sb v1,0(s4)
+1c0: sb s7,0(s4)
+1c4: sb s5,0(s4)
+1c8: li v0,0x65
+1cc: sb v0,0(s4)
+1d0: lui v0,0x4041
+1d4: ori v0,v0,0x4243
+1d8: srl v1,v0,0x10
+1dc: sb v1,0(s4)
+1e0: lui v0,0x8400
+1e4: srl v1,v0,0x19
+1e8: sb v1,0(s4)
+1ec: sb s7,0(s4)
+1f0: sb s5,0(s4)
+1f4: li v0,0x66
+1f8: sb v0,0(s4)
+1fc: lui v0,0x4041
+200: ori v0,v0,0x4243
+204: li v1,0x10
+208: srlv a0,v0,v1
+20c: sb a0,0(s4)
+210: li v1,0x19
+214: lui v0,0x8400
+218: srlv v1,v0,v1
+21c: sb v1,0(s4)
+220: sb s7,0(s4)
+224: sb s5,0(s4)
+228: li v0,0x44
+22c: sb v0,0(s4)
+230: li v0,0x6f
+234: sb v0,0(s4)
+238: li v0,0x6e
+23c: sb v0,0(s4)
+240: li v0,0x65
+244: sb v0,0(s4)
+248: sb s7,0(s4)
+24c: sb s5,0(s4)
+250: li v0,0x41
+254: sb v0,0(s4)
+258: li v0,0x72
+25c: sb v0,0(s4)
+260: li v0,0x69
+264: sb v0,0(s4)
+268: li v0,0x74
+26c: sb v0,0(s4)
+270: li v0,0x68
+274: sb v0,0(s4)
+278: sb s7,0(s4)
+27c: sb s5,0(s4)
+280: li v0,0x61
+284: sb v0,0(s4)
+288: li v1,0x5
+28c: li a0,0x3c
+290: add v0,v1,a0
+294: sb v0,0(s4)
+298: sb s7,0(s4)
+29c: sb s5,0(s4)
+2a0: li v0,0x62
+2a4: sb v0,0(s4)
+2a8: li a0,0x3c
+2ac: addi v0,a0,5
+2b0: sb v0,0(s4)
+2b4: sb s7,0(s4)
+2b8: sb s5,0(s4)
+2bc: li v0,0x63
+2c0: sb v0,0(s4)
+2c4: li a0,0x32
+2c8: addiu a1,a0,15
+2cc: sb a1,0(s4)
+2d0: sb s7,0(s4)
+2d4: sb s5,0(s4)
+2d8: li v0,0x64
+2dc: sb v0,0(s4)
+2e0: li v1,0x5
+2e4: li a0,0x3c
+2e8: add v0,v1,a0
+2ec: sb v0,0(s4)
+2f0: sb s7,0(s4)
+2f4: sb s5,0(s4)
+2f8: li v0,0x65
+2fc: sb v0,0(s4)
+300: li v0,0x1dde
+304: li v1,0x75
+308: bnez v1,0x314
+30c: div zero,v0,v1
+310: break 0x7
+314: li at,-1
+318: bne v1,at,0x32c
+31c: lui at,0x8000
+320: bne v0,at,0x32c
+324: nop
+328: break 0x6
+32c: mflo v0
+330: nop
+334: mflo a0
+338: sb a0,0(s4)
+33c: mfhi a0
+340: addi a0,a0,25
+344: sb a0,0(s4)
+348: li v0,-1273
+34c: li v1,0x13
+350: bnez v1,0x35c
+354: div zero,v0,v1
+358: break 0x7
+35c: li at,-1
+360: bne v1,at,0x374
+364: lui at,0x8000
+368: bne v0,at,0x374
+36c: nop
+370: break 0x6
+374: mflo v0
+378: nop
+37c: mflo a0
+380: neg a0,a0
+384: sb a0,0(s4)
+388: li v0,0x61c
+38c: li v1,-23
+390: bnez v1,0x39c
+394: div zero,v0,v1
+398: break 0x7
+39c: li at,-1
+3a0: bne v1,at,0x3b4
+3a4: lui at,0x8000
+3a8: bne v0,at,0x3b4
+3ac: nop
+3b0: break 0x6
+3b4: mflo v0
+3b8: nop
+3bc: mflo a0
+3c0: neg a0,a0
+3c4: sb a0,0(s4)
+3c8: li v0,-897
+3cc: li v1,-13
+3d0: bnez v1,0x3dc
+3d4: div zero,v0,v1
+3d8: break 0x7
+3dc: li at,-1
+3e0: bne v1,at,0x3f4
+3e4: lui at,0x8000
+3e8: bne v0,at,0x3f4
+3ec: nop
+3f0: break 0x6
+3f4: mflo v0
+3f8: mflo a0
+3fc: sb a0,0(s4)
+400: sb s7,0(s4)
+404: sb s5,0(s4)
+408: li v0,0x66
+40c: sb v0,0(s4)
+410: li v0,0x34d
+414: li v1,0xd
+418: bnez v1,0x424
+41c: divu zero,v0,v1
+420: break 0x7
+424: mflo v0
+428: nop
+42c: mflo a0
+430: sb a0,0(s4)
+434: sb s7,0(s4)
+438: sb s5,0(s4)
+43c: li v0,0x67
+440: sb v0,0(s4)
+444: li v0,0x5
+448: li v1,0xd
+44c: mult v0,v1
+450: nop
+454: mflo a0
+458: sb a0,0(s4)
+45c: li v0,-5
+460: li v1,0xd
+464: mult v0,v1
+468: mfhi a1
+46c: mflo a0
+470: neg a0,a0
+474: addu a0,a0,a1
+478: addi a0,a0,2
+47c: sb a0,0(s4)
+480: li v0,0x5
+484: li v1,-13
+488: mult v0,v1
+48c: mfhi a1
+490: mflo a0
+494: neg a0,a0
+498: addu a0,a0,a1
+49c: addi a0,a0,3
+4a0: sb a0,0(s4)
+4a4: li v0,-5
+4a8: li v1,-13
+4ac: mult v0,v1
+4b0: mfhi a1
+4b4: mflo a0
+4b8: addu a0,a0,a1
+4bc: addi a0,a0,3
+4c0: sb a0,0(s4)
+4c4: lui a0,0xfe98
+4c8: ori a0,a0,0x62e5
+4cc: lui a1,0x6
+4d0: ori a1,a1,0x8db8
+4d4: mult a0,a1
+4d8: mfhi a2
+4dc: addiu a3,a2,2426
+4e0: sb a3,0(s4)
+4e4: sb s7,0(s4)
+4e8: sb s5,0(s4)
+4ec: li v0,0x68
+4f0: sb v0,0(s4)
+4f4: li v0,0x5
+4f8: li v1,0xd
+4fc: multu v0,v1
+500: nop
+504: mflo a0
+508: sb a0,0(s4)
+50c: sb s7,0(s4)
+510: sb s5,0(s4)
+514: li v0,0x69
+518: sb v0,0(s4)
+51c: li v0,0xa
+520: li v1,0xc
+524: slt a0,v0,v1
+528: addi a1,a0,64
+52c: sb a1,0(s4)
+530: slt a0,v1,v0
+534: addi a1,a0,66
+538: sb a1,0(s4)
+53c: li v0,-16
+540: slt a0,v0,v1
+544: addi a1,a0,66
+548: sb a1,0(s4)
+54c: slt a0,v1,v0
+550: addi a1,a0,68
+554: sb a1,0(s4)
+558: li v1,-1
+55c: slt a0,v0,v1
+560: addi a1,a0,68
+564: sb a1,0(s4)
+568: slt a0,v1,v0
+56c: addi a1,a0,70
+570: sb a1,0(s4)
+574: sb s7,0(s4)
+578: sb s5,0(s4)
+57c: li v0,0x6a
+580: sb v0,0(s4)
+584: li v0,0xa
+588: slti a0,v0,12
+58c: addi a1,a0,64
+590: sb a1,0(s4)
+594: slti a0,v0,8
+598: addi a1,a0,66
+59c: sb a1,0(s4)
+5a0: sb s7,0(s4)
+5a4: sb s5,0(s4)
+5a8: li v0,0x6b
+5ac: sb v0,0(s4)
+5b0: li v0,0xa
+5b4: sltiu a0,v0,12
+5b8: addi a1,a0,64
+5bc: sb a1,0(s4)
+5c0: sltiu a0,v0,8
+5c4: addi a1,a0,66
+5c8: sb a1,0(s4)
+5cc: sb s7,0(s4)
+5d0: sb s5,0(s4)
+5d4: li v0,0x6c
+5d8: sb v0,0(s4)
+5dc: li v0,0xa
+5e0: li v1,0xc
+5e4: slt a0,v0,v1
+5e8: addi a1,a0,64
+5ec: sb a1,0(s4)
+5f0: slt a0,v1,v0
+5f4: addi a1,a0,66
+5f8: sb a1,0(s4)
+5fc: sb s7,0(s4)
+600: sb s5,0(s4)
+604: li v0,0x6d
+608: sb v0,0(s4)
+60c: li v1,0x46
+610: li a0,0x5
+614: sub v0,v1,a0
+618: sb v0,0(s4)
+61c: sb s7,0(s4)
+620: sb s5,0(s4)
+624: li v0,0x6e
+628: sb v0,0(s4)
+62c: li v1,0x46
+630: li a0,0x5
+634: sub v0,v1,a0
+638: sb v0,0(s4)
+63c: sb s7,0(s4)
+640: sb s5,0(s4)
+644: li v0,0x42
+648: sb v0,0(s4)
+64c: li v0,0x72
+650: sb v0,0(s4)
+654: li v0,0x61
+658: sb v0,0(s4)
+65c: li v0,0x6e
+660: sb v0,0(s4)
+664: li v0,0x63
+668: sb v0,0(s4)
+66c: li v0,0x68
+670: sb v0,0(s4)
+674: sb s7,0(s4)
+678: sb s5,0(s4)
+67c: li v0,0x61
+680: sb v0,0(s4)
+684: li t2,0x41
+688: li t3,0x42
+68c: b 0x698
+690: sb t2,0(s4)
+694: sb s6,0(s4)
+698: sb t3,0(s4)
+69c: sb s7,0(s4)
+6a0: sb s5,0(s4)
+6a4: li v0,0x62
+6a8: sb v0,0(s4)
+6ac: li t2,0x41
+6b0: li t3,0x42
+6b4: li t4,0x43
+6b8: li t5,0x44
+6bc: li t6,0x45
+6c0: li t7,0x58
+6c4: bal 0x6dc
+6c8: sb t2,0(s4)
+6cc: sb t5,0(s4)
+6d0: b 0x6ec
+6d4: sb t6,0(s4)
+6d8: sb t7,0(s4)
+6dc: sb t3,0(s4)
+6e0: jr ra
+6e4: sb t4,0(s4)
+6e8: sb s6,0(s4)
+6ec: sb s7,0(s4)
+6f0: sb s5,0(s4)
+6f4: li v0,0x63
+6f8: sb v0,0(s4)
+6fc: li t2,0x41
+700: li t3,0x42
+704: li t4,0x43
+708: li t5,0x44
+70c: li v0,0x64
+710: li v1,0x7b
+714: li a0,0x7b
+718: beq v0,v1,0x730
+71c: sb t2,0(s4)
+720: sb t3,0(s4)
+724: beq v1,a0,0x730
+728: sb t4,0(s4)
+72c: sb s6,0(s4)
+730: sb t5,0(s4)
+734: sb s7,0(s4)
+738: sb s5,0(s4)
+73c: li v0,0x64
+740: sb v0,0(s4)
+744: li t2,0x41
+748: li t3,0x42
+74c: li t4,0x43
+750: li t5,0x44
+754: li t7,0x58
+758: li v0,0x64
+75c: lui v1,0xffff
+760: ori v1,v1,0x1234
+764: li a0,0x7b
+768: bgez v1,0x780
+76c: sb t2,0(s4)
+770: sb t3,0(s4)
+774: bgez v0,0x780
+778: sb t4,0(s4)
+77c: sb s6,0(s4)
+780: b 0x78c
+784: nop
+788: sb t7,0(s4)
+78c: sb t5,0(s4)
+790: sb s7,0(s4)
+794: sb s5,0(s4)
+798: li v0,0x65
+79c: sb v0,0(s4)
+7a0: li t2,0x41
+7a4: li t3,0x42
+7a8: li t4,0x43
+7ac: li t5,0x44
+7b0: li t6,0x45
+7b4: li t7,0x58
+7b8: lui v1,0xffff
+7bc: ori v1,v1,0x1234
+7c0: bgezal v1,0x7e4
+7c4: nop
+7c8: sb t2,0(s4)
+7cc: bal 0x7e4
+7d0: nop
+7d4: sb t5,0(s4)
+7d8: b 0x7f4
+7dc: sb t6,0(s4)
+7e0: sb t7,0(s4)
+7e4: sb t3,0(s4)
+7e8: jr ra
+7ec: sb t4,0(s4)
+7f0: sb s6,0(s4)
+7f4: sb s7,0(s4)
+7f8: sb s5,0(s4)
+7fc: li v0,0x66
+800: sb v0,0(s4)
+804: li t2,0x41
+808: li t3,0x42
+80c: li t4,0x43
+810: li t5,0x44
+814: li v0,0x64
+818: lui v1,0xffff
+81c: ori v1,v1,0x1234
+820: bgtz v1,0x838
+824: sb t2,0(s4)
+828: sb t3,0(s4)
+82c: bgtz v0,0x838
+830: sb t4,0(s4)
+834: sb s6,0(s4)
+838: sb t5,0(s4)
+83c: sb s7,0(s4)
+840: sb s5,0(s4)
+844: li v0,0x67
+848: sb v0,0(s4)
+84c: li t2,0x41
+850: li t3,0x42
+854: li t4,0x43
+858: li t5,0x44
+85c: li v0,0x64
+860: lui v1,0xffff
+864: ori v1,v1,0x1234
+868: blez v0,0x880
+86c: sb t2,0(s4)
+870: sb t3,0(s4)
+874: blez v1,0x880
+878: sb t4,0(s4)
+87c: sb s6,0(s4)
+880: blez zero,0x88c
+884: nop
+888: sb s6,0(s4)
+88c: sb t5,0(s4)
+890: sb s7,0(s4)
+894: sb s5,0(s4)
+898: li v0,0x68
+89c: sb v0,0(s4)
+8a0: li t2,0x41
+8a4: li t3,0x42
+8a8: li t4,0x43
+8ac: li t5,0x44
+8b0: li t6,0x45
+8b4: li v0,0x64
+8b8: lui v1,0xffff
+8bc: ori v1,v1,0x1234
+8c0: li a0,0x0
+8c4: bltz v0,0x8dc
+8c8: sb t2,0(s4)
+8cc: sb t3,0(s4)
+8d0: bltz v1,0x8dc
+8d4: sb t4,0(s4)
+8d8: sb s6,0(s4)
+8dc: bltz a0,0x8e8
+8e0: nop
+8e4: sb t5,0(s4)
+8e8: sb t6,0(s4)
+8ec: sb s7,0(s4)
+8f0: sb s5,0(s4)
+8f4: li v0,0x69
+8f8: sb v0,0(s4)
+8fc: li t2,0x41
+900: li t3,0x42
+904: li t4,0x43
+908: li t5,0x44
+90c: li t6,0x45
+910: li t7,0x58
+914: lui v1,0xffff
+918: ori v1,v1,0x1234
+91c: bltzal zero,0x940
+920: nop
+924: sb t2,0(s4)
+928: bltzal v1,0x940
+92c: nop
+930: sb t5,0(s4)
+934: b 0x950
+938: sb t6,0(s4)
+93c: sb t7,0(s4)
+940: sb t3,0(s4)
+944: jr ra
+948: sb t4,0(s4)
+94c: sb s6,0(s4)
+950: sb s7,0(s4)
+954: sb s5,0(s4)
+958: li v0,0x6a
+95c: sb v0,0(s4)
+960: li t2,0x41
+964: li t3,0x42
+968: li t4,0x43
+96c: li t5,0x44
+970: li v0,0x64
+974: li v1,0x7b
+978: li a0,0x7b
+97c: bne v1,a0,0x994
+980: sb t2,0(s4)
+984: sb t3,0(s4)
+988: bne v0,v1,0x994
+98c: sb t4,0(s4)
+990: sb s6,0(s4)
+994: sb t5,0(s4)
+998: sb s7,0(s4)
+99c: sb s5,0(s4)
+9a0: li v0,0x6b
+9a4: sb v0,0(s4)
+9a8: li t2,0x41
+9ac: li t3,0x42
+9b0: li t7,0x58
+9b4: j 0x9c0
+9b8: sb t2,0(s4)
+9bc: sb t7,0(s4)
+9c0: sb t3,0(s4)
+9c4: sb s7,0(s4)
+9c8: sb s5,0(s4)
+9cc: li v0,0x6c
+9d0: sb v0,0(s4)
+9d4: li t2,0x41
+9d8: li t3,0x42
+9dc: li t4,0x43
+9e0: li t5,0x44
+9e4: li t6,0x45
+9e8: li t7,0x58
+9ec: jal 0xa04
+9f0: sb t2,0(s4)
+9f4: sb t5,0(s4)
+9f8: b 0xa14
+9fc: sb t6,0(s4)
+a00: sb t7,0(s4)
+a04: sb t3,0(s4)
+a08: jr ra
+a0c: sb t4,0(s4)
+a10: sb s6,0(s4)
+a14: sb s7,0(s4)
+a18: sb s5,0(s4)
+a1c: li v0,0x6d
+a20: sb v0,0(s4)
+a24: li t2,0x41
+a28: li t3,0x42
+a2c: li t4,0x43
+a30: li t5,0x44
+a34: li t6,0x45
+a38: li t7,0x58
+a3c: lui v1,0x0
+a40: addiu v1,v1,2652
+a44: jalr v1
+a48: sb t2,0(s4)
+a4c: sb t5,0(s4)
+a50: b 0xa6c
+a54: sb t6,0(s4)
+a58: sb t7,0(s4)
+a5c: sb t3,0(s4)
+a60: jr ra
+a64: sb t4,0(s4)
+a68: sb s6,0(s4)
+a6c: sb s7,0(s4)
+a70: sb s5,0(s4)
+a74: li v0,0x6e
+a78: sb v0,0(s4)
+a7c: li t2,0x41
+a80: li t3,0x42
+a84: li t7,0x58
+a88: lui v1,0x0
+a8c: addiu v1,v1,2716
+a90: jr v1
+a94: sb t2,0(s4)
+a98: sb t7,0(s4)
+a9c: sb t3,0(s4)
+aa0: sb s7,0(s4)
+aa4: sb s5,0(s4)
+aa8: li v0,0x6f
+aac: sb v0,0(s4)
+ab0: li v0,0x41
+ab4: nop
+ab8: sb v0,0(s4)
+abc: sb s7,0(s4)
+ac0: sb s5,0(s4)
+ac4: li v0,0x4c
+ac8: sb v0,0(s4)
+acc: li v0,0x6f
+ad0: sb v0,0(s4)
+ad4: li v0,0x61
+ad8: sb v0,0(s4)
+adc: li v0,0x64
+ae0: sb v0,0(s4)
+ae4: sb s7,0(s4)
+ae8: sb s5,0(s4)
+aec: li v0,0x61
+af0: sb v0,0(s4)
+af4: or v0,zero,t8
+af8: lui v1,0x4142
+afc: ori v1,v1,0x4344
+b00: sw v1,16(v0)
+b04: lb a0,16(v0)
+b08: sb a0,0(s4)
+b0c: lb a0,17(v0)
+b10: sb a0,0(s4)
+b14: lb a0,18(v0)
+b18: sb a0,0(s4)
+b1c: lb v0,19(v0)
+b20: sb v0,0(s4)
+b24: sb s7,0(s4)
+b28: sb s5,0(s4)
+b2c: li v0,0x62
+b30: sb v0,0(s4)
+b34: or v0,zero,t8
+b38: lui v1,0x4142
+b3c: ori v1,v1,0x4344
+b40: sw v1,16(v0)
+b44: lb a0,16(v0)
+b48: sb a0,0(s4)
+b4c: lb a0,17(v0)
+b50: sb a0,0(s4)
+b54: lb a0,18(v0)
+b58: sb a0,0(s4)
+b5c: lb v0,19(v0)
+b60: sb v0,0(s4)
+b64: sb s7,0(s4)
+b68: sb s5,0(s4)
+b6c: li v0,0x63
+b70: sb v0,0(s4)
+b74: or v0,zero,t8
+b78: lui v1,0x41
+b7c: ori v1,v1,0x42
+b80: sw v1,16(v0)
+b84: lh a0,16(v0)
+b88: sb a0,0(s4)
+b8c: lh v0,18(v0)
+b90: sb v0,0(s4)
+b94: sb s7,0(s4)
+b98: sb s5,0(s4)
+b9c: li v0,0x64
+ba0: sb v0,0(s4)
+ba4: or v0,zero,t8
+ba8: lui v1,0x41
+bac: ori v1,v1,0x42
+bb0: sw v1,16(v0)
+bb4: lh a0,16(v0)
+bb8: sb a0,0(s4)
+bbc: lh v0,18(v0)
+bc0: sb v0,0(s4)
+bc4: sb s7,0(s4)
+bc8: sb s5,0(s4)
+bcc: li v0,0x65
+bd0: sb v0,0(s4)
+bd4: or v0,zero,t8
+bd8: li v1,65
+bdc: sw v1,16(v0)
+be0: li v1,0x0
+be4: lw v0,16(v0)
+be8: sb v0,0(s4)
+bec: sb s7,0(s4)
+bf0: sb s5,0(s4)
+bf4: li v0,0x66
+bf8: sb v0,0(s4)
+bfc: or v0,zero,t8
+c00: li v1,65
+c04: sw v1,16(v0)
+c08: li v1,0x0
+c0c: lwl v0,16(v0)
+c10: lwr v0,16(v0)
+c14: sb v0,0(s4)
+c18: sb s7,0(s4)
+c1c: sb s5,0(s4)
+c20: li v0,0x67
+c24: sb v0,0(s4)
+c28: li v0,0x41
+c2c: sb v0,0(s4)
+c30: sb s7,0(s4)
+c34: sb s5,0(s4)
+c38: li v0,0x68
+c3c: sb v0,0(s4)
+c40: or a0,zero,t8
+c44: li v0,0x4142
+c48: sh v0,16(a0)
+c4c: lb v1,16(a0)
+c50: sb v1,0(s4)
+c54: lb v0,17(a0)
+c58: sb v0,0(s4)
+c5c: sb s7,0(s4)
+c60: sb s5,0(s4)
+c64: li v0,0x69
+c68: sb v0,0(s4)
+c6c: or v0,zero,t8
+c70: lui v1,0x4142
+c74: ori v1,v1,0x4344
+c78: sw v1,16(v0)
+c7c: lb a0,16(v0)
+c80: sb a0,0(s4)
+c84: lb a0,17(v0)
+c88: sb a0,0(s4)
+c8c: lb a0,18(v0)
+c90: sb a0,0(s4)
+c94: lb v0,19(v0)
+c98: sb v0,0(s4)
+c9c: sb s7,0(s4)
+ca0: sb s5,0(s4)
+ca4: li v0,0x6a
+ca8: sb v0,0(s4)
+cac: or v0,zero,t8
+cb0: lui v1,0x4142
+cb4: ori v1,v1,0x4344
+cb8: swl v1,16(v0)
+cbc: swr v1,16(v0)
+cc0: lb a0,16(v0)
+cc4: sb a0,0(s4)
+cc8: lb a0,17(v0)
+ccc: sb a0,0(s4)
+cd0: lb a0,18(v0)
+cd4: sb a0,0(s4)
+cd8: lb v0,19(v0)
+cdc: sb v0,0(s4)
+ce0: sb s7,0(s4)
+ce4: sb s5,0(s4)
+ce8: li v0,0x4c
+cec: sb v0,0(s4)
+cf0: li v0,0x6f
+cf4: sb v0,0(s4)
+cf8: li v0,0x67
+cfc: sb v0,0(s4)
+d00: li v0,0x69
+d04: sb v0,0(s4)
+d08: li v0,0x63
+d0c: sb v0,0(s4)
+d10: sb s7,0(s4)
+d14: sb s5,0(s4)
+d18: li v0,0x61
+d1c: sb v0,0(s4)
+d20: li v0,0x741
+d24: li v1,0x60f3
+d28: and a0,v0,v1
+d2c: sb a0,0(s4)
+d30: sb s7,0(s4)
+d34: sb s5,0(s4)
+d38: li v0,0x62
+d3c: sb v0,0(s4)
+d40: li v0,0x741
+d44: andi a0,v0,0x60f3
+d48: sb a0,0(s4)
+d4c: sb s7,0(s4)
+d50: sb s5,0(s4)
+d54: li v0,0x63
+d58: sb v0,0(s4)
+d5c: lui v0,0x41
+d60: srl v1,v0,0x10
+d64: sb v1,0(s4)
+d68: sb s7,0(s4)
+d6c: sb s5,0(s4)
+d70: li v0,0x64
+d74: sb v0,0(s4)
+d78: lui v0,0xf0ff
+d7c: ori v0,v0,0xf08e
+d80: lui v1,0xf0f
+d84: ori v1,v1,0xf30
+d88: nor a0,v0,v1
+d8c: sb a0,0(s4)
+d90: sb s7,0(s4)
+d94: sb s5,0(s4)
+d98: li v0,0x65
+d9c: sb v0,0(s4)
+da0: li v0,0x40
+da4: li v1,0x1
+da8: or a0,v0,v1
+dac: sb a0,0(s4)
+db0: sb s7,0(s4)
+db4: sb s5,0(s4)
+db8: li v0,0x66
+dbc: sb v0,0(s4)
+dc0: li v0,0x40
+dc4: ori a0,v0,0x1
+dc8: sb a0,0(s4)
+dcc: sb s7,0(s4)
+dd0: sb s5,0(s4)
+dd4: li v0,0x67
+dd8: sb v0,0(s4)
+ddc: li v0,0xf043
+de0: li v1,0xf002
+de4: xor a0,v0,v1
+de8: sb a0,0(s4)
+dec: sb s7,0(s4)
+df0: sb s5,0(s4)
+df4: li v0,0x68
+df8: sb v0,0(s4)
+dfc: li v0,0xf043
+e00: xori a0,v0,0xf002
+e04: sb a0,0(s4)
+e08: sb s7,0(s4)
+e0c: sb s5,0(s4)
+e10: j 0xe10
+e14: nop
+e18: nop
+e1c: nop
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.code
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.code
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem.code
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,284 +1,904 @@
-3c190000
-27390050
-3c1d0800
-0320f809
-37bd8000
-00000000
-08000006
-00000000
-00000000
-27bdfffc
-afa80000
-2408000f
-00000000
-40888800
-00000000
-8fa80000
-27bd0004
-42000018
-00000000
-00000000
-3c1c0800
-279cffb0
-0399e021
-27bdffa8
-afbf0050
-afb7004c
-afb60048
-afb50044
-afb40040
-afb3003c
-afb20038
-afb10034
-afb00030
-afbc0010
-240200f0
-240300f1
-a7a20018
-a7a3001a
-240200f2
-240300f3
-a7a2001c
-a7a3001e
-240200f4
-240300f5
-a7a20020
-a7a30022
-240200f6
-240300f7
-27b70018
-a7a20024
-a7a30026
-240200f8
-240300f9
-8f950008
-8f940008
-8f930008
-a7a20028
-a7a3002a
-00008021
-02e08821
-2412000a
-8f990020
-00000000
-0320f809
-26a4002c
-8fbc0010
-02002021
-8f99001c
-00000000
-0320f809
-26100001
-8fbc0010
-00000000
-8f990020
-00000000
-0320f809
-26840030
-8fbc0010
-86240000
-8f990028
-00000000
-0320f809
-24050010
-8fbc0010
-26640034
-8f990020
-00000000
-0320f809
-26310002
-8fbc0010
-1612ffe2
-00000000
-8f960008
-8f990020
-00000000
-0320f809
-26c40038
-8fbc0010
-27a40018
-8f990024
-00000000
-0320f809
-2405000a
-8fbc0010
-02e08821
-00008021
-2412000a
-8f990020
-00000000
-0320f809
-26a4002c
-8fbc0010
-02002021
-8f99001c
-00000000
-0320f809
-26100001
-8fbc0010
-00000000
-8f990020
-00000000
-0320f809
-26840030
-8fbc0010
-86240000
-8f990028
-00000000
-0320f809
-24050010
-8fbc0010
-26640034
-8f990020
-00000000
-0320f809
-26310002
-8fbc0010
-1612ffe2
-00000000
-8f990020
-00000000
-0320f809
-26c40038
-87a20018
-8fbc0010
-8fbf0050
-8fb7004c
-8fb60048
-8fb50044
-8fb40040
-8fb3003c
-8fb20038
-8fb10034
-8fb00030
-03e00008
-27bd0058
-00000000
-8c820000
-03e00008
-00000000
-03e00008
-aca40000
-18a00016
-24840002
-00001021
-244a0001
-0145102a
-1040000e
-00000000
-00801821
-00004021
-00aa4823
-84660000
-8487fffe
-00000000
-00e6102a
-10400003
-25080001
-a486fffe
-a4670000
-1509fff7
-24630002
-24840002
-14aaffed
-01401021
-03e00008
-00000000
-00042600
-00042603
-24030004
-8c620000
-00000000
-1440fffd
-2402000c
-ac440000
-03e00008
-00000000
-80820000
-00000000
-1040000e
-24030004
-2406000c
-00022e00
-00052e03
-8c620000
-00000000
-1440fffd
-00000000
-acc50000
-24840001
-80820000
-00000000
-1440fff6
-00022e00
-03e00008
-00000000
-24a5fffc
-04a00012
-2407000c
-00a41007
-3042000f
-2843000a
-1060000f
-00000000
-24420030
-00021e00
-00031e03
-24060004
-8cc20000
-00000000
-1440fffd
-00000000
-ace30000
-24a5fffc
-04a1fff1
-00a41007
-03e00008
-00000000
-24420057
-00021600
-1000fff0
-00021603
-14800013
-3c026666
-24030004
-8c620000
-00000000
-1440fffd
-2402000c
-24030030
-ac430000
-03e00008
-00000000
-ac660000
-3c026666
-34426667
-00820018
-00001010
-00021083
-00472023
-1080fff6
-3c026666
-34426667
-00820018
-00043fc3
-24050004
-00001010
-00021083
-00471023
-000218c0
-00021040
-00431021
-00821023
-24420030
-00023600
-00063603
-8ca20000
-00000000
-1440fffd
-2403000c
-1000ffe4
-00000000
-00000000
-00000000
-00000000
+3c1c0000
+379c0000
+3c040000
+34840000
+3c050000
+34a50000
+3c1d0080
+37bd0000
+3c140080
+36940010
+3415000a
+34160058
+3417000d
+3c180080
+37180004
+3402004d
+a2820000
+3402006f
+a2820000
+34020076
+a2820000
+34020065
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34020041
+00400011
+00001810
+a2830000
+a2970000
+a2950000
+34020062
+a2820000
+34020041
+00400013
+00001812
+a2830000
+a2970000
+a2950000
+34020063
+a2820000
+34020041
+00400011
+00001810
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+34020041
+00400013
+00001812
+a2830000
+a2970000
+a2950000
+34020053
+a2820000
+34020068
+a2820000
+34020069
+a2820000
+34020066
+a2820000
+34020074
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+3c024041
+34424243
+00021a00
+00031e02
+a2830000
+a2970000
+a2950000
+34020062
+a2820000
+3c024041
+34424243
+34030008
+00621804
+00031e02
+a2830000
+a2970000
+a2950000
+34020063
+a2820000
+3c024041
+34424243
+00021c03
+a2830000
+3c028400
+00021e43
+2063ff80
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+3c024041
+34424243
+34030010
+00621807
+a2830000
+34030019
+3c028400
+00621807
+2063ff80
+a2830000
+a2970000
+a2950000
+34020065
+a2820000
+3c024041
+34424243
+00021c02
+a2830000
+3c028400
+00021e42
+a2830000
+a2970000
+a2950000
+34020066
+a2820000
+3c024041
+34424243
+34030010
+00622006
+a2840000
+34030019
+3c028400
+00621806
+a2830000
+a2970000
+a2950000
+34020044
+a2820000
+3402006f
+a2820000
+3402006e
+a2820000
+34020065
+a2820000
+a2970000
+a2950000
+34020041
+a2820000
+34020072
+a2820000
+34020069
+a2820000
+34020074
+a2820000
+34020068
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34030005
+3404003c
+00641020
+a2820000
+a2970000
+a2950000
+34020062
+a2820000
+3404003c
+20820005
+a2820000
+a2970000
+a2950000
+34020063
+a2820000
+34040032
+2485000f
+a2850000
+a2970000
+a2950000
+34020064
+a2820000
+34030005
+3404003c
+00641020
+a2820000
+a2970000
+a2950000
+34020065
+a2820000
+34021dde
+34030075
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+a2840000
+00002010
+20840019
+a2840000
+2402fb07
+34030013
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+00042022
+a2840000
+3402061c
+2403ffe9
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00000000
+00002012
+00042022
+a2840000
+2402fc7f
+2403fff3
+14600002
+0043001a
+0007000d
+2401ffff
+14610004
+3c018000
+14410002
+00000000
+0006000d
+00001012
+00002012
+a2840000
+a2970000
+a2950000
+34020066
+a2820000
+3402034d
+3403000d
+14600002
+0043001b
+0007000d
+00001012
+00000000
+00002012
+a2840000
+a2970000
+a2950000
+34020067
+a2820000
+34020005
+3403000d
+00430018
+00000000
+00002012
+a2840000
+2402fffb
+3403000d
+00430018
+00002810
+00002012
+00042022
+00852021
+20840002
+a2840000
+34020005
+2403fff3
+00430018
+00002810
+00002012
+00042022
+00852021
+20840003
+a2840000
+2402fffb
+2403fff3
+00430018
+00002810
+00002012
+00852021
+20840003
+a2840000
+3c04fe98
+348462e5
+3c050006
+34a58db8
+00850018
+00003010
+24c7097a
+a2870000
+a2970000
+a2950000
+34020068
+a2820000
+34020005
+3403000d
+00430019
+00000000
+00002012
+a2840000
+a2970000
+a2950000
+34020069
+a2820000
+3402000a
+3403000c
+0043202a
+20850040
+a2850000
+0062202a
+20850042
+a2850000
+2402fff0
+0043202a
+20850042
+a2850000
+0062202a
+20850044
+a2850000
+2403ffff
+0043202a
+20850044
+a2850000
+0062202a
+20850046
+a2850000
+a2970000
+a2950000
+3402006a
+a2820000
+3402000a
+2844000c
+20850040
+a2850000
+28440008
+20850042
+a2850000
+a2970000
+a2950000
+3402006b
+a2820000
+3402000a
+2c44000c
+20850040
+a2850000
+2c440008
+20850042
+a2850000
+a2970000
+a2950000
+3402006c
+a2820000
+3402000a
+3403000c
+0043202a
+20850040
+a2850000
+0062202a
+20850042
+a2850000
+a2970000
+a2950000
+3402006d
+a2820000
+34030046
+34040005
+00641022
+a2820000
+a2970000
+a2950000
+3402006e
+a2820000
+34030046
+34040005
+00641022
+a2820000
+a2970000
+a2950000
+34020042
+a2820000
+34020072
+a2820000
+34020061
+a2820000
+3402006e
+a2820000
+34020063
+a2820000
+34020068
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+340a0041
+340b0042
+10000002
+a28a0000
+a2960000
+a28b0000
+a2970000
+a2950000
+34020062
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+04110005
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+34020063
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3403007b
+3404007b
+10430005
+a28a0000
+a28b0000
+10640002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020064
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340f0058
+34020064
+3c03ffff
+34631234
+3404007b
+04610005
+a28a0000
+a28b0000
+04410002
+a28c0000
+a2960000
+04010002
+00000000
+a28f0000
+a28d0000
+a2970000
+a2950000
+34020065
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c03ffff
+34631234
+04710008
+00000000
+a28a0000
+04110005
+00000000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+34020066
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3c03ffff
+34631234
+1c600005
+a28a0000
+a28b0000
+1c400002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020067
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3c03ffff
+34631234
+18400005
+a28a0000
+a28b0000
+18600002
+a28c0000
+a2960000
+18000002
+00000000
+a2960000
+a28d0000
+a2970000
+a2950000
+34020068
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+34020064
+3c03ffff
+34631234
+34040000
+04400005
+a28a0000
+a28b0000
+04600002
+a28c0000
+a2960000
+04800002
+00000000
+a28d0000
+a28e0000
+a2970000
+a2950000
+34020069
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c03ffff
+34631234
+04100008
+00000000
+a28a0000
+04700005
+00000000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006a
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+34020064
+3403007b
+3404007b
+14640005
+a28a0000
+a28b0000
+14430002
+a28c0000
+a2960000
+a28d0000
+a2970000
+a2950000
+3402006b
+a2820000
+340a0041
+340b0042
+340f0058
+08000270
+a28a0000
+a28f0000
+a28b0000
+a2970000
+a2950000
+3402006c
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+0c000281
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006d
+a2820000
+340a0041
+340b0042
+340c0043
+340d0044
+340e0045
+340f0058
+3c030000
+24630a5c
+0060f809
+a28a0000
+a28d0000
+10000006
+a28e0000
+a28f0000
+a28b0000
+03e00008
+a28c0000
+a2960000
+a2970000
+a2950000
+3402006e
+a2820000
+340a0041
+340b0042
+340f0058
+3c030000
+24630a9c
+00600008
+a28a0000
+a28f0000
+a28b0000
+a2970000
+a2950000
+3402006f
+a2820000
+34020041
+00000000
+a2820000
+a2970000
+a2950000
+3402004c
+a2820000
+3402006f
+a2820000
+34020061
+a2820000
+34020064
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+34020062
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+34020063
+a2820000
+00181025
+3c030041
+34630042
+ac430010
+84440010
+a2840000
+84420012
+a2820000
+a2970000
+a2950000
+34020064
+a2820000
+00181025
+3c030041
+34630042
+ac430010
+84440010
+a2840000
+84420012
+a2820000
+a2970000
+a2950000
+34020065
+a2820000
+00181025
+24030041
+ac430010
+34030000
+8c420010
+a2820000
+a2970000
+a2950000
+34020066
+a2820000
+00181025
+24030041
+ac430010
+34030000
+88420010
+98420010
+a2820000
+a2970000
+a2950000
+34020067
+a2820000
+34020041
+a2820000
+a2970000
+a2950000
+34020068
+a2820000
+00182025
+34024142
+a4820010
+80830010
+a2830000
+80820011
+a2820000
+a2970000
+a2950000
+34020069
+a2820000
+00181025
+3c034142
+34634344
+ac430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+3402006a
+a2820000
+00181025
+3c034142
+34634344
+a8430010
+b8430010
+80440010
+a2840000
+80440011
+a2840000
+80440012
+a2840000
+80420013
+a2820000
+a2970000
+a2950000
+3402004c
+a2820000
+3402006f
+a2820000
+34020067
+a2820000
+34020069
+a2820000
+34020063
+a2820000
+a2970000
+a2950000
+34020061
+a2820000
+34020741
+340360f3
+00432024
+a2840000
+a2970000
+a2950000
+34020062
+a2820000
+34020741
+304460f3
+a2840000
+a2970000
+a2950000
+34020063
+a2820000
+3c020041
+00021c02
+a2830000
+a2970000
+a2950000
+34020064
+a2820000
+3c02f0ff
+3442f08e
+3c030f0f
+34630f30
+00432027
+a2840000
+a2970000
+a2950000
+34020065
+a2820000
+34020040
+34030001
+00432025
+a2840000
+a2970000
+a2950000
+34020066
+a2820000
+34020040
+34440001
+a2840000
+a2970000
+a2950000
+34020067
+a2820000
+3402f043
+3403f002
+00432026
+a2840000
+a2970000
+a2950000
+34020068
+a2820000
+3402f043
+3844f002
+a2840000
+a2970000
+a2950000
+08000384
+00000000
+00000000
+00000000
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem_init.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem_init.v
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/inst_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,54 +1,134 @@
-`ifndef __INST_INIT__
-`define __INST_INIT__
-
-`define INIT_INST_MEM \
-defparam bank0.INIT_00 =
256'h4004014104252400402240040040141042580120e848e8400000100000c02040 ;\
-defparam bank0.INIT_01 =
256'h3800102f0c34040c0ef200810430200040c05ac9e23529680000000001022400 ;\
-defparam bank0.INIT_02 = 256'h000430d0f0cebc ;\
-defparam bank1.INIT_00 =
256'h8808008c3820286282008108808008c3820aaa96505f0a006c6c800900cc1080 ;\
-defparam bank1.INIT_01 =
256'h9420f05004930c100edcc8400c037023c102304c2300380488286c6c2a000810 ;\
-defparam bank1.INIT_02 = 256'h007c0000012540 ;\
-defparam bank2.INIT_00 =
256'h08708406608a409708240b508708406608aa03e9faf5f5f7fc01ac04000c0004 ;\
-defparam bank2.INIT_01 =
256'h68033024c40f0c00c001c0c00c000000c000a0cc232a08840013fc015c2240b5 ;\
-defparam bank2.INIT_02 = 256'h008c03a0841ae1 ;\
-defparam bank3.INIT_00 =
256'h00000000000000000030000000000000000003c0f0f0f0f001558800000c0004 ;\
-defparam bank3.INIT_01 =
256'h14003010c40f0c000000c0c00c000000c00030cc030000000010015500030000 ;\
-defparam bank3.INIT_02 = 256'h00cc000720c5c8 ;\
-defparam bank4.INIT_00 =
256'h0000000000000000003000000000000000000000000000000000cc00000c0000 ;\
-defparam bank4.INIT_01 =
256'h28003022e00f0c0a0000c2c00c280000c0a030cc030000000000000000030000 ;\
-defparam bank4.INIT_02 = 256'h00cc280000cac0 ;\
-defparam bank5.INIT_00 =
256'h8008008008020800803080080080080080800000000000000000ce00080c00a0 ;\
-defparam bank5.INIT_01 =
256'h14003011d00f0c0f0000c3c00c3c0000c05030cc032200000000000002030800 ;\
-defparam bank5.INIT_02 = 256'h00cc140200c5c0 ;\
-defparam bank6.INIT_00 =
256'hc00c00c20c000c00c030c00c00c00c20c0000000000000000000ec00000c00c0 ;\
-defparam bank6.INIT_01 =
256'h28003021d01f0c050010c2c00c280000c0a070cc130104400000000003030c00 ;\
-defparam bank6.INIT_02 = 256'h00cc3c5554cae5 ;\
-defparam bank7.INIT_00 =
256'hc00c00c00c0a0c00c030c00c00c00c00c0a00000000000000000fc00080c02c0 ;\
-defparam bank7.INIT_01 =
256'h14003010c00f0c000000c0c00c000000c00030cc031400000000000003030c00 ;\
-defparam bank7.INIT_02 = 256'h00cc00000005c0 ;\
-defparam bank8.INIT_00 =
256'h04004004006010400621041040040040060ec7bbeeeeeee06c6f500100040115 ;\
-defparam bank8.INIT_01 =
256'haa0f82e22805c0ae838c4208409ac2020b00237823a0060002106c6f20121041 ;\
-defparam bank8.INIT_02 = 256'h0030aabae12a38 ;\
-defparam bank9.INIT_00 =
256'h09d08c08d080d09d090c09d09d08c08d080014010000000c0157ef0388ac033a ;\
-defparam bank9.INIT_01 =
256'h01000000001100100014400140110004005024961160061100300157c420c09d ;\
-defparam bank9.INIT_02 = 256'h00001000414010 ;\
-defparam banka.INIT_00 =
256'h86c84d84e852c86c851f86c86c84d84e858a542b0a0a0a0fffffd503802c039d ;\
-defparam banka.INIT_01 =
256'h0220020000aa800008228800008000200802222020a0000a883bffffe211f86c ;\
-defparam banka.INIT_02 = 256'h00008000000000 ;\
-defparam bankb.INIT_00 =
256'h08a08808a08380ab0a0809808a08808a08caa82a0a0a0a0aaaaaa80288280200 ;\
-defparam bankb.INIT_01 =
256'h9134110804eac4c045628c4ac4401234440369187262152ace2eaaaaac208098 ;\
-defparam bankb.INIT_02 = 256'h00048190402490 ;\
-defparam bankc.INIT_00 =
256'hceecceceecc2ccfecf2ececceecceceecc8ffc3f0f0f0f0ffffffc0bc03c03cc ;\
-defparam bankc.INIT_01 =
256'h0030000000c0000000000c00000000300003404100000400cc3ffffffb32ecec ;\
-defparam bankc.INIT_02 = 256'h00000000000000 ;\
-defparam bankd.INIT_00 =
256'h0dd0cd0cd0d0d0dd0f1d0dd0dd0cd0cd0d05fd555555555fffff4701c0742137 ;\
-defparam bankd.INIT_01 =
256'h1f0d53740405c4d042054041c4c1400d4d0015550140011b0313ffffd431d0dd ;\
-defparam bankd.INIT_02 = 256'h0014c100010700 ;\
-defparam banke.INIT_00 =
256'h00200200202020220012022002002002020a02aaaaaaaaaaaaaa8b0200a8033b ;\
-defparam banke.INIT_01 =
256'h3e0a90b44802842086c880428402900a42001a6a400012260020000008012022 ;\
-defparam banke.INIT_02 = 256'h00640200020f40 ;\
-defparam bankf.INIT_00 =
256'h0a808808808080880a080880a8088088080aa8280a0a0a0aaaaa000484200000 ;\
-defparam bankf.INIT_01 =
256'h0208020000008080000000088080020808000028028000020202aaaaa0208088 ;\
-defparam bankf.INIT_02 = 256'h00008000000000
-
-`endif
+`ifndef __INST_INIT__
+`define __INST_INIT__
+
+`define INIT_INST_MEM \
+defparam bank0.INIT_00 =
256'h48082d100c4cd000c3d3020d20234400840c0b40014c0b480144048c41200000 ;\
+defparam bank0.INIT_01 =
256'h2920daf28920da428920daf108920da610010038c04200110001210123002123 ;\
+defparam bank0.INIT_02 =
256'h0a0880080230200880a0b08a0a08840854008090d83cda0d2681c814c089e520 ;\
+defparam bank0.INIT_03 =
256'h8000204031391002081cc0e400081f0e4c0002044e4800a4400c848809880984 ;\
+defparam bank0.INIT_04 =
256'h2044e400009300207c39200008100c4e440082043139000208130e4c008130e4 ;\
+defparam bank0.INIT_05 =
256'h480014408094008094c0c8402480c840244004c0013000024800020404e44000 ;\
+defparam bank0.INIT_06 =
256'hc00acc0420141033b0024c0d200d10313300321002480c840244040900130001 ;\
+defparam bank0.INIT_07 = 256'h0002 ;\
+defparam bank1.INIT_00 =
256'h0400001004840100000000600000000448800004000000000000044cd3a00000 ;\
+defparam bank1.INIT_01 =
256'h0301f8300301f8b00301f81200301f87100d1030007000d00212000133101210 ;\
+defparam bank1.INIT_02 =
256'h020b8c020e2008388061b182020b8800b4808a5800880021000b80b440038f10 ;\
+defparam bank1.INIT_03 =
256'h40201042794010000019d90040001a5000020106500000000080c000014c014c ;\
+defparam bank1.INIT_04 =
256'h102500c0020200006940200804109e5008000004754020000017500400017500 ;\
+defparam bank1.INIT_05 =
256'h44000440000440000400000044000000440040cc003002c80c02010b2500c020 ;\
+defparam bank1.INIT_06 =
256'h0804040010101013f10000000010000213300000044800000448000120010000 ;\
+defparam bank1.INIT_07 = 256'h0100 ;\
+defparam bank2.INIT_00 =
256'h0800002000410200000200002000080c8884050805080508050808c800440000 ;\
+defparam bank2.INIT_01 =
256'h1400c4f24400c4924400c44144400c4d202c200c803202c20232300222000104 ;\
+defparam bank2.INIT_02 =
256'h02080800002000008020b082c20808044080d724257c295c0a54c44080444020 ;\
+defparam bank2.INIT_03 =
256'h80000000f4002000000fe40080000f800800000100080000808888c008080808 ;\
+defparam bank2.INIT_04 =
256'h001000800d0200003e00200000003d0008000000f8002000000f80080000f800 ;\
+defparam bank2.INIT_05 =
256'h8804488045088045088044450880444508808880002000440800000110008000 ;\
+defparam bank2.INIT_06 =
256'h080808002020202c3200080c202c202222001111508804445088045220020144 ;\
+defparam bank2.INIT_07 = 256'h0000 ;\
+defparam bank3.INIT_00 =
256'h4404051020005102405100051001440444440044004400440044044448422000 ;\
+defparam bank3.INIT_01 =
256'h0000c0d00000c0c00000c00000000c0710001000400100010111110111100001 ;\
+defparam bank3.INIT_02 =
256'h041004041010104040413104c410040000404238003c000c0000c00040000110 ;\
+defparam bank3.INIT_03 =
256'h40000000355510000004d5544000055544000001554400144044444400440044 ;\
+defparam bank3.INIT_04 =
256'h00955440055100001555100000000d5544000000355510000003554400003554 ;\
+defparam bank3.INIT_05 =
256'h0400104000504000504000005040000050404444011000854400000115544000 ;\
+defparam bank3.INIT_06 =
256'h4400440110011000b100440d100d101111100000050400000504000410110001 ;\
+defparam bank3.INIT_07 = 256'h0200 ;\
+defparam bank4.INIT_00 =
256'h000808003000800380800208002a000000000000000000000000000000000000 ;\
+defparam bank4.INIT_01 =
256'h0000c0c00000c0e00000c03000000c0100000000000000000000000000000002 ;\
+defparam bank4.INIT_02 =
256'h000000000000000000003000c000000000004128003c000c0000c00000000300 ;\
+defparam bank4.INIT_03 =
256'h00000000b00000000002c0000000000000000000000000000000000000000000 ;\
+defparam bank4.INIT_04 =
256'h00800000080000000000000000002c0000000000b0000000000b00000000b000 ;\
+defparam bank4.INIT_05 =
256'h000000000000000000000000d0000000d0000000000000800000000200000000 ;\
+defparam bank4.INIT_06 =
256'h000000000000000f0000000300030000000000000d0000000d00000400000000 ;\
+defparam bank4.INIT_07 = 256'h0300 ;\
+defparam bank5.INIT_00 =
256'h000d300039080003d30003800038000000000800080008000800000000000000 ;\
+defparam bank5.INIT_01 =
256'h0000c0f00000c0d00000c02000000c0300000000000000000000000000002400 ;\
+defparam bank5.INIT_02 =
256'h000000000000000000003000c00000000000830c023c008c0020c00000000000 ;\
+defparam bank5.INIT_03 =
256'h00000000300000000000c0000000000000000000000000000000000000000000 ;\
+defparam bank5.INIT_04 =
256'h00000000000000000000000000000c0000000000300000000003000000003000 ;\
+defparam bank5.INIT_05 =
256'h0000000000000000000000000000000000000000000000800000000a00000000 ;\
+defparam bank5.INIT_06 =
256'h000000000000000f000300010001000000000000000000000000000000000000 ;\
+defparam bank5.INIT_07 = 256'h0000 ;\
+defparam bank6.INIT_00 =
256'h0004100034040003410001400014000000000400040004000400000000000000 ;\
+defparam bank6.INIT_01 =
256'h2400c0f28400c0c28400c03088400c0100100000000001000000000000001020 ;\
+defparam bank6.INIT_02 =
256'h02080000000000000020b082c20800080000302c2a3c2a8c0aa0c80000840000 ;\
+defparam bank6.INIT_03 =
256'h00000000700000000001c0000000000000000000000000000000000004000400 ;\
+defparam bank6.INIT_04 =
256'h00000000000000000000000000001c0000000000700000000007000000007000 ;\
+defparam bank6.INIT_05 =
256'h4000040000040000040000000400000004000000000000000000000c00000000 ;\
+defparam bank6.INIT_06 =
256'hc00bc00000200020f00100080028000000000000004000000040000200000000 ;\
+defparam bank6.INIT_07 = 256'h0003 ;\
+defparam bank7.INIT_00 =
256'h4002050032005003205000050001400000000000000000000000000000000000 ;\
+defparam bank7.INIT_01 =
256'h0008c0f00008c0c00008c03000008c0000000000000000000000000000000801 ;\
+defparam bank7.INIT_02 =
256'h000000000000000000003000c00000000000021c003c000c0000c00000000000 ;\
+defparam bank7.INIT_03 =
256'h00000000300000000000c0000000000000000000000000000000000000000000 ;\
+defparam bank7.INIT_04 =
256'h00000000000000000000000000000c0000000000300000000003000000003000 ;\
+defparam bank7.INIT_05 =
256'h0000000000000000000000005000000050000000000000000000000c00000000 ;\
+defparam bank7.INIT_06 =
256'hc003c00000000000f00000040004000000000000050000000500000400000000 ;\
+defparam bank7.INIT_07 = 256'h0003 ;\
+defparam bank8.INIT_00 =
256'ha9faeaa7fafbaa7faeaa7fbaa7faa9eaaaa9f0a9f0a9f0a9f0a9eaaa83905500 ;\
+defparam bank8.INIT_01 =
256'h02157ce002157ce002157ce0002157cea783a7529e8a783a7aaaaa7aaaa7eb2e ;\
+defparam bank8.INIT_02 =
256'hd65fa9d452a7514a9d65f597965fa9c0fa9fc54010f8103e040f80fa9c03cea7 ;\
+defparam bank8.INIT_03 =
256'h9e0f8461fe4ea7718793ed3a9d83b393a9e0f86793a9fa3a9eaaaaa9e0e9e0e9 ;\
+defparam bank8.INIT_04 =
256'h86393a9fe3ea763e0e4ea783e1083f93a9e420e0fa4ea760838f93a9d838f93a ;\
+defparam bank8.INIT_05 =
256'h29ebf29e83f29e83f29e8003f29e8003f29eaaa9e2a7f8ffa9e0f863f93a9e0f ;\
+defparam bank8.INIT_06 =
256'ha9cfa9c2a73ea73faa7ea9c2a73ea7aaaaa7a000ff29e8003f29ebe8a7aa7abf ;\
+defparam bank8.INIT_07 = 256'h0070 ;\
+defparam bank9.INIT_00 =
256'h014000050000005000005000050001400001400140014001400140002955f55f ;\
+defparam bank9.INIT_01 =
256'h4100100501001005010010051010010005140554141051405000005000050040 ;\
+defparam bank9.INIT_02 =
256'h5450015554055550154505141450015000154555500154005500100015010005 ;\
+defparam bank9.INIT_03 =
256'h15cbcc200ffa05f072840fe81776843e815cbce3fe8166281400000145014501 ;\
+defparam bank9.INIT_04 =
256'hce3fe816e3a05dca50fa0572f30803fe817c1ca103fa05d072803e81772803e8 ;\
+defparam bank9.INIT_05 =
256'h81400814140814140814155408141554081400014005b80e815cbce03fe815cb ;\
+defparam bank9.INIT_06 =
256'h0150015405400540005001540540050000050555008141554081400205005000 ;\
+defparam bank9.INIT_07 = 256'h0055 ;\
+defparam banka.INIT_00 =
256'h014000052808005200005080050001400001400140014001400140001555d805 ;\
+defparam banka.INIT_01 =
256'h0002020000020200000202000000202005200500140052005000005000052020 ;\
+defparam banka.INIT_02 =
256'h4200014000050000142000800200014000140200000000000000000014002005 ;\
+defparam banka.INIT_03 =
256'h1520004380000500402200001448000001520004000144001400000148014801 ;\
+defparam banka.INIT_04 =
256'h0000001400005100800005480030600001401200800005104808000144028000 ;\
+defparam banka.INIT_05 =
256'h4140041400841400841400008414000084140001400502800152000a00001520 ;\
+defparam banka.INIT_06 =
256'h0140014005000508005001400500050000050000084140000841400105005000 ;\
+defparam banka.INIT_07 = 256'h0050 ;\
+defparam bankb.INIT_00 =
256'h22a0848a942448a90848a8448a8122a22222a122a122a122a122a22200088888 ;\
+defparam bankb.INIT_01 =
256'h80110508001105080011050a200110508a908aa22a88a908a88888a8888a9091 ;\
+defparam bankb.INIT_02 =
256'ha9a422a9a48aa6922a9a4a6929a422a0422aca22a042a010a80420422a00508a ;\
+defparam bankb.INIT_03 =
256'h2aba882140008aa0a69100022aa6900022aba8a00022aa022a222222a422a422 ;\
+defparam bankb.INIT_04 =
256'h8a00022aa008aa9a40008aaea218100022a8a9a440008aa0a6940022aa694002 ;\
+defparam bankb.INIT_05 =
256'h22a4422a65422a65422a6665422a6665422a2222a08aa94022aba8a500022aba ;\
+defparam bankb.INIT_06 =
256'h22a422a48a908a9448a822a48a908a88888a99995422a6665422aaa08a88a944 ;\
+defparam bankb.INIT_07 = 256'h00a9 ;\
+defparam bankc.INIT_00 =
256'h22a0808a802008a80808a8008a8022a22222a022a022a022a022a2223008c00c ;\
+defparam bankc.INIT_01 =
256'h800000080000000800000008200000008a808a822a08a808a88888a8888a8080 ;\
+defparam bankc.INIT_02 =
256'ha08022a0808a82022a080820208022a0022a000200020000800020022a00008a ;\
+defparam bankc.INIT_03 =
256'h2aba882000008aa0a28000022aa2800022aba8a00022aa022a222222a022a022 ;\
+defparam bankc.INIT_04 =
256'h8a00022aa008aa8a00008aaea208000022a828a000008aa0a2800022aa280002 ;\
+defparam bankc.INIT_05 =
256'h22a0022a20022a20022a2220022a2220022a2222a08aa80022aba8a000022aba ;\
+defparam bankc.INIT_06 =
256'h22a022a08a808a8008a822a08a808a88888a88880022a2220022a2008a88a800 ;\
+defparam bankc.INIT_07 = 256'h00a8 ;\
+defparam bankd.INIT_00 =
256'hc403071003417100307100171001c4044444004400440044004404445d577777 ;\
+defparam bankd.INIT_01 =
256'h001d4150001d4150001d41500001d41510051014401100510111110111100d05 ;\
+defparam bankd.INIT_02 =
256'h000144030d1008244000100040014400144041dc001400050001401440001510 ;\
+defparam bankd.INIT_03 =
256'h40000041755510010415d5544000055544000005554400144044444401440144 ;\
+defparam bankd.INIT_04 =
256'h00d55440095100105555100000105d5544004105755510020827554400c37554 ;\
+defparam bankd.INIT_05 =
256'h040dd040477040477040000370400003704044440110007544000001d5544000 ;\
+defparam bankd.INIT_06 =
256'h44014405100510077100c4011005101111100000a7040000370400141011029d ;\
+defparam bankd.INIT_07 = 256'h0202 ;\
+defparam banke.INIT_00 =
256'heea38fbaa3e3fbaa38fba83fba83eeaeeeeea0eea0eea0eea0eeaeeeffffffff ;\
+defparam banke.INIT_01 =
256'h801d81a8001d81b8001d81ea2001d81fba8fbaaeeabba8fbabbbbbabbbba8f8f ;\
+defparam banke.INIT_02 =
256'ha8a3eeaaabbaaaaeea8a2a28a8a3eea03eea83fe802a800ba003a03eea001fba ;\
+defparam banke.INIT_03 =
256'hea8a9820ffffbaa0a28ffffeeaa69fffeea8a9a3ffeeaa7eeaeeeeeea3eea3ee ;\
+defparam banke.INIT_04 =
256'h9a3ffeeaa3fbaa9a7fffbaa2a6083fffeea828a3ffffbaa1a69fffeeaa69fffe ;\
+defparam banke.INIT_05 =
256'h2ea3a2ea22f2ea22f2ea2222f2ea2222f2eaeeeea3baa8bfeea8a9a2fffeea8a ;\
+defparam banke.INIT_06 =
256'heea3eeafba8fba8ffba8eeafba8fbabbbbba8888ef2ea2222f2ea22cbabba93a ;\
+defparam banke.INIT_07 = 256'h00ab ;\
+defparam bankf.INIT_00 =
256'h22a0808a802008a80808a8008a8022a22222a022a022a022a022a22200000000 ;\
+defparam bankf.INIT_01 =
256'h800000080000000800000008200000008a808a822a08a808a88888a8888a8080 ;\
+defparam bankf.INIT_02 =
256'ha08022a0808a82022a080820208022a0022a000200020000800020022a00008a ;\
+defparam bankf.INIT_03 =
256'h2a8a882000008aa0a28000022aa2800022a8a8a00022aa022a222222a022a022 ;\
+defparam bankf.INIT_04 =
256'h8a00022aa008aa8a00008aa2a208000022a828a000008aa0a2800022aa280002 ;\
+defparam bankf.INIT_05 =
256'h22a8822aaa022aaa022aaaaa022aaaaa022a2222a08aa80022a8a8a000022a8a ;\
+defparam bankf.INIT_06 =
256'h22a022a08a808a8008a822a08a808a88888aaaaaa022aaaaa022aaa08a88aa88 ;\
+defparam bankf.INIT_07 = 256'h00a8
+
+`endif
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort.s
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_sort.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,329 @@
+
+ld_sort: file format elf32-tradlittlemips
+
+Disassembly of section .init:
+
+00000000 <here-0x18>:
+ 0: 3c190000 lui t9,0x0
+ 4: 27390050 addiu t9,t9,80
+ 8: 3c1d0800 lui sp,0x800
+ c: 0320f809 jalr t9
+ 10: 37bd8000 ori sp,sp,0x8000
+ 14: 00000000 nop
+
+00000018 <here>:
+ 18: 08000006 j 18 <here>
+ 1c: 00000000 nop
+ 20: 00000000 nop
+Disassembly of section .interrupt:
+
+00000024 <.interrupt>:
+ 24: 27bdfffc addiu sp,sp,-4
+ 28: afa80000 sw t0,0(sp)
+ 2c: 2408000f li t0,15
+ 30: 00000000 nop
+ 34: 40888800 mtc0 t0,$17
+ 38: 00000000 nop
+ 3c: 8fa80000 lw t0,0(sp)
+ 40: 27bd0004 addiu sp,sp,4
+ 44: 42000018 c0 0x18
+ 48: 00000000 nop
+ 4c: 00000000 nop
+Disassembly of section .text:
+
+00000050 <main>:
+ 50: 3c1c0800 lui gp,0x800
+ 54: 279cffb0 addiu gp,gp,-80
+ 58: 0399e021 addu gp,gp,t9
+ 5c: 27bdffb0 addiu sp,sp,-80
+ 60: afbf004c sw ra,76(sp)
+ 64: afb60048 sw s6,72(sp)
+ 68: afb50044 sw s5,68(sp)
+ 6c: afb40040 sw s4,64(sp)
+ 70: afb3003c sw s3,60(sp)
+ 74: afb20038 sw s2,56(sp)
+ 78: afb10034 sw s1,52(sp)
+ 7c: afb00030 sw s0,48(sp)
+ 80: afbc0010 sw gp,16(sp)
+ 84: 240200f0 li v0,240
+ 88: 240300f1 li v1,241
+ 8c: a7a20018 sh v0,24(sp)
+ 90: a7a3001a sh v1,26(sp)
+ 94: 240200f2 li v0,242
+ 98: 240300f3 li v1,243
+ 9c: a7a2001c sh v0,28(sp)
+ a0: a7a3001e sh v1,30(sp)
+ a4: 240200f4 li v0,244
+ a8: 240300f5 li v1,245
+ ac: a7a20020 sh v0,32(sp)
+ b0: a7a30022 sh v1,34(sp)
+ b4: 240200f6 li v0,246
+ b8: 240300f7 li v1,247
+ bc: 27b60018 addiu s6,sp,24
+ c0: a7a20024 sh v0,36(sp)
+ c4: a7a30026 sh v1,38(sp)
+ c8: 240200f8 li v0,248
+ cc: 240300f9 li v1,249
+ d0: 8f940008 lw s4,8(gp)
+ d4: 8f930008 lw s3,8(gp)
+ d8: 8f920008 lw s2,8(gp)
+ dc: a7a20028 sh v0,40(sp)
+ e0: a7a3002a sh v1,42(sp)
+ e4: 00008021 move s0,zero
+ e8: 02c08821 move s1,s6
+ ec: 8f990020 lw t9,32(gp)
+ f0: 00000000 nop
+ f4: 0320f809 jalr t9
+ f8: 2684002c addiu a0,s4,44
+ fc: 8fbc0010 lw gp,16(sp)
+ 100: 02002021 move a0,s0
+ 104: 8f990024 lw t9,36(gp)
+ 108: 00000000 nop
+ 10c: 0320f809 jalr t9
+ 110: 26100001 addiu s0,s0,1
+ 114: 8fbc0010 lw gp,16(sp)
+ 118: 00000000 nop
+ 11c: 8f990020 lw t9,32(gp)
+ 120: 00000000 nop
+ 124: 0320f809 jalr t9
+ 128: 26640030 addiu a0,s3,48
+ 12c: 8fbc0010 lw gp,16(sp)
+ 130: 86240000 lh a0,0(s1)
+ 134: 8f990028 lw t9,40(gp)
+ 138: 00000000 nop
+ 13c: 0320f809 jalr t9
+ 140: 24050010 li a1,16
+ 144: 8fbc0010 lw gp,16(sp)
+ 148: 26440034 addiu a0,s2,52
+ 14c: 8f990020 lw t9,32(gp)
+ 150: 00000000 nop
+ 154: 0320f809 jalr t9
+ 158: 26310002 addiu s1,s1,2
+ 15c: 2a02000a slti v0,s0,10
+ 160: 8fbc0010 lw gp,16(sp)
+ 164: 1440ffe1 bnez v0,ec <main+0x9c>
+ 168: 00000000 nop
+ 16c: 8f950008 lw s5,8(gp)
+ 170: 8f990020 lw t9,32(gp)
+ 174: 00000000 nop
+ 178: 0320f809 jalr t9
+ 17c: 26a40038 addiu a0,s5,56
+ 180: 8fbc0010 lw gp,16(sp)
+ 184: 27a40018 addiu a0,sp,24
+ 188: 8f99001c lw t9,28(gp)
+ 18c: 00000000 nop
+ 190: 0320f809 jalr t9
+ 194: 2405000a li a1,10
+ 198: 8fbc0010 lw gp,16(sp)
+ 19c: 02c08821 move s1,s6
+ 1a0: 00008021 move s0,zero
+ 1a4: 8f990020 lw t9,32(gp)
+ 1a8: 00000000 nop
+ 1ac: 0320f809 jalr t9
+ 1b0: 2684002c addiu a0,s4,44
+ 1b4: 8fbc0010 lw gp,16(sp)
+ 1b8: 02002021 move a0,s0
+ 1bc: 8f990024 lw t9,36(gp)
+ 1c0: 00000000 nop
+ 1c4: 0320f809 jalr t9
+ 1c8: 26100001 addiu s0,s0,1
+ 1cc: 8fbc0010 lw gp,16(sp)
+ 1d0: 00000000 nop
+ 1d4: 8f990020 lw t9,32(gp)
+ 1d8: 00000000 nop
+ 1dc: 0320f809 jalr t9
+ 1e0: 26640030 addiu a0,s3,48
+ 1e4: 8fbc0010 lw gp,16(sp)
+ 1e8: 86240000 lh a0,0(s1)
+ 1ec: 8f990028 lw t9,40(gp)
+ 1f0: 00000000 nop
+ 1f4: 0320f809 jalr t9
+ 1f8: 24050010 li a1,16
+ 1fc: 8fbc0010 lw gp,16(sp)
+ 200: 26440034 addiu a0,s2,52
+ 204: 8f990020 lw t9,32(gp)
+ 208: 00000000 nop
+ 20c: 0320f809 jalr t9
+ 210: 26310002 addiu s1,s1,2
+ 214: 2a02000a slti v0,s0,10
+ 218: 8fbc0010 lw gp,16(sp)
+ 21c: 1440ffe1 bnez v0,1a4 <main+0x154>
+ 220: 00000000 nop
+ 224: 8f990020 lw t9,32(gp)
+ 228: 00000000 nop
+ 22c: 0320f809 jalr t9
+ 230: 26a40038 addiu a0,s5,56
+ 234: 87a20018 lh v0,24(sp)
+ 238: 8fbc0010 lw gp,16(sp)
+ 23c: 8fbf004c lw ra,76(sp)
+ 240: 8fb60048 lw s6,72(sp)
+ 244: 8fb50044 lw s5,68(sp)
+ 248: 8fb40040 lw s4,64(sp)
+ 24c: 8fb3003c lw s3,60(sp)
+ 250: 8fb20038 lw s2,56(sp)
+ 254: 8fb10034 lw s1,52(sp)
+ 258: 8fb00030 lw s0,48(sp)
+ 25c: 03e00008 jr ra
+ 260: 27bd0050 addiu sp,sp,80
+ 264: 00000000 nop
+ 268: 00000000 nop
+ 26c: 00000000 nop
+
+00000270 <get_word>:
+ 270: 8c820000 lw v0,0(a0)
+ 274: 03e00008 jr ra
+ 278: 00000000 nop
+
+0000027c <put_word>:
+ 27c: 03e00008 jr ra
+ 280: aca40000 sw a0,0(a1)
+
+00000284 <put_char>:
+ 284: 00042600 sll a0,a0,0x18
+ 288: 00042603 sra a0,a0,0x18
+ 28c: 24030004 li v1,4
+ 290: 8c620000 lw v0,0(v1)
+ 294: 00000000 nop
+ 298: 1440fffd bnez v0,290 <put_char+0xc>
+ 29c: 2402000c li v0,12
+ 2a0: ac440000 sw a0,0(v0)
+ 2a4: 03e00008 jr ra
+ 2a8: 00000000 nop
+
+000002ac <put_str>:
+ 2ac: 80820000 lb v0,0(a0)
+ 2b0: 00000000 nop
+ 2b4: 1040000e beqz v0,2f0 <put_str+0x44>
+ 2b8: 00000000 nop
+ 2bc: 00401821 move v1,v0
+ 2c0: 24050004 li a1,4
+ 2c4: 2406000c li a2,12
+ 2c8: 8ca20000 lw v0,0(a1)
+ 2cc: 00000000 nop
+ 2d0: 1440fffd bnez v0,2c8 <put_str+0x1c>
+ 2d4: 00000000 nop
+ 2d8: acc30000 sw v1,0(a2)
+ 2dc: 24840001 addiu a0,a0,1
+ 2e0: 80830000 lb v1,0(a0)
+ 2e4: 00000000 nop
+ 2e8: 1460fff7 bnez v1,2c8 <put_str+0x1c>
+ 2ec: 00000000 nop
+ 2f0: 03e00008 jr ra
+ 2f4: 00000000 nop
+
+000002f8 <put_hex>:
+ 2f8: 24a5fffc addiu a1,a1,-4
+ 2fc: 04a00010 bltz a1,340 <put_hex+0x48>
+ 300: 00a41007 srav v0,a0,a1
+ 304: 2407000c li a3,12
+ 308: 3046000f andi a2,v0,0xf
+ 30c: 28c3000a slti v1,a2,10
+ 310: 1060000d beqz v1,348 <put_hex+0x50>
+ 314: 24c20057 addiu v0,a2,87
+ 318: 24c60030 addiu a2,a2,48
+ 31c: 24030004 li v1,4
+ 320: 8c620000 lw v0,0(v1)
+ 324: 00000000 nop
+ 328: 1440fffd bnez v0,320 <put_hex+0x28>
+ 32c: 00000000 nop
+ 330: ace60000 sw a2,0(a3)
+ 334: 24a5fffc addiu a1,a1,-4
+ 338: 04a1fff3 bgez a1,308 <put_hex+0x10>
+ 33c: 00a41007 srav v0,a0,a1
+ 340: 03e00008 jr ra
+ 344: 00000000 nop
+ 348: 00023600 sll a2,v0,0x18
+ 34c: 1000fff3 b 31c <put_hex+0x24>
+ 350: 00063603 sra a2,a2,0x18
+
+00000354 <put_decu>:
+ 354: 1480000a bnez a0,380 <put_decu+0x2c>
+ 358: 3c026666 lui v0,0x6666
+ 35c: 24040030 li a0,48
+ 360: 24030004 li v1,4
+ 364: 8c620000 lw v0,0(v1)
+ 368: 00000000 nop
+ 36c: 1440fffd bnez v0,364 <put_decu+0x10>
+ 370: 2402000c li v0,12
+ 374: ac440000 sw a0,0(v0)
+ 378: 03e00008 jr ra
+ 37c: 00000000 nop
+ 380: 34486667 ori t0,v0,0x6667
+ 384: 24050004 li a1,4
+ 388: 2407000c li a3,12
+ 38c: 00880018 mult a0,t0
+ 390: 000437c3 sra a2,a0,0x1f
+ 394: 00001810 mfhi v1
+ 398: 00031883 sra v1,v1,0x2
+ 39c: 00661823 subu v1,v1,a2
+ 3a0: 00031080 sll v0,v1,0x2
+ 3a4: 00431021 addu v0,v0,v1
+ 3a8: 00021040 sll v0,v0,0x1
+ 3ac: 00821023 subu v0,a0,v0
+ 3b0: 24420030 addiu v0,v0,48
+ 3b4: 00021e00 sll v1,v0,0x18
+ 3b8: 00031e03 sra v1,v1,0x18
+ 3bc: 8ca20000 lw v0,0(a1)
+ 3c0: 00000000 nop
+ 3c4: 1440fffd bnez v0,3bc <put_decu+0x68>
+ 3c8: 00000000 nop
+ 3cc: ace30000 sw v1,0(a3)
+ 3d0: 00880018 mult a0,t0
+ 3d4: 00001010 mfhi v0
+ 3d8: 00021083 sra v0,v0,0x2
+ 3dc: 00462023 subu a0,v0,a2
+ 3e0: 1480ffea bnez a0,38c <put_decu+0x38>
+ 3e4: 00000000 nop
+ 3e8: 03e00008 jr ra
+ 3ec: 00000000 nop
+
+000003f0 <sort>:
+ 3f0: 18a00018 blez a1,454 <sort+0x64>
+ 3f4: 00001821 move v1,zero
+ 3f8: 246b0001 addiu t3,v1,1
+ 3fc: 0165102a slt v0,t3,a1
+ 400: 10400012 beqz v0,44c <sort+0x5c>
+ 404: 01603821 move a3,t3
+ 408: 00031040 sll v0,v1,0x1
+ 40c: 000b1840 sll v1,t3,0x1
+ 410: 00445021 addu t2,v0,a0
+ 414: 00641821 addu v1,v1,a0
+ 418: 94680000 lhu t0,0(v1)
+ 41c: 85460000 lh a2,0(t2)
+ 420: 00081400 sll v0,t0,0x10
+ 424: 00021403 sra v0,v0,0x10
+ 428: 24e70001 addiu a3,a3,1
+ 42c: 00c2102a slt v0,a2,v0
+ 430: 10400003 beqz v0,440 <sort+0x50>
+ 434: 00e5482a slt t1,a3,a1
+ 438: a5480000 sh t0,0(t2)
+ 43c: a4660000 sh a2,0(v1)
+ 440: 1520fff5 bnez t1,418 <sort+0x28>
+ 444: 24630002 addiu v1,v1,2
+ 448: 0165102a slt v0,t3,a1
+ 44c: 1440ffea bnez v0,3f8 <sort+0x8>
+ 450: 01601821 move v1,t3
+ 454: 03e00008 jr ra
+ 458: 00000000 nop
+ 45c: 00000000 nop
+Disassembly of section .got:
+
+08000000 <_GLOBAL_OFFSET_TABLE_>:
+ 8000000: 00000000 nop
+ 8000004: 80000000 lb zero,0(zero)
+ 8000008: 08000000 j 0 <here-0x18>
+ 800000c: 00000000 nop
+ 8000010: 00000000 nop
+ 8000014: 00000000 nop
+ 8000018: 00000000 nop
+ 800001c: 000003f0 0x3f0
+ 8000020: 000002ac 0x2ac
+ 8000024: 00000354 0x354
+ 8000028: 000002f8 0x2f8
+Disassembly of section .rodata:
+
+0800002c <.rodata>:
+ 800002c: 00005b61 0x5b61
+ 8000030: 00003d5d 0x3d5d
+ 8000034: 0000000a 0xa
+ 8000038: 000a0a0a 0xa0a0a
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code_sw
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_test_code_sw
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_timtest
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/ld_timtest
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data.data
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data_init.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data_init.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_data_mem.data_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,7 @@
+`ifndef __DATA_INIT__
+`define __DATA_INIT__
+
+`define INIT_DATA_MEM defparam bank0.bank0.INIT_00 = 256'h0
+
+
+`endif
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code.asm
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code.code
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code_init.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code_init.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_inst_mem.code_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,7 @@
+`ifndef __INST_INIT__
+`define __INST_INIT__
+
+`define INIT_INST_MEM defparam bank0.INIT_00 = 256'h0
+
+
+`endif
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz.s
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/reg_macz.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,37 @@
+
+reg_macz: file format elf32-tradlittlemips
+
+Disassembly of section .text:
+
+00000000 <here-0x3c>:
+ 0: 3c011234 lui at,0x1234
+ 4: 34215678 ori at,at,0x5678
+ 8: 3c022345 lui v0,0x2345
+ c: 34426789 ori v0,v0,0x6789
+ 10: 3c03ffff lui v1,0xffff
+ 14: 00012020 add a0,zero,at
+ 18: 00832024 and a0,a0,v1
+ 1c: 00022c02 srl a1,v0,0x10
+ 20: 00853021 addu a2,a0,a1
+ 24: 24010010 li at,16
+ 28: 2402000f li v0,15
+ 2c: 00221821 addu v1,at,v0
+ 30: 00000000 nop
+ 34: 00000000 nop
+ 38: 00000000 nop
+
+0000003c <here>:
+ 3c: 0800000f j 3c <here>
+ 40: 00000000 nop
+ 44: 00000000 nop
+ 48: 00000000 nop
+ 4c: 00000000 nop
+Disassembly of section .reginfo:
+
+00000000 <.reginfo>:
+ 0: 0000007e 0x7e
+ 4: 00000000 nop
+ 8: 00000000 nop
+ c: 00000000 nop
+ 10: 00000000 nop
+ 14: 00000000 nop
Modified: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.c
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.c
2007-10-26 22:21:30 UTC (rev 6709)
@@ -4,7 +4,7 @@
int main()
{
int i;//,j;
-
+
short a[10];//,num,tmp;
//num = 10;
//char str[30] = "";
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.s
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sort.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,313 @@
+
+strip_sort: file format elf32-tradlittlemips
+
+Disassembly of section .init:
+
+00000000 <.init>:
+ 0: 3c190000 lui t9,0x0
+ 4: 27390050 addiu t9,t9,80
+ 8: 3c1d0800 lui sp,0x800
+ c: 0320f809 jalr t9
+ 10: 37bd8000 ori sp,sp,0x8000
+ 14: 00000000 nop
+ 18: 08000006 j 0x18
+ 1c: 00000000 nop
+ 20: 00000000 nop
+Disassembly of section .interrupt:
+
+00000024 <.interrupt>:
+ 24: 27bdfffc addiu sp,sp,-4
+ 28: afa80000 sw t0,0(sp)
+ 2c: 2408000f li t0,15
+ 30: 00000000 nop
+ 34: 40888800 mtc0 t0,$17
+ 38: 00000000 nop
+ 3c: 8fa80000 lw t0,0(sp)
+ 40: 27bd0004 addiu sp,sp,4
+ 44: 42000018 c0 0x18
+ 48: 00000000 nop
+ 4c: 00000000 nop
+Disassembly of section .text:
+
+00000050 <.text>:
+ 50: 3c1c0800 lui gp,0x800
+ 54: 279cffb0 addiu gp,gp,-80
+ 58: 0399e021 addu gp,gp,t9
+ 5c: 27bdffb0 addiu sp,sp,-80
+ 60: afbf004c sw ra,76(sp)
+ 64: afb60048 sw s6,72(sp)
+ 68: afb50044 sw s5,68(sp)
+ 6c: afb40040 sw s4,64(sp)
+ 70: afb3003c sw s3,60(sp)
+ 74: afb20038 sw s2,56(sp)
+ 78: afb10034 sw s1,52(sp)
+ 7c: afb00030 sw s0,48(sp)
+ 80: afbc0010 sw gp,16(sp)
+ 84: 240200f0 li v0,240
+ 88: 240300f1 li v1,241
+ 8c: a7a20018 sh v0,24(sp)
+ 90: a7a3001a sh v1,26(sp)
+ 94: 240200f2 li v0,242
+ 98: 240300f3 li v1,243
+ 9c: a7a2001c sh v0,28(sp)
+ a0: a7a3001e sh v1,30(sp)
+ a4: 240200f4 li v0,244
+ a8: 240300f5 li v1,245
+ ac: a7a20020 sh v0,32(sp)
+ b0: a7a30022 sh v1,34(sp)
+ b4: 240200f6 li v0,246
+ b8: 240300f7 li v1,247
+ bc: 27b60018 addiu s6,sp,24
+ c0: a7a20024 sh v0,36(sp)
+ c4: a7a30026 sh v1,38(sp)
+ c8: 240200f8 li v0,248
+ cc: 240300f9 li v1,249
+ d0: 8f940008 lw s4,8(gp)
+ d4: 8f930008 lw s3,8(gp)
+ d8: 8f920008 lw s2,8(gp)
+ dc: a7a20028 sh v0,40(sp)
+ e0: a7a3002a sh v1,42(sp)
+ e4: 00008021 move s0,zero
+ e8: 02c08821 move s1,s6
+ ec: 8f990020 lw t9,32(gp)
+ f0: 00000000 nop
+ f4: 0320f809 jalr t9
+ f8: 2684002c addiu a0,s4,44
+ fc: 8fbc0010 lw gp,16(sp)
+ 100: 02002021 move a0,s0
+ 104: 8f990024 lw t9,36(gp)
+ 108: 00000000 nop
+ 10c: 0320f809 jalr t9
+ 110: 26100001 addiu s0,s0,1
+ 114: 8fbc0010 lw gp,16(sp)
+ 118: 00000000 nop
+ 11c: 8f990020 lw t9,32(gp)
+ 120: 00000000 nop
+ 124: 0320f809 jalr t9
+ 128: 26640030 addiu a0,s3,48
+ 12c: 8fbc0010 lw gp,16(sp)
+ 130: 86240000 lh a0,0(s1)
+ 134: 8f990028 lw t9,40(gp)
+ 138: 00000000 nop
+ 13c: 0320f809 jalr t9
+ 140: 24050010 li a1,16
+ 144: 8fbc0010 lw gp,16(sp)
+ 148: 26440034 addiu a0,s2,52
+ 14c: 8f990020 lw t9,32(gp)
+ 150: 00000000 nop
+ 154: 0320f809 jalr t9
+ 158: 26310002 addiu s1,s1,2
+ 15c: 2a02000a slti v0,s0,10
+ 160: 8fbc0010 lw gp,16(sp)
+ 164: 1440ffe1 bnez v0,0xec
+ 168: 00000000 nop
+ 16c: 8f950008 lw s5,8(gp)
+ 170: 8f990020 lw t9,32(gp)
+ 174: 00000000 nop
+ 178: 0320f809 jalr t9
+ 17c: 26a40038 addiu a0,s5,56
+ 180: 8fbc0010 lw gp,16(sp)
+ 184: 27a40018 addiu a0,sp,24
+ 188: 8f99001c lw t9,28(gp)
+ 18c: 00000000 nop
+ 190: 0320f809 jalr t9
+ 194: 2405000a li a1,10
+ 198: 8fbc0010 lw gp,16(sp)
+ 19c: 02c08821 move s1,s6
+ 1a0: 00008021 move s0,zero
+ 1a4: 8f990020 lw t9,32(gp)
+ 1a8: 00000000 nop
+ 1ac: 0320f809 jalr t9
+ 1b0: 2684002c addiu a0,s4,44
+ 1b4: 8fbc0010 lw gp,16(sp)
+ 1b8: 02002021 move a0,s0
+ 1bc: 8f990024 lw t9,36(gp)
+ 1c0: 00000000 nop
+ 1c4: 0320f809 jalr t9
+ 1c8: 26100001 addiu s0,s0,1
+ 1cc: 8fbc0010 lw gp,16(sp)
+ 1d0: 00000000 nop
+ 1d4: 8f990020 lw t9,32(gp)
+ 1d8: 00000000 nop
+ 1dc: 0320f809 jalr t9
+ 1e0: 26640030 addiu a0,s3,48
+ 1e4: 8fbc0010 lw gp,16(sp)
+ 1e8: 86240000 lh a0,0(s1)
+ 1ec: 8f990028 lw t9,40(gp)
+ 1f0: 00000000 nop
+ 1f4: 0320f809 jalr t9
+ 1f8: 24050010 li a1,16
+ 1fc: 8fbc0010 lw gp,16(sp)
+ 200: 26440034 addiu a0,s2,52
+ 204: 8f990020 lw t9,32(gp)
+ 208: 00000000 nop
+ 20c: 0320f809 jalr t9
+ 210: 26310002 addiu s1,s1,2
+ 214: 2a02000a slti v0,s0,10
+ 218: 8fbc0010 lw gp,16(sp)
+ 21c: 1440ffe1 bnez v0,0x1a4
+ 220: 00000000 nop
+ 224: 8f990020 lw t9,32(gp)
+ 228: 00000000 nop
+ 22c: 0320f809 jalr t9
+ 230: 26a40038 addiu a0,s5,56
+ 234: 87a20018 lh v0,24(sp)
+ 238: 8fbc0010 lw gp,16(sp)
+ 23c: 8fbf004c lw ra,76(sp)
+ 240: 8fb60048 lw s6,72(sp)
+ 244: 8fb50044 lw s5,68(sp)
+ 248: 8fb40040 lw s4,64(sp)
+ 24c: 8fb3003c lw s3,60(sp)
+ 250: 8fb20038 lw s2,56(sp)
+ 254: 8fb10034 lw s1,52(sp)
+ 258: 8fb00030 lw s0,48(sp)
+ 25c: 03e00008 jr ra
+ 260: 27bd0050 addiu sp,sp,80
+ 264: 00000000 nop
+ 268: 00000000 nop
+ 26c: 00000000 nop
+ 270: 8c820000 lw v0,0(a0)
+ 274: 03e00008 jr ra
+ 278: 00000000 nop
+ 27c: 03e00008 jr ra
+ 280: aca40000 sw a0,0(a1)
+ 284: 00042600 sll a0,a0,0x18
+ 288: 00042603 sra a0,a0,0x18
+ 28c: 24030004 li v1,4
+ 290: 8c620000 lw v0,0(v1)
+ 294: 00000000 nop
+ 298: 1440fffd bnez v0,0x290
+ 29c: 2402000c li v0,12
+ 2a0: ac440000 sw a0,0(v0)
+ 2a4: 03e00008 jr ra
+ 2a8: 00000000 nop
+ 2ac: 80820000 lb v0,0(a0)
+ 2b0: 00000000 nop
+ 2b4: 1040000e beqz v0,0x2f0
+ 2b8: 00000000 nop
+ 2bc: 00401821 move v1,v0
+ 2c0: 24050004 li a1,4
+ 2c4: 2406000c li a2,12
+ 2c8: 8ca20000 lw v0,0(a1)
+ 2cc: 00000000 nop
+ 2d0: 1440fffd bnez v0,0x2c8
+ 2d4: 00000000 nop
+ 2d8: acc30000 sw v1,0(a2)
+ 2dc: 24840001 addiu a0,a0,1
+ 2e0: 80830000 lb v1,0(a0)
+ 2e4: 00000000 nop
+ 2e8: 1460fff7 bnez v1,0x2c8
+ 2ec: 00000000 nop
+ 2f0: 03e00008 jr ra
+ 2f4: 00000000 nop
+ 2f8: 24a5fffc addiu a1,a1,-4
+ 2fc: 04a00010 bltz a1,0x340
+ 300: 00a41007 srav v0,a0,a1
+ 304: 2407000c li a3,12
+ 308: 3046000f andi a2,v0,0xf
+ 30c: 28c3000a slti v1,a2,10
+ 310: 1060000d beqz v1,0x348
+ 314: 24c20057 addiu v0,a2,87
+ 318: 24c60030 addiu a2,a2,48
+ 31c: 24030004 li v1,4
+ 320: 8c620000 lw v0,0(v1)
+ 324: 00000000 nop
+ 328: 1440fffd bnez v0,0x320
+ 32c: 00000000 nop
+ 330: ace60000 sw a2,0(a3)
+ 334: 24a5fffc addiu a1,a1,-4
+ 338: 04a1fff3 bgez a1,0x308
+ 33c: 00a41007 srav v0,a0,a1
+ 340: 03e00008 jr ra
+ 344: 00000000 nop
+ 348: 00023600 sll a2,v0,0x18
+ 34c: 1000fff3 b 0x31c
+ 350: 00063603 sra a2,a2,0x18
+ 354: 1480000a bnez a0,0x380
+ 358: 3c026666 lui v0,0x6666
+ 35c: 24040030 li a0,48
+ 360: 24030004 li v1,4
+ 364: 8c620000 lw v0,0(v1)
+ 368: 00000000 nop
+ 36c: 1440fffd bnez v0,0x364
+ 370: 2402000c li v0,12
+ 374: ac440000 sw a0,0(v0)
+ 378: 03e00008 jr ra
+ 37c: 00000000 nop
+ 380: 34486667 ori t0,v0,0x6667
+ 384: 24050004 li a1,4
+ 388: 2407000c li a3,12
+ 38c: 00880018 mult a0,t0
+ 390: 000437c3 sra a2,a0,0x1f
+ 394: 00001810 mfhi v1
+ 398: 00031883 sra v1,v1,0x2
+ 39c: 00661823 subu v1,v1,a2
+ 3a0: 00031080 sll v0,v1,0x2
+ 3a4: 00431021 addu v0,v0,v1
+ 3a8: 00021040 sll v0,v0,0x1
+ 3ac: 00821023 subu v0,a0,v0
+ 3b0: 24420030 addiu v0,v0,48
+ 3b4: 00021e00 sll v1,v0,0x18
+ 3b8: 00031e03 sra v1,v1,0x18
+ 3bc: 8ca20000 lw v0,0(a1)
+ 3c0: 00000000 nop
+ 3c4: 1440fffd bnez v0,0x3bc
+ 3c8: 00000000 nop
+ 3cc: ace30000 sw v1,0(a3)
+ 3d0: 00880018 mult a0,t0
+ 3d4: 00001010 mfhi v0
+ 3d8: 00021083 sra v0,v0,0x2
+ 3dc: 00462023 subu a0,v0,a2
+ 3e0: 1480ffea bnez a0,0x38c
+ 3e4: 00000000 nop
+ 3e8: 03e00008 jr ra
+ 3ec: 00000000 nop
+ 3f0: 18a00018 blez a1,0x454
+ 3f4: 00001821 move v1,zero
+ 3f8: 246b0001 addiu t3,v1,1
+ 3fc: 0165102a slt v0,t3,a1
+ 400: 10400012 beqz v0,0x44c
+ 404: 01603821 move a3,t3
+ 408: 00031040 sll v0,v1,0x1
+ 40c: 000b1840 sll v1,t3,0x1
+ 410: 00445021 addu t2,v0,a0
+ 414: 00641821 addu v1,v1,a0
+ 418: 94680000 lhu t0,0(v1)
+ 41c: 85460000 lh a2,0(t2)
+ 420: 00081400 sll v0,t0,0x10
+ 424: 00021403 sra v0,v0,0x10
+ 428: 24e70001 addiu a3,a3,1
+ 42c: 00c2102a slt v0,a2,v0
+ 430: 10400003 beqz v0,0x440
+ 434: 00e5482a slt t1,a3,a1
+ 438: a5480000 sh t0,0(t2)
+ 43c: a4660000 sh a2,0(v1)
+ 440: 1520fff5 bnez t1,0x418
+ 444: 24630002 addiu v1,v1,2
+ 448: 0165102a slt v0,t3,a1
+ 44c: 1440ffea bnez v0,0x3f8
+ 450: 01601821 move v1,t3
+ 454: 03e00008 jr ra
+ 458: 00000000 nop
+ 45c: 00000000 nop
+Disassembly of section .got:
+
+08000000 <.got>:
+ 8000000: 00000000 nop
+ 8000004: 80000000 lb zero,0(zero)
+ 8000008: 08000000 j 0x0
+ 800000c: 00000000 nop
+ 8000010: 00000000 nop
+ 8000014: 00000000 nop
+ 8000018: 00000000 nop
+ 800001c: 000003f0 0x3f0
+ 8000020: 000002ac 0x2ac
+ 8000024: 00000354 0x354
+ 8000028: 000002f8 0x2f8
+Disassembly of section .rodata:
+
+0800002c <.rodata>:
+ 800002c: 00005b61 0x5b61
+ 8000030: 00003d5d 0x3d5d
+ 8000034: 0000000a 0xa
+ 8000038: 000a0a0a 0xa0a0a
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sortlib.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/sortlib.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_sort
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_sort
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code_sw
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_test_code_sw
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_timtest
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/strip_timtest
___________________________________________________________________
Name: svn:executable
+ *
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.asm
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.asm
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.asm
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,1027 @@
+##################################################################
+# TITLE: Opcode Tester
+# DESCRIPTION:
+# This test assumes that address 0x00800010 is the UART write register
+# Successful tests will print out "A" or "AB" or "ABC" or ....
+# Missing letters or letters out of order indicate a failure.
+##################################################################
+
+.text 0x20
+.set noreorder
+
+ #These four instructions must be the first instructions
+ #convert.exe will correctly initialize $gp
+ lui $gp,0
+ ori $gp,$gp,0
+ #convert.exe will set $4=.sbss_start $5=.bss_end
+ lui $4,0
+ ori $4,$4,0
+ lui $5,0
+ ori $5,$5,0
+ lui $sp,0x0080
+ ori $sp,$sp,0x0000
+
+ lui $20,0x0080
+ ori $20,$20,0x0010 #serial port write address
+ ori $21,$0,'\n' #<CR> letter
+ ori $22,$0,'X' #'X' letter
+ ori $23,$0,'\r'
+ lui $24,0x0080
+ ori $24,$24,0x0004 #temp memory
+
+ ######################################
+ #Move Instructions
+ ######################################
+ ori $2,$0,'M'
+ sb $2,0($20)
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,'v'
+ sb $2,0($20)
+ ori $2,$0,'e'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: MFHI
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $2,$0,65
+ mthi $2
+ mfhi $3
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: MFLO
+ ori $2,$0,'b'
+ sb $2,0($20)
+ ori $2,$0,65
+ mtlo $2
+ mflo $3
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: MTHI
+ ori $2,$0,'c'
+ sb $2,0($20)
+ ori $2,$0,65
+ mthi $2
+ mfhi $3
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: MTLO
+ ori $2,$0,'d'
+ sb $2,0($20)
+ ori $2,$0,65
+ mtlo $2
+ mflo $3
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+ ######################################
+ #Shift Instructions
+ ######################################
+ ori $2,$0,'S'
+ sb $2,0($20)
+ ori $2,$0,'h'
+ sb $2,0($20)
+ ori $2,$0,'i'
+ sb $2,0($20)
+ ori $2,$0,'f'
+ sb $2,0($20)
+ ori $2,$0,'t'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: SLL
+ ori $2,$0,'a'
+ sb $2,0($20)
+ li $2,0x40414243
+ sll $3,$2,8
+ srl $3,$3,24
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: SLLV
+ ori $2,$0,'b'
+ sb $2,0($20)
+ li $2,0x40414243
+ ori $3,$0,8
+ sllv $3,$2,$3
+ srl $3,$3,24
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: SRA
+ ori $2,$0,'c'
+ sb $2,0($20)
+ li $2,0x40414243
+ sra $3,$2,16
+ sb $3,0($20)
+ li $2,0x84000000
+ sra $3,$2,25
+ sub $3,$3,0x80
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: SRAV
+ ori $2,$0,'d'
+ sb $2,0($20)
+ li $2,0x40414243
+ ori $3,$0,16
+ srav $3,$2,$3
+ sb $3,0($20)
+ ori $3,$0,25
+ li $2,0x84000000
+ srav $3,$2,$3
+ sub $3,$3,0x80
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: SRL
+ ori $2,$0,'e'
+ sb $2,0($20)
+ li $2,0x40414243
+ srl $3,$2,16
+ sb $3,0($20)
+ li $2,0x84000000
+ srl $3,$2,25
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: SRLV
+ ori $2,$0,'f'
+ sb $2,0($20)
+ li $2,0x40414243
+ ori $3,$0,16
+ srlv $4,$2,$3
+ sb $4,0($20)
+ ori $3,$0,25
+ li $2,0x84000000
+ srlv $3,$2,$3
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+ ori $2,$0,'D'
+ sb $2,0($20)
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,'n'
+ sb $2,0($20)
+ ori $2,$0,'e'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+ ######################################
+ #Arithmetic Instructions
+ ######################################
+ ori $2,$0,'A'
+ sb $2,0($20)
+ ori $2,$0,'r'
+ sb $2,0($20)
+ ori $2,$0,'i'
+ sb $2,0($20)
+ ori $2,$0,'t'
+ sb $2,0($20)
+ ori $2,$0,'h'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: ADD
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $3,$0,5
+ ori $4,$0,60
+ add $2,$3,$4
+ sb $2,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: ADDI
+ ori $2,$0,'b'
+ sb $2,0($20)
+ ori $4,$0,60
+ addi $2,$4,5
+ sb $2,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: ADDIU
+ ori $2,$0,'c'
+ sb $2,0($20)
+ ori $4,$0,50
+ addiu $5,$4,15
+ sb $5,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: ADDU
+ ori $2,$0,'d'
+ sb $2,0($20)
+ ori $3,$0,5
+ ori $4,$0,60
+ add $2,$3,$4
+ sb $2,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: DIV
+ ori $2,$0,'e'
+ sb $2,0($20)
+ ori $2,$0,65*117+41
+ ori $3,$0,117
+ div $2,$3
+ nop
+ mflo $4
+ sb $4,0($20) #A
+ mfhi $4
+ addi $4,$4,66-41
+ sb $4,0($20) #B
+ li $2,-67*19
+ ori $3,$0,19
+ div $2,$3
+ nop
+ mflo $4
+ sub $4,$0,$4
+ sb $4,0($20) #C
+ ori $2,$0,68*23
+ li $3,-23
+ div $2,$3
+ nop
+ mflo $4
+ sub $4,$0,$4
+ sb $4,0($20) #D
+ li $2,-69*13
+ li $3,-13
+ div $2,$3
+ mflo $4
+ sb $4,0($20) #E
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: DIVU
+ ori $2,$0,'f'
+ sb $2,0($20)
+ ori $2,$0,65*13
+ ori $3,$0,13
+ divu $2,$3
+ nop
+ mflo $4
+ sb $4,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #g: MULT
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $2,$0,5
+ ori $3,$0,13
+ mult $2,$3
+ nop
+ mflo $4
+ sb $4,0($20) #A
+ li $2,-5
+ ori $3,$0,13
+ mult $2,$3
+ mfhi $5
+ mflo $4
+ sub $4,$0,$4
+ addu $4,$4,$5
+ addi $4,$4,2
+ sb $4,0($20) #B
+ ori $2,$0,5
+ li $3,-13
+ mult $2,$3
+ mfhi $5
+ mflo $4
+ sub $4,$0,$4
+ addu $4,$4,$5
+ addi $4,$4,3
+ sb $4,0($20) #C
+ li $2,-5
+ li $3,-13
+ mult $2,$3
+ mfhi $5
+ mflo $4
+ addu $4,$4,$5
+ addi $4,$4,3
+ sb $4,0($20) #D
+ lui $4,0xfe98
+ ori $4,$4,0x62e5
+ lui $5,0x6
+ ori $5,0x8db8
+ mult $4,$5
+ mfhi $6
+ addiu $7,$6,2356+1+'E' #E
+ sb $7,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #h: MULTU
+ ori $2,$0,'h'
+ sb $2,0($20)
+ ori $2,$0,5
+ ori $3,$0,13
+ multu $2,$3
+ nop
+ mflo $4
+ sb $4,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #i: SLT
+ ori $2,$0,'i'
+ sb $2,0($20)
+ ori $2,$0,10
+ ori $3,$0,12
+ slt $4,$2,$3
+ addi $5,$4,64
+ sb $5,0($20) #A
+ slt $4,$3,$2
+ addi $5,$4,66
+ sb $5,0($20) #B
+ li $2,0xfffffff0
+ slt $4,$2,$3
+ addi $5,$4,66
+ sb $5,0($20) #C
+ slt $4,$3,$2
+ addi $5,$4,68
+ sb $5,0($20) #D
+ li $3,0xffffffff
+ slt $4,$2,$3
+ addi $5,$4,68
+ sb $5,0($20) #E
+ slt $4,$3,$2
+ addi $5,$4,70
+ sb $5,0($20) #F
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #j: SLTI
+ ori $2,$0,'j'
+ sb $2,0($20)
+ ori $2,$0,10
+ slti $4,$2,12
+ addi $5,$4,64
+ sb $5,0($20) #A
+ slti $4,$2,8
+ addi $5,$4,66
+ sb $5,0($20) #B
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #k: SLTIU
+ ori $2,$0,'k'
+ sb $2,0($20)
+ ori $2,$0,10
+ sltiu $4,$2,12
+ addi $5,$4,64
+ sb $5,0($20) #A
+ sltiu $4,$2,8
+ addi $5,$4,66
+ sb $5,0($20) #B
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #l: SLTU
+ ori $2,$0,'l'
+ sb $2,0($20)
+ ori $2,$0,10
+ ori $3,$0,12
+ slt $4,$2,$3
+ addi $5,$4,64
+ sb $5,0($20) #A
+ slt $4,$3,$2
+ addi $5,$4,66
+ sb $5,0($20) #B
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #m: SUB
+ ori $2,$0,'m'
+ sb $2,0($20)
+ ori $3,$0,70
+ ori $4,$0,5
+ sub $2,$3,$4
+ sb $2,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #n: SUBU
+ ori $2,$0,'n'
+ sb $2,0($20)
+ ori $3,$0,70
+ ori $4,$0,5
+ sub $2,$3,$4
+ sb $2,0($20) #A
+ sb $23,0($20)
+ sb $21,0($20)
+
+ ######################################
+ #Branch and Jump Instructions
+ ######################################
+ ori $2,$0,'B'
+ sb $2,0($20)
+ ori $2,$0,'r'
+ sb $2,0($20)
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $2,$0,'n'
+ sb $2,0($20)
+ ori $2,$0,'c'
+ sb $2,0($20)
+ ori $2,$0,'h'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: B
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ b $B1
+ sb $10,0($20)
+ sb $22,0($20)
+$B1:
+ sb $11,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: BAL
+ ori $2,$0,'b'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $15,$0,'X'
+ bal $BAL1
+ sb $10,0($20)
+ sb $13,0($20)
+ b $BAL2
+ sb $14,0($20)
+ sb $15,0($20)
+$BAL1:
+ sb $11,0($20)
+ jr $31
+ sb $12,0($20)
+ sb $22,0($20)
+$BAL2:
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: BEQ
+ ori $2,$0,'c'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $2,$0,100
+ ori $3,$0,123
+ ori $4,$0,123
+ beq $2,$3,$BEQ1
+ sb $10,0($20)
+ sb $11,0($20)
+ beq $3,$4,$BEQ1
+ sb $12,0($20)
+ sb $22,0($20)
+$BEQ1:
+ sb $13,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: BGEZ
+ ori $2,$0,'d'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ or $15,$0,'X'
+ ori $2,$0,100
+ li $3,0xffff1234
+ ori $4,$0,123
+ bgez $3,$BGEZ1
+ sb $10,0($20)
+ sb $11,0($20)
+ bgez $2,$BGEZ1
+ sb $12,0($20)
+ sb $22,0($20)
+$BGEZ1:
+ bgez $0,$BGEZ2
+ nop
+ sb $15,0($20)
+$BGEZ2:
+ sb $13,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: BGEZAL
+ ori $2,$0,'e'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $15,$0,'X'
+ li $3,0xffff1234
+ bgezal $3,$BGEZAL1
+ nop
+ sb $10,0($20)
+ bgezal $0,$BGEZAL1
+ nop
+ sb $13,0($20)
+ b $BGEZAL2
+ sb $14,0($20)
+ sb $15,0($20)
+$BGEZAL1:
+ sb $11,0($20)
+ jr $31
+ sb $12,0($20)
+ sb $22,0($20)
+$BGEZAL2:
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: BGTZ
+ ori $2,$0,'f'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $2,$0,100
+ li $3,0xffff1234
+ bgtz $3,$BGTZ1
+ sb $10,0($20)
+ sb $11,0($20)
+ bgtz $2,$BGTZ1
+ sb $12,0($20)
+ sb $22,0($20)
+$BGTZ1:
+ sb $13,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #g: BLEZ
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $2,$0,100
+ li $3,0xffff1234
+ blez $2,$BLEZ1
+ sb $10,0($20)
+ sb $11,0($20)
+ blez $3,$BLEZ1
+ sb $12,0($20)
+ sb $22,0($20)
+$BLEZ1:
+ blez $0,$BLEZ2
+ nop
+ sb $22,0($20)
+$BLEZ2:
+ sb $13,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #h: BLTZ
+ ori $2,$0,'h'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $2,$0,100
+ li $3,0xffff1234
+ ori $4,$0,0
+ bltz $2,$BLTZ1
+ sb $10,0($20)
+ sb $11,0($20)
+ bltz $3,$BLTZ1
+ sb $12,0($20)
+ sb $22,0($20)
+$BLTZ1:
+ bltz $4,$BLTZ2
+ nop
+ sb $13,0($20)
+$BLTZ2:
+ sb $14,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #i: BLTZAL
+ ori $2,$0,'i'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $15,$0,'X'
+ li $3,0xffff1234
+ bltzal $0,$BLTZAL1
+ nop
+ sb $10,0($20)
+ bltzal $3,$BLTZAL1
+ nop
+ sb $13,0($20)
+ b $BLTZAL2
+ sb $14,0($20)
+ sb $15,0($20)
+$BLTZAL1:
+ sb $11,0($20)
+ jr $31
+ sb $12,0($20)
+ sb $22,0($20)
+$BLTZAL2:
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #j: BNE
+ ori $2,$0,'j'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $2,$0,100
+ ori $3,$0,123
+ ori $4,$0,123
+ bne $3,$4,$BNE1
+ sb $10,0($20)
+ sb $11,0($20)
+ bne $2,$3,$BNE1
+ sb $12,0($20)
+ sb $22,0($20)
+$BNE1:
+ sb $13,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #k: J
+ ori $2,$0,'k'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $15,$0,'X'
+ j $J1
+ sb $10,0($20)
+ sb $15,0($20)
+$J1:
+ sb $11,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #l: JAL
+ ori $2,$0,'l'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $15,$0,'X'
+ jal $JAL1
+ sb $10,0($20)
+ sb $13,0($20)
+ b $JAL2
+ sb $14,0($20)
+ sb $15,0($20)
+$JAL1:
+ sb $11,0($20)
+ jr $31
+ sb $12,0($20)
+ sb $22,0($20)
+$JAL2:
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #m: JALR
+ ori $2,$0,'m'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $12,$0,'C'
+ ori $13,$0,'D'
+ ori $14,$0,'E'
+ ori $15,$0,'X'
+ la $3,$JALR1
+ jalr $3
+ sb $10,0($20)
+ sb $13,0($20)
+ b $JALR2
+ sb $14,0($20)
+ sb $15,0($20)
+$JALR1:
+ sb $11,0($20)
+ jr $31
+ sb $12,0($20)
+ sb $22,0($20)
+$JALR2:
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #n: JR
+ ori $2,$0,'n'
+ sb $2,0($20)
+ ori $10,$0,'A'
+ ori $11,$0,'B'
+ ori $15,$0,'X'
+ la $3,$JR1
+ jr $3
+ sb $10,0($20)
+ sb $15,0($20)
+$JR1:
+ sb $11,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #o: NOP
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,65
+ nop
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+ ######################################
+ #Load, Store, and Memory Control Instructions
+ ######################################
+ ori $2,$0,'L'
+ sb $2,0($20)
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $2,$0,'d'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: LB
+ ori $2,$0,'a'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: LBU
+ ori $2,$0,'b'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: LH
+ ori $2,$0,'c'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x00410042
+ sw $3,16($2)
+ lh $4,16($2)
+ sb $4,0($20)
+ lh $2,18($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: LHU
+ ori $2,$0,'d'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x00410042
+ sw $3,16($2)
+ lh $4,16($2)
+ sb $4,0($20)
+ lh $2,18($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: LW
+ ori $2,$0,'e'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,'A'
+ sw $3,16($2)
+ ori $3,$0,0
+ lw $2,16($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: LWL & LWR
+ ori $2,$0,'f'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,'A'
+ sw $3,16($2)
+ ori $3,$0,0
+ lwl $2,16($2)
+ lwr $2,16($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #g: SB
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $2,$0,'A'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #h: SH
+ ori $2,$0,'h'
+ sb $2,0($20)
+ or $4,$0,$24
+ ori $2,$0,0x4142
+ sh $2,16($4)
+ lb $3,16($4)
+ sb $3,0($20)
+ lb $2,17($4)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #i: SW
+ ori $2,$0,'i'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #j: SWL & SWR
+ ori $2,$0,'j'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ swl $3,16($2)
+ swr $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+ ######################################
+ #Logical Instructions
+ ######################################
+ ori $2,$0,'L'
+ sb $2,0($20)
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $2,$0,'i'
+ sb $2,0($20)
+ ori $2,$0,'c'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: AND
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $2,$0,0x0741
+ ori $3,$0,0x60f3
+ and $4,$2,$3
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #b: ANDI
+ ori $2,$0,'b'
+ sb $2,0($20)
+ ori $2,$0,0x0741
+ andi $4,$2,0x60f3
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #c: LUI
+ ori $2,$0,'c'
+ sb $2,0($20)
+ lui $2,0x41
+ srl $3,$2,16
+ sb $3,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #d: NOR
+ ori $2,$0,'d'
+ sb $2,0($20)
+ li $2,0xf0fff08e
+ li $3,0x0f0f0f30
+ nor $4,$2,$3
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: OR
+ ori $2,$0,'e'
+ sb $2,0($20)
+ ori $2,$0,0x40
+ ori $3,$0,0x01
+ or $4,$2,$3
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: ORI
+ ori $2,$0,'f'
+ sb $2,0($20)
+ ori $2,$0,0x40
+ ori $4,$2,0x01
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #g: XOR
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $2,$0,0xf043
+ ori $3,$0,0xf002
+ xor $4,$2,$3
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #h: XORI
+ ori $2,$0,'h'
+ sb $2,0($20)
+ ori $2,$0,0xf043
+ xor $4,$2,0xf002
+ sb $4,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+
+$DONE:
+ j $DONE
+ nop
+
+.set reorder
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Modified:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.s
2007-10-26 22:10:05 UTC (rev 6708)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -1,1027 +1,910 @@
-##################################################################
-# TITLE: Opcode Tester
-# DESCRIPTION:
-# This test assumes that address 0x00800010 is the UART write register
-# Successful tests will print out "A" or "AB" or "ABC" or ....
-# Missing letters or letters out of order indicate a failure.
-##################################################################
-
-.text 0x20
-.set noreorder
-
- #These four instructions must be the first instructions
- #convert.exe will correctly initialize $gp
- lui $gp,0
- ori $gp,$gp,0
- #convert.exe will set $4=.sbss_start $5=.bss_end
- lui $4,0
- ori $4,$4,0
- lui $5,0
- ori $5,$5,0
- lui $sp,0x0080
- ori $sp,$sp,0x0000
-
- lui $20,0x0080
- ori $20,$20,0x0010 #serial port write address
- ori $21,$0,'\n' #<CR> letter
- ori $22,$0,'X' #'X' letter
- ori $23,$0,'\r'
- lui $24,0x0080
- ori $24,$24,0x0004 #temp memory
-
- ######################################
- #Move Instructions
- ######################################
- ori $2,$0,'M'
- sb $2,0($20)
- ori $2,$0,'o'
- sb $2,0($20)
- ori $2,$0,'v'
- sb $2,0($20)
- ori $2,$0,'e'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: MFHI
- ori $2,$0,'a'
- sb $2,0($20)
- ori $2,$0,65
- mthi $2
- mfhi $3
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #b: MFLO
- ori $2,$0,'b'
- sb $2,0($20)
- ori $2,$0,65
- mtlo $2
- mflo $3
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #c: MTHI
- ori $2,$0,'c'
- sb $2,0($20)
- ori $2,$0,65
- mthi $2
- mfhi $3
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #d: MTLO
- ori $2,$0,'d'
- sb $2,0($20)
- ori $2,$0,65
- mtlo $2
- mflo $3
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
- ######################################
- #Shift Instructions
- ######################################
- ori $2,$0,'S'
- sb $2,0($20)
- ori $2,$0,'h'
- sb $2,0($20)
- ori $2,$0,'i'
- sb $2,0($20)
- ori $2,$0,'f'
- sb $2,0($20)
- ori $2,$0,'t'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: SLL
- ori $2,$0,'a'
- sb $2,0($20)
- li $2,0x40414243
- sll $3,$2,8
- srl $3,$3,24
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #b: SLLV
- ori $2,$0,'b'
- sb $2,0($20)
- li $2,0x40414243
- ori $3,$0,8
- sllv $3,$2,$3
- srl $3,$3,24
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #c: SRA
- ori $2,$0,'c'
- sb $2,0($20)
- li $2,0x40414243
- sra $3,$2,16
- sb $3,0($20)
- li $2,0x84000000
- sra $3,$2,25
- sub $3,$3,0x80
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #d: SRAV
- ori $2,$0,'d'
- sb $2,0($20)
- li $2,0x40414243
- ori $3,$0,16
- srav $3,$2,$3
- sb $3,0($20)
- ori $3,$0,25
- li $2,0x84000000
- srav $3,$2,$3
- sub $3,$3,0x80
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #e: SRL
- ori $2,$0,'e'
- sb $2,0($20)
- li $2,0x40414243
- srl $3,$2,16
- sb $3,0($20)
- li $2,0x84000000
- srl $3,$2,25
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #f: SRLV
- ori $2,$0,'f'
- sb $2,0($20)
- li $2,0x40414243
- ori $3,$0,16
- srlv $4,$2,$3
- sb $4,0($20)
- ori $3,$0,25
- li $2,0x84000000
- srlv $3,$2,$3
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
- ori $2,$0,'D'
- sb $2,0($20)
- ori $2,$0,'o'
- sb $2,0($20)
- ori $2,$0,'n'
- sb $2,0($20)
- ori $2,$0,'e'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
- ######################################
- #Arithmetic Instructions
- ######################################
- ori $2,$0,'A'
- sb $2,0($20)
- ori $2,$0,'r'
- sb $2,0($20)
- ori $2,$0,'i'
- sb $2,0($20)
- ori $2,$0,'t'
- sb $2,0($20)
- ori $2,$0,'h'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: ADD
- ori $2,$0,'a'
- sb $2,0($20)
- ori $3,$0,5
- ori $4,$0,60
- add $2,$3,$4
- sb $2,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #b: ADDI
- ori $2,$0,'b'
- sb $2,0($20)
- ori $4,$0,60
- addi $2,$4,5
- sb $2,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #c: ADDIU
- ori $2,$0,'c'
- sb $2,0($20)
- ori $4,$0,50
- addiu $5,$4,15
- sb $5,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #d: ADDU
- ori $2,$0,'d'
- sb $2,0($20)
- ori $3,$0,5
- ori $4,$0,60
- add $2,$3,$4
- sb $2,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #e: DIV
- ori $2,$0,'e'
- sb $2,0($20)
- ori $2,$0,65*117+41
- ori $3,$0,117
- div $2,$3
- nop
- mflo $4
- sb $4,0($20) #A
- mfhi $4
- addi $4,$4,66-41
- sb $4,0($20) #B
- li $2,-67*19
- ori $3,$0,19
- div $2,$3
- nop
- mflo $4
- sub $4,$0,$4
- sb $4,0($20) #C
- ori $2,$0,68*23
- li $3,-23
- div $2,$3
- nop
- mflo $4
- sub $4,$0,$4
- sb $4,0($20) #D
- li $2,-69*13
- li $3,-13
- div $2,$3
- mflo $4
- sb $4,0($20) #E
- sb $23,0($20)
- sb $21,0($20)
-
- #f: DIVU
- ori $2,$0,'f'
- sb $2,0($20)
- ori $2,$0,65*13
- ori $3,$0,13
- divu $2,$3
- nop
- mflo $4
- sb $4,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #g: MULT
- ori $2,$0,'g'
- sb $2,0($20)
- ori $2,$0,5
- ori $3,$0,13
- mult $2,$3
- nop
- mflo $4
- sb $4,0($20) #A
- li $2,-5
- ori $3,$0,13
- mult $2,$3
- mfhi $5
- mflo $4
- sub $4,$0,$4
- addu $4,$4,$5
- addi $4,$4,2
- sb $4,0($20) #B
- ori $2,$0,5
- li $3,-13
- mult $2,$3
- mfhi $5
- mflo $4
- sub $4,$0,$4
- addu $4,$4,$5
- addi $4,$4,3
- sb $4,0($20) #C
- li $2,-5
- li $3,-13
- mult $2,$3
- mfhi $5
- mflo $4
- addu $4,$4,$5
- addi $4,$4,3
- sb $4,0($20) #D
- lui $4,0xfe98
- ori $4,$4,0x62e5
- lui $5,0x6
- ori $5,0x8db8
- mult $4,$5
- mfhi $6
- addiu $7,$6,2356+1+'E' #E
- sb $7,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #h: MULTU
- ori $2,$0,'h'
- sb $2,0($20)
- ori $2,$0,5
- ori $3,$0,13
- multu $2,$3
- nop
- mflo $4
- sb $4,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #i: SLT
- ori $2,$0,'i'
- sb $2,0($20)
- ori $2,$0,10
- ori $3,$0,12
- slt $4,$2,$3
- addi $5,$4,64
- sb $5,0($20) #A
- slt $4,$3,$2
- addi $5,$4,66
- sb $5,0($20) #B
- li $2,0xfffffff0
- slt $4,$2,$3
- addi $5,$4,66
- sb $5,0($20) #C
- slt $4,$3,$2
- addi $5,$4,68
- sb $5,0($20) #D
- li $3,0xffffffff
- slt $4,$2,$3
- addi $5,$4,68
- sb $5,0($20) #E
- slt $4,$3,$2
- addi $5,$4,70
- sb $5,0($20) #F
- sb $23,0($20)
- sb $21,0($20)
-
- #j: SLTI
- ori $2,$0,'j'
- sb $2,0($20)
- ori $2,$0,10
- slti $4,$2,12
- addi $5,$4,64
- sb $5,0($20) #A
- slti $4,$2,8
- addi $5,$4,66
- sb $5,0($20) #B
- sb $23,0($20)
- sb $21,0($20)
-
- #k: SLTIU
- ori $2,$0,'k'
- sb $2,0($20)
- ori $2,$0,10
- sltiu $4,$2,12
- addi $5,$4,64
- sb $5,0($20) #A
- sltiu $4,$2,8
- addi $5,$4,66
- sb $5,0($20) #B
- sb $23,0($20)
- sb $21,0($20)
-
- #l: SLTU
- ori $2,$0,'l'
- sb $2,0($20)
- ori $2,$0,10
- ori $3,$0,12
- slt $4,$2,$3
- addi $5,$4,64
- sb $5,0($20) #A
- slt $4,$3,$2
- addi $5,$4,66
- sb $5,0($20) #B
- sb $23,0($20)
- sb $21,0($20)
-
- #m: SUB
- ori $2,$0,'m'
- sb $2,0($20)
- ori $3,$0,70
- ori $4,$0,5
- sub $2,$3,$4
- sb $2,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- #n: SUBU
- ori $2,$0,'n'
- sb $2,0($20)
- ori $3,$0,70
- ori $4,$0,5
- sub $2,$3,$4
- sb $2,0($20) #A
- sb $23,0($20)
- sb $21,0($20)
-
- ######################################
- #Branch and Jump Instructions
- ######################################
- ori $2,$0,'B'
- sb $2,0($20)
- ori $2,$0,'r'
- sb $2,0($20)
- ori $2,$0,'a'
- sb $2,0($20)
- ori $2,$0,'n'
- sb $2,0($20)
- ori $2,$0,'c'
- sb $2,0($20)
- ori $2,$0,'h'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: B
- ori $2,$0,'a'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- b $B1
- sb $10,0($20)
- sb $22,0($20)
-$B1:
- sb $11,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #b: BAL
- ori $2,$0,'b'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $15,$0,'X'
- bal $BAL1
- sb $10,0($20)
- sb $13,0($20)
- b $BAL2
- sb $14,0($20)
- sb $15,0($20)
-$BAL1:
- sb $11,0($20)
- jr $31
- sb $12,0($20)
- sb $22,0($20)
-$BAL2:
- sb $23,0($20)
- sb $21,0($20)
-
- #c: BEQ
- ori $2,$0,'c'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $2,$0,100
- ori $3,$0,123
- ori $4,$0,123
- beq $2,$3,$BEQ1
- sb $10,0($20)
- sb $11,0($20)
- beq $3,$4,$BEQ1
- sb $12,0($20)
- sb $22,0($20)
-$BEQ1:
- sb $13,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #d: BGEZ
- ori $2,$0,'d'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- or $15,$0,'X'
- ori $2,$0,100
- li $3,0xffff1234
- ori $4,$0,123
- bgez $3,$BGEZ1
- sb $10,0($20)
- sb $11,0($20)
- bgez $2,$BGEZ1
- sb $12,0($20)
- sb $22,0($20)
-$BGEZ1:
- bgez $0,$BGEZ2
- nop
- sb $15,0($20)
-$BGEZ2:
- sb $13,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #e: BGEZAL
- ori $2,$0,'e'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $15,$0,'X'
- li $3,0xffff1234
- bgezal $3,$BGEZAL1
- nop
- sb $10,0($20)
- bgezal $0,$BGEZAL1
- nop
- sb $13,0($20)
- b $BGEZAL2
- sb $14,0($20)
- sb $15,0($20)
-$BGEZAL1:
- sb $11,0($20)
- jr $31
- sb $12,0($20)
- sb $22,0($20)
-$BGEZAL2:
- sb $23,0($20)
- sb $21,0($20)
-
- #f: BGTZ
- ori $2,$0,'f'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $2,$0,100
- li $3,0xffff1234
- bgtz $3,$BGTZ1
- sb $10,0($20)
- sb $11,0($20)
- bgtz $2,$BGTZ1
- sb $12,0($20)
- sb $22,0($20)
-$BGTZ1:
- sb $13,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #g: BLEZ
- ori $2,$0,'g'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $2,$0,100
- li $3,0xffff1234
- blez $2,$BLEZ1
- sb $10,0($20)
- sb $11,0($20)
- blez $3,$BLEZ1
- sb $12,0($20)
- sb $22,0($20)
-$BLEZ1:
- blez $0,$BLEZ2
- nop
- sb $22,0($20)
-$BLEZ2:
- sb $13,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #h: BLTZ
- ori $2,$0,'h'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $2,$0,100
- li $3,0xffff1234
- ori $4,$0,0
- bltz $2,$BLTZ1
- sb $10,0($20)
- sb $11,0($20)
- bltz $3,$BLTZ1
- sb $12,0($20)
- sb $22,0($20)
-$BLTZ1:
- bltz $4,$BLTZ2
- nop
- sb $13,0($20)
-$BLTZ2:
- sb $14,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #i: BLTZAL
- ori $2,$0,'i'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $15,$0,'X'
- li $3,0xffff1234
- bltzal $0,$BLTZAL1
- nop
- sb $10,0($20)
- bltzal $3,$BLTZAL1
- nop
- sb $13,0($20)
- b $BLTZAL2
- sb $14,0($20)
- sb $15,0($20)
-$BLTZAL1:
- sb $11,0($20)
- jr $31
- sb $12,0($20)
- sb $22,0($20)
-$BLTZAL2:
- sb $23,0($20)
- sb $21,0($20)
-
- #j: BNE
- ori $2,$0,'j'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $2,$0,100
- ori $3,$0,123
- ori $4,$0,123
- bne $3,$4,$BNE1
- sb $10,0($20)
- sb $11,0($20)
- bne $2,$3,$BNE1
- sb $12,0($20)
- sb $22,0($20)
-$BNE1:
- sb $13,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #k: J
- ori $2,$0,'k'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $15,$0,'X'
- j $J1
- sb $10,0($20)
- sb $15,0($20)
-$J1:
- sb $11,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #l: JAL
- ori $2,$0,'l'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $15,$0,'X'
- jal $JAL1
- sb $10,0($20)
- sb $13,0($20)
- b $JAL2
- sb $14,0($20)
- sb $15,0($20)
-$JAL1:
- sb $11,0($20)
- jr $31
- sb $12,0($20)
- sb $22,0($20)
-$JAL2:
- sb $23,0($20)
- sb $21,0($20)
-
- #m: JALR
- ori $2,$0,'m'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $12,$0,'C'
- ori $13,$0,'D'
- ori $14,$0,'E'
- ori $15,$0,'X'
- la $3,$JALR1
- jalr $3
- sb $10,0($20)
- sb $13,0($20)
- b $JALR2
- sb $14,0($20)
- sb $15,0($20)
-$JALR1:
- sb $11,0($20)
- jr $31
- sb $12,0($20)
- sb $22,0($20)
-$JALR2:
- sb $23,0($20)
- sb $21,0($20)
-
- #n: JR
- ori $2,$0,'n'
- sb $2,0($20)
- ori $10,$0,'A'
- ori $11,$0,'B'
- ori $15,$0,'X'
- la $3,$JR1
- jr $3
- sb $10,0($20)
- sb $15,0($20)
-$JR1:
- sb $11,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #o: NOP
- ori $2,$0,'o'
- sb $2,0($20)
- ori $2,$0,65
- nop
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
- ######################################
- #Load, Store, and Memory Control Instructions
- ######################################
- ori $2,$0,'L'
- sb $2,0($20)
- ori $2,$0,'o'
- sb $2,0($20)
- ori $2,$0,'a'
- sb $2,0($20)
- ori $2,$0,'d'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: LB
- ori $2,$0,'a'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x41424344
- sw $3,16($2)
- lb $4,16($2)
- sb $4,0($20)
- lb $4,17($2)
- sb $4,0($20)
- lb $4,18($2)
- sb $4,0($20)
- lb $2,19($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #b: LBU
- ori $2,$0,'b'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x41424344
- sw $3,16($2)
- lb $4,16($2)
- sb $4,0($20)
- lb $4,17($2)
- sb $4,0($20)
- lb $4,18($2)
- sb $4,0($20)
- lb $2,19($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #c: LH
- ori $2,$0,'c'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x00410042
- sw $3,16($2)
- lh $4,16($2)
- sb $4,0($20)
- lh $2,18($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #d: LHU
- ori $2,$0,'d'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x00410042
- sw $3,16($2)
- lh $4,16($2)
- sb $4,0($20)
- lh $2,18($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #e: LW
- ori $2,$0,'e'
- sb $2,0($20)
- or $2,$0,$24
- li $3,'A'
- sw $3,16($2)
- ori $3,$0,0
- lw $2,16($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #f: LWL & LWR
- ori $2,$0,'f'
- sb $2,0($20)
- or $2,$0,$24
- li $3,'A'
- sw $3,16($2)
- ori $3,$0,0
- lwl $2,16($2)
- lwr $2,16($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #g: SB
- ori $2,$0,'g'
- sb $2,0($20)
- ori $2,$0,'A'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #h: SH
- ori $2,$0,'h'
- sb $2,0($20)
- or $4,$0,$24
- ori $2,$0,0x4142
- sh $2,16($4)
- lb $3,16($4)
- sb $3,0($20)
- lb $2,17($4)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #i: SW
- ori $2,$0,'i'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x41424344
- sw $3,16($2)
- lb $4,16($2)
- sb $4,0($20)
- lb $4,17($2)
- sb $4,0($20)
- lb $4,18($2)
- sb $4,0($20)
- lb $2,19($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #j: SWL & SWR
- ori $2,$0,'j'
- sb $2,0($20)
- or $2,$0,$24
- li $3,0x41424344
- swl $3,16($2)
- swr $3,16($2)
- lb $4,16($2)
- sb $4,0($20)
- lb $4,17($2)
- sb $4,0($20)
- lb $4,18($2)
- sb $4,0($20)
- lb $2,19($2)
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
- ######################################
- #Logical Instructions
- ######################################
- ori $2,$0,'L'
- sb $2,0($20)
- ori $2,$0,'o'
- sb $2,0($20)
- ori $2,$0,'g'
- sb $2,0($20)
- ori $2,$0,'i'
- sb $2,0($20)
- ori $2,$0,'c'
- sb $2,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #a: AND
- ori $2,$0,'a'
- sb $2,0($20)
- ori $2,$0,0x0741
- ori $3,$0,0x60f3
- and $4,$2,$3
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #b: ANDI
- ori $2,$0,'b'
- sb $2,0($20)
- ori $2,$0,0x0741
- andi $4,$2,0x60f3
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #c: LUI
- ori $2,$0,'c'
- sb $2,0($20)
- lui $2,0x41
- srl $3,$2,16
- sb $3,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #d: NOR
- ori $2,$0,'d'
- sb $2,0($20)
- li $2,0xf0fff08e
- li $3,0x0f0f0f30
- nor $4,$2,$3
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #e: OR
- ori $2,$0,'e'
- sb $2,0($20)
- ori $2,$0,0x40
- ori $3,$0,0x01
- or $4,$2,$3
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #f: ORI
- ori $2,$0,'f'
- sb $2,0($20)
- ori $2,$0,0x40
- ori $4,$2,0x01
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #g: XOR
- ori $2,$0,'g'
- sb $2,0($20)
- ori $2,$0,0xf043
- ori $3,$0,0xf002
- xor $4,$2,$3
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
- #h: XORI
- ori $2,$0,'h'
- sb $2,0($20)
- ori $2,$0,0xf043
- xor $4,$2,0xf002
- sb $4,0($20)
- sb $23,0($20)
- sb $21,0($20)
-
-
-$DONE:
- j $DONE
- nop
-
-.set reorder
+
+strip_test_code: file format elf32-tradlittlemips
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 3c1c0000 lui gp,0x0
+ 4: 379c0000 ori gp,gp,0x0
+ 8: 3c040000 lui a0,0x0
+ c: 34840000 ori a0,a0,0x0
+ 10: 3c050000 lui a1,0x0
+ 14: 34a50000 ori a1,a1,0x0
+ 18: 3c1d0080 lui sp,0x80
+ 1c: 37bd0000 ori sp,sp,0x0
+ 20: 3c140080 lui s4,0x80
+ 24: 36940010 ori s4,s4,0x10
+ 28: 3415000a li s5,0xa
+ 2c: 34160058 li s6,0x58
+ 30: 3417000d li s7,0xd
+ 34: 3c180080 lui t8,0x80
+ 38: 37180004 ori t8,t8,0x4
+ 3c: 3402004d li v0,0x4d
+ 40: a2820000 sb v0,0(s4)
+ 44: 3402006f li v0,0x6f
+ 48: a2820000 sb v0,0(s4)
+ 4c: 34020076 li v0,0x76
+ 50: a2820000 sb v0,0(s4)
+ 54: 34020065 li v0,0x65
+ 58: a2820000 sb v0,0(s4)
+ 5c: a2970000 sb s7,0(s4)
+ 60: a2950000 sb s5,0(s4)
+ 64: 34020061 li v0,0x61
+ 68: a2820000 sb v0,0(s4)
+ 6c: 34020041 li v0,0x41
+ 70: 00400011 mthi v0
+ 74: 00001810 mfhi v1
+ 78: a2830000 sb v1,0(s4)
+ 7c: a2970000 sb s7,0(s4)
+ 80: a2950000 sb s5,0(s4)
+ 84: 34020062 li v0,0x62
+ 88: a2820000 sb v0,0(s4)
+ 8c: 34020041 li v0,0x41
+ 90: 00400013 mtlo v0
+ 94: 00001812 mflo v1
+ 98: a2830000 sb v1,0(s4)
+ 9c: a2970000 sb s7,0(s4)
+ a0: a2950000 sb s5,0(s4)
+ a4: 34020063 li v0,0x63
+ a8: a2820000 sb v0,0(s4)
+ ac: 34020041 li v0,0x41
+ b0: 00400011 mthi v0
+ b4: 00001810 mfhi v1
+ b8: a2830000 sb v1,0(s4)
+ bc: a2970000 sb s7,0(s4)
+ c0: a2950000 sb s5,0(s4)
+ c4: 34020064 li v0,0x64
+ c8: a2820000 sb v0,0(s4)
+ cc: 34020041 li v0,0x41
+ d0: 00400013 mtlo v0
+ d4: 00001812 mflo v1
+ d8: a2830000 sb v1,0(s4)
+ dc: a2970000 sb s7,0(s4)
+ e0: a2950000 sb s5,0(s4)
+ e4: 34020053 li v0,0x53
+ e8: a2820000 sb v0,0(s4)
+ ec: 34020068 li v0,0x68
+ f0: a2820000 sb v0,0(s4)
+ f4: 34020069 li v0,0x69
+ f8: a2820000 sb v0,0(s4)
+ fc: 34020066 li v0,0x66
+ 100: a2820000 sb v0,0(s4)
+ 104: 34020074 li v0,0x74
+ 108: a2820000 sb v0,0(s4)
+ 10c: a2970000 sb s7,0(s4)
+ 110: a2950000 sb s5,0(s4)
+ 114: 34020061 li v0,0x61
+ 118: a2820000 sb v0,0(s4)
+ 11c: 3c024041 lui v0,0x4041
+ 120: 34424243 ori v0,v0,0x4243
+ 124: 00021a00 sll v1,v0,0x8
+ 128: 00031e02 srl v1,v1,0x18
+ 12c: a2830000 sb v1,0(s4)
+ 130: a2970000 sb s7,0(s4)
+ 134: a2950000 sb s5,0(s4)
+ 138: 34020062 li v0,0x62
+ 13c: a2820000 sb v0,0(s4)
+ 140: 3c024041 lui v0,0x4041
+ 144: 34424243 ori v0,v0,0x4243
+ 148: 34030008 li v1,0x8
+ 14c: 00621804 sllv v1,v0,v1
+ 150: 00031e02 srl v1,v1,0x18
+ 154: a2830000 sb v1,0(s4)
+ 158: a2970000 sb s7,0(s4)
+ 15c: a2950000 sb s5,0(s4)
+ 160: 34020063 li v0,0x63
+ 164: a2820000 sb v0,0(s4)
+ 168: 3c024041 lui v0,0x4041
+ 16c: 34424243 ori v0,v0,0x4243
+ 170: 00021c03 sra v1,v0,0x10
+ 174: a2830000 sb v1,0(s4)
+ 178: 3c028400 lui v0,0x8400
+ 17c: 00021e43 sra v1,v0,0x19
+ 180: 2063ff80 addi v1,v1,-128
+ 184: a2830000 sb v1,0(s4)
+ 188: a2970000 sb s7,0(s4)
+ 18c: a2950000 sb s5,0(s4)
+ 190: 34020064 li v0,0x64
+ 194: a2820000 sb v0,0(s4)
+ 198: 3c024041 lui v0,0x4041
+ 19c: 34424243 ori v0,v0,0x4243
+ 1a0: 34030010 li v1,0x10
+ 1a4: 00621807 srav v1,v0,v1
+ 1a8: a2830000 sb v1,0(s4)
+ 1ac: 34030019 li v1,0x19
+ 1b0: 3c028400 lui v0,0x8400
+ 1b4: 00621807 srav v1,v0,v1
+ 1b8: 2063ff80 addi v1,v1,-128
+ 1bc: a2830000 sb v1,0(s4)
+ 1c0: a2970000 sb s7,0(s4)
+ 1c4: a2950000 sb s5,0(s4)
+ 1c8: 34020065 li v0,0x65
+ 1cc: a2820000 sb v0,0(s4)
+ 1d0: 3c024041 lui v0,0x4041
+ 1d4: 34424243 ori v0,v0,0x4243
+ 1d8: 00021c02 srl v1,v0,0x10
+ 1dc: a2830000 sb v1,0(s4)
+ 1e0: 3c028400 lui v0,0x8400
+ 1e4: 00021e42 srl v1,v0,0x19
+ 1e8: a2830000 sb v1,0(s4)
+ 1ec: a2970000 sb s7,0(s4)
+ 1f0: a2950000 sb s5,0(s4)
+ 1f4: 34020066 li v0,0x66
+ 1f8: a2820000 sb v0,0(s4)
+ 1fc: 3c024041 lui v0,0x4041
+ 200: 34424243 ori v0,v0,0x4243
+ 204: 34030010 li v1,0x10
+ 208: 00622006 srlv a0,v0,v1
+ 20c: a2840000 sb a0,0(s4)
+ 210: 34030019 li v1,0x19
+ 214: 3c028400 lui v0,0x8400
+ 218: 00621806 srlv v1,v0,v1
+ 21c: a2830000 sb v1,0(s4)
+ 220: a2970000 sb s7,0(s4)
+ 224: a2950000 sb s5,0(s4)
+ 228: 34020044 li v0,0x44
+ 22c: a2820000 sb v0,0(s4)
+ 230: 3402006f li v0,0x6f
+ 234: a2820000 sb v0,0(s4)
+ 238: 3402006e li v0,0x6e
+ 23c: a2820000 sb v0,0(s4)
+ 240: 34020065 li v0,0x65
+ 244: a2820000 sb v0,0(s4)
+ 248: a2970000 sb s7,0(s4)
+ 24c: a2950000 sb s5,0(s4)
+ 250: 34020041 li v0,0x41
+ 254: a2820000 sb v0,0(s4)
+ 258: 34020072 li v0,0x72
+ 25c: a2820000 sb v0,0(s4)
+ 260: 34020069 li v0,0x69
+ 264: a2820000 sb v0,0(s4)
+ 268: 34020074 li v0,0x74
+ 26c: a2820000 sb v0,0(s4)
+ 270: 34020068 li v0,0x68
+ 274: a2820000 sb v0,0(s4)
+ 278: a2970000 sb s7,0(s4)
+ 27c: a2950000 sb s5,0(s4)
+ 280: 34020061 li v0,0x61
+ 284: a2820000 sb v0,0(s4)
+ 288: 34030005 li v1,0x5
+ 28c: 3404003c li a0,0x3c
+ 290: 00641020 add v0,v1,a0
+ 294: a2820000 sb v0,0(s4)
+ 298: a2970000 sb s7,0(s4)
+ 29c: a2950000 sb s5,0(s4)
+ 2a0: 34020062 li v0,0x62
+ 2a4: a2820000 sb v0,0(s4)
+ 2a8: 3404003c li a0,0x3c
+ 2ac: 20820005 addi v0,a0,5
+ 2b0: a2820000 sb v0,0(s4)
+ 2b4: a2970000 sb s7,0(s4)
+ 2b8: a2950000 sb s5,0(s4)
+ 2bc: 34020063 li v0,0x63
+ 2c0: a2820000 sb v0,0(s4)
+ 2c4: 34040032 li a0,0x32
+ 2c8: 2485000f addiu a1,a0,15
+ 2cc: a2850000 sb a1,0(s4)
+ 2d0: a2970000 sb s7,0(s4)
+ 2d4: a2950000 sb s5,0(s4)
+ 2d8: 34020064 li v0,0x64
+ 2dc: a2820000 sb v0,0(s4)
+ 2e0: 34030005 li v1,0x5
+ 2e4: 3404003c li a0,0x3c
+ 2e8: 00641020 add v0,v1,a0
+ 2ec: a2820000 sb v0,0(s4)
+ 2f0: a2970000 sb s7,0(s4)
+ 2f4: a2950000 sb s5,0(s4)
+ 2f8: 34020065 li v0,0x65
+ 2fc: a2820000 sb v0,0(s4)
+ 300: 34021dde li v0,0x1dde
+ 304: 34030075 li v1,0x75
+ 308: 14600002 bnez v1,0x314
+ 30c: 0043001a div zero,v0,v1
+ 310: 0007000d break 0x7
+ 314: 2401ffff li at,-1
+ 318: 14610004 bne v1,at,0x32c
+ 31c: 3c018000 lui at,0x8000
+ 320: 14410002 bne v0,at,0x32c
+ 324: 00000000 nop
+ 328: 0006000d break 0x6
+ 32c: 00001012 mflo v0
+ 330: 00000000 nop
+ 334: 00002012 mflo a0
+ 338: a2840000 sb a0,0(s4)
+ 33c: 00002010 mfhi a0
+ 340: 20840019 addi a0,a0,25
+ 344: a2840000 sb a0,0(s4)
+ 348: 2402fb07 li v0,-1273
+ 34c: 34030013 li v1,0x13
+ 350: 14600002 bnez v1,0x35c
+ 354: 0043001a div zero,v0,v1
+ 358: 0007000d break 0x7
+ 35c: 2401ffff li at,-1
+ 360: 14610004 bne v1,at,0x374
+ 364: 3c018000 lui at,0x8000
+ 368: 14410002 bne v0,at,0x374
+ 36c: 00000000 nop
+ 370: 0006000d break 0x6
+ 374: 00001012 mflo v0
+ 378: 00000000 nop
+ 37c: 00002012 mflo a0
+ 380: 00042022 neg a0,a0
+ 384: a2840000 sb a0,0(s4)
+ 388: 3402061c li v0,0x61c
+ 38c: 2403ffe9 li v1,-23
+ 390: 14600002 bnez v1,0x39c
+ 394: 0043001a div zero,v0,v1
+ 398: 0007000d break 0x7
+ 39c: 2401ffff li at,-1
+ 3a0: 14610004 bne v1,at,0x3b4
+ 3a4: 3c018000 lui at,0x8000
+ 3a8: 14410002 bne v0,at,0x3b4
+ 3ac: 00000000 nop
+ 3b0: 0006000d break 0x6
+ 3b4: 00001012 mflo v0
+ 3b8: 00000000 nop
+ 3bc: 00002012 mflo a0
+ 3c0: 00042022 neg a0,a0
+ 3c4: a2840000 sb a0,0(s4)
+ 3c8: 2402fc7f li v0,-897
+ 3cc: 2403fff3 li v1,-13
+ 3d0: 14600002 bnez v1,0x3dc
+ 3d4: 0043001a div zero,v0,v1
+ 3d8: 0007000d break 0x7
+ 3dc: 2401ffff li at,-1
+ 3e0: 14610004 bne v1,at,0x3f4
+ 3e4: 3c018000 lui at,0x8000
+ 3e8: 14410002 bne v0,at,0x3f4
+ 3ec: 00000000 nop
+ 3f0: 0006000d break 0x6
+ 3f4: 00001012 mflo v0
+ 3f8: 00002012 mflo a0
+ 3fc: a2840000 sb a0,0(s4)
+ 400: a2970000 sb s7,0(s4)
+ 404: a2950000 sb s5,0(s4)
+ 408: 34020066 li v0,0x66
+ 40c: a2820000 sb v0,0(s4)
+ 410: 3402034d li v0,0x34d
+ 414: 3403000d li v1,0xd
+ 418: 14600002 bnez v1,0x424
+ 41c: 0043001b divu zero,v0,v1
+ 420: 0007000d break 0x7
+ 424: 00001012 mflo v0
+ 428: 00000000 nop
+ 42c: 00002012 mflo a0
+ 430: a2840000 sb a0,0(s4)
+ 434: a2970000 sb s7,0(s4)
+ 438: a2950000 sb s5,0(s4)
+ 43c: 34020067 li v0,0x67
+ 440: a2820000 sb v0,0(s4)
+ 444: 34020005 li v0,0x5
+ 448: 3403000d li v1,0xd
+ 44c: 00430018 mult v0,v1
+ 450: 00000000 nop
+ 454: 00002012 mflo a0
+ 458: a2840000 sb a0,0(s4)
+ 45c: 2402fffb li v0,-5
+ 460: 3403000d li v1,0xd
+ 464: 00430018 mult v0,v1
+ 468: 00002810 mfhi a1
+ 46c: 00002012 mflo a0
+ 470: 00042022 neg a0,a0
+ 474: 00852021 addu a0,a0,a1
+ 478: 20840002 addi a0,a0,2
+ 47c: a2840000 sb a0,0(s4)
+ 480: 34020005 li v0,0x5
+ 484: 2403fff3 li v1,-13
+ 488: 00430018 mult v0,v1
+ 48c: 00002810 mfhi a1
+ 490: 00002012 mflo a0
+ 494: 00042022 neg a0,a0
+ 498: 00852021 addu a0,a0,a1
+ 49c: 20840003 addi a0,a0,3
+ 4a0: a2840000 sb a0,0(s4)
+ 4a4: 2402fffb li v0,-5
+ 4a8: 2403fff3 li v1,-13
+ 4ac: 00430018 mult v0,v1
+ 4b0: 00002810 mfhi a1
+ 4b4: 00002012 mflo a0
+ 4b8: 00852021 addu a0,a0,a1
+ 4bc: 20840003 addi a0,a0,3
+ 4c0: a2840000 sb a0,0(s4)
+ 4c4: 3c04fe98 lui a0,0xfe98
+ 4c8: 348462e5 ori a0,a0,0x62e5
+ 4cc: 3c050006 lui a1,0x6
+ 4d0: 34a58db8 ori a1,a1,0x8db8
+ 4d4: 00850018 mult a0,a1
+ 4d8: 00003010 mfhi a2
+ 4dc: 24c7097a addiu a3,a2,2426
+ 4e0: a2870000 sb a3,0(s4)
+ 4e4: a2970000 sb s7,0(s4)
+ 4e8: a2950000 sb s5,0(s4)
+ 4ec: 34020068 li v0,0x68
+ 4f0: a2820000 sb v0,0(s4)
+ 4f4: 34020005 li v0,0x5
+ 4f8: 3403000d li v1,0xd
+ 4fc: 00430019 multu v0,v1
+ 500: 00000000 nop
+ 504: 00002012 mflo a0
+ 508: a2840000 sb a0,0(s4)
+ 50c: a2970000 sb s7,0(s4)
+ 510: a2950000 sb s5,0(s4)
+ 514: 34020069 li v0,0x69
+ 518: a2820000 sb v0,0(s4)
+ 51c: 3402000a li v0,0xa
+ 520: 3403000c li v1,0xc
+ 524: 0043202a slt a0,v0,v1
+ 528: 20850040 addi a1,a0,64
+ 52c: a2850000 sb a1,0(s4)
+ 530: 0062202a slt a0,v1,v0
+ 534: 20850042 addi a1,a0,66
+ 538: a2850000 sb a1,0(s4)
+ 53c: 2402fff0 li v0,-16
+ 540: 0043202a slt a0,v0,v1
+ 544: 20850042 addi a1,a0,66
+ 548: a2850000 sb a1,0(s4)
+ 54c: 0062202a slt a0,v1,v0
+ 550: 20850044 addi a1,a0,68
+ 554: a2850000 sb a1,0(s4)
+ 558: 2403ffff li v1,-1
+ 55c: 0043202a slt a0,v0,v1
+ 560: 20850044 addi a1,a0,68
+ 564: a2850000 sb a1,0(s4)
+ 568: 0062202a slt a0,v1,v0
+ 56c: 20850046 addi a1,a0,70
+ 570: a2850000 sb a1,0(s4)
+ 574: a2970000 sb s7,0(s4)
+ 578: a2950000 sb s5,0(s4)
+ 57c: 3402006a li v0,0x6a
+ 580: a2820000 sb v0,0(s4)
+ 584: 3402000a li v0,0xa
+ 588: 2844000c slti a0,v0,12
+ 58c: 20850040 addi a1,a0,64
+ 590: a2850000 sb a1,0(s4)
+ 594: 28440008 slti a0,v0,8
+ 598: 20850042 addi a1,a0,66
+ 59c: a2850000 sb a1,0(s4)
+ 5a0: a2970000 sb s7,0(s4)
+ 5a4: a2950000 sb s5,0(s4)
+ 5a8: 3402006b li v0,0x6b
+ 5ac: a2820000 sb v0,0(s4)
+ 5b0: 3402000a li v0,0xa
+ 5b4: 2c44000c sltiu a0,v0,12
+ 5b8: 20850040 addi a1,a0,64
+ 5bc: a2850000 sb a1,0(s4)
+ 5c0: 2c440008 sltiu a0,v0,8
+ 5c4: 20850042 addi a1,a0,66
+ 5c8: a2850000 sb a1,0(s4)
+ 5cc: a2970000 sb s7,0(s4)
+ 5d0: a2950000 sb s5,0(s4)
+ 5d4: 3402006c li v0,0x6c
+ 5d8: a2820000 sb v0,0(s4)
+ 5dc: 3402000a li v0,0xa
+ 5e0: 3403000c li v1,0xc
+ 5e4: 0043202a slt a0,v0,v1
+ 5e8: 20850040 addi a1,a0,64
+ 5ec: a2850000 sb a1,0(s4)
+ 5f0: 0062202a slt a0,v1,v0
+ 5f4: 20850042 addi a1,a0,66
+ 5f8: a2850000 sb a1,0(s4)
+ 5fc: a2970000 sb s7,0(s4)
+ 600: a2950000 sb s5,0(s4)
+ 604: 3402006d li v0,0x6d
+ 608: a2820000 sb v0,0(s4)
+ 60c: 34030046 li v1,0x46
+ 610: 34040005 li a0,0x5
+ 614: 00641022 sub v0,v1,a0
+ 618: a2820000 sb v0,0(s4)
+ 61c: a2970000 sb s7,0(s4)
+ 620: a2950000 sb s5,0(s4)
+ 624: 3402006e li v0,0x6e
+ 628: a2820000 sb v0,0(s4)
+ 62c: 34030046 li v1,0x46
+ 630: 34040005 li a0,0x5
+ 634: 00641022 sub v0,v1,a0
+ 638: a2820000 sb v0,0(s4)
+ 63c: a2970000 sb s7,0(s4)
+ 640: a2950000 sb s5,0(s4)
+ 644: 34020042 li v0,0x42
+ 648: a2820000 sb v0,0(s4)
+ 64c: 34020072 li v0,0x72
+ 650: a2820000 sb v0,0(s4)
+ 654: 34020061 li v0,0x61
+ 658: a2820000 sb v0,0(s4)
+ 65c: 3402006e li v0,0x6e
+ 660: a2820000 sb v0,0(s4)
+ 664: 34020063 li v0,0x63
+ 668: a2820000 sb v0,0(s4)
+ 66c: 34020068 li v0,0x68
+ 670: a2820000 sb v0,0(s4)
+ 674: a2970000 sb s7,0(s4)
+ 678: a2950000 sb s5,0(s4)
+ 67c: 34020061 li v0,0x61
+ 680: a2820000 sb v0,0(s4)
+ 684: 340a0041 li t2,0x41
+ 688: 340b0042 li t3,0x42
+ 68c: 10000002 b 0x698
+ 690: a28a0000 sb t2,0(s4)
+ 694: a2960000 sb s6,0(s4)
+ 698: a28b0000 sb t3,0(s4)
+ 69c: a2970000 sb s7,0(s4)
+ 6a0: a2950000 sb s5,0(s4)
+ 6a4: 34020062 li v0,0x62
+ 6a8: a2820000 sb v0,0(s4)
+ 6ac: 340a0041 li t2,0x41
+ 6b0: 340b0042 li t3,0x42
+ 6b4: 340c0043 li t4,0x43
+ 6b8: 340d0044 li t5,0x44
+ 6bc: 340e0045 li t6,0x45
+ 6c0: 340f0058 li t7,0x58
+ 6c4: 04110005 bal 0x6dc
+ 6c8: a28a0000 sb t2,0(s4)
+ 6cc: a28d0000 sb t5,0(s4)
+ 6d0: 10000006 b 0x6ec
+ 6d4: a28e0000 sb t6,0(s4)
+ 6d8: a28f0000 sb t7,0(s4)
+ 6dc: a28b0000 sb t3,0(s4)
+ 6e0: 03e00008 jr ra
+ 6e4: a28c0000 sb t4,0(s4)
+ 6e8: a2960000 sb s6,0(s4)
+ 6ec: a2970000 sb s7,0(s4)
+ 6f0: a2950000 sb s5,0(s4)
+ 6f4: 34020063 li v0,0x63
+ 6f8: a2820000 sb v0,0(s4)
+ 6fc: 340a0041 li t2,0x41
+ 700: 340b0042 li t3,0x42
+ 704: 340c0043 li t4,0x43
+ 708: 340d0044 li t5,0x44
+ 70c: 34020064 li v0,0x64
+ 710: 3403007b li v1,0x7b
+ 714: 3404007b li a0,0x7b
+ 718: 10430005 beq v0,v1,0x730
+ 71c: a28a0000 sb t2,0(s4)
+ 720: a28b0000 sb t3,0(s4)
+ 724: 10640002 beq v1,a0,0x730
+ 728: a28c0000 sb t4,0(s4)
+ 72c: a2960000 sb s6,0(s4)
+ 730: a28d0000 sb t5,0(s4)
+ 734: a2970000 sb s7,0(s4)
+ 738: a2950000 sb s5,0(s4)
+ 73c: 34020064 li v0,0x64
+ 740: a2820000 sb v0,0(s4)
+ 744: 340a0041 li t2,0x41
+ 748: 340b0042 li t3,0x42
+ 74c: 340c0043 li t4,0x43
+ 750: 340d0044 li t5,0x44
+ 754: 340f0058 li t7,0x58
+ 758: 34020064 li v0,0x64
+ 75c: 3c03ffff lui v1,0xffff
+ 760: 34631234 ori v1,v1,0x1234
+ 764: 3404007b li a0,0x7b
+ 768: 04610005 bgez v1,0x780
+ 76c: a28a0000 sb t2,0(s4)
+ 770: a28b0000 sb t3,0(s4)
+ 774: 04410002 bgez v0,0x780
+ 778: a28c0000 sb t4,0(s4)
+ 77c: a2960000 sb s6,0(s4)
+ 780: 04010002 b 0x78c
+ 784: 00000000 nop
+ 788: a28f0000 sb t7,0(s4)
+ 78c: a28d0000 sb t5,0(s4)
+ 790: a2970000 sb s7,0(s4)
+ 794: a2950000 sb s5,0(s4)
+ 798: 34020065 li v0,0x65
+ 79c: a2820000 sb v0,0(s4)
+ 7a0: 340a0041 li t2,0x41
+ 7a4: 340b0042 li t3,0x42
+ 7a8: 340c0043 li t4,0x43
+ 7ac: 340d0044 li t5,0x44
+ 7b0: 340e0045 li t6,0x45
+ 7b4: 340f0058 li t7,0x58
+ 7b8: 3c03ffff lui v1,0xffff
+ 7bc: 34631234 ori v1,v1,0x1234
+ 7c0: 04710008 bgezal v1,0x7e4
+ 7c4: 00000000 nop
+ 7c8: a28a0000 sb t2,0(s4)
+ 7cc: 04110005 bal 0x7e4
+ 7d0: 00000000 nop
+ 7d4: a28d0000 sb t5,0(s4)
+ 7d8: 10000006 b 0x7f4
+ 7dc: a28e0000 sb t6,0(s4)
+ 7e0: a28f0000 sb t7,0(s4)
+ 7e4: a28b0000 sb t3,0(s4)
+ 7e8: 03e00008 jr ra
+ 7ec: a28c0000 sb t4,0(s4)
+ 7f0: a2960000 sb s6,0(s4)
+ 7f4: a2970000 sb s7,0(s4)
+ 7f8: a2950000 sb s5,0(s4)
+ 7fc: 34020066 li v0,0x66
+ 800: a2820000 sb v0,0(s4)
+ 804: 340a0041 li t2,0x41
+ 808: 340b0042 li t3,0x42
+ 80c: 340c0043 li t4,0x43
+ 810: 340d0044 li t5,0x44
+ 814: 34020064 li v0,0x64
+ 818: 3c03ffff lui v1,0xffff
+ 81c: 34631234 ori v1,v1,0x1234
+ 820: 1c600005 bgtz v1,0x838
+ 824: a28a0000 sb t2,0(s4)
+ 828: a28b0000 sb t3,0(s4)
+ 82c: 1c400002 bgtz v0,0x838
+ 830: a28c0000 sb t4,0(s4)
+ 834: a2960000 sb s6,0(s4)
+ 838: a28d0000 sb t5,0(s4)
+ 83c: a2970000 sb s7,0(s4)
+ 840: a2950000 sb s5,0(s4)
+ 844: 34020067 li v0,0x67
+ 848: a2820000 sb v0,0(s4)
+ 84c: 340a0041 li t2,0x41
+ 850: 340b0042 li t3,0x42
+ 854: 340c0043 li t4,0x43
+ 858: 340d0044 li t5,0x44
+ 85c: 34020064 li v0,0x64
+ 860: 3c03ffff lui v1,0xffff
+ 864: 34631234 ori v1,v1,0x1234
+ 868: 18400005 blez v0,0x880
+ 86c: a28a0000 sb t2,0(s4)
+ 870: a28b0000 sb t3,0(s4)
+ 874: 18600002 blez v1,0x880
+ 878: a28c0000 sb t4,0(s4)
+ 87c: a2960000 sb s6,0(s4)
+ 880: 18000002 blez zero,0x88c
+ 884: 00000000 nop
+ 888: a2960000 sb s6,0(s4)
+ 88c: a28d0000 sb t5,0(s4)
+ 890: a2970000 sb s7,0(s4)
+ 894: a2950000 sb s5,0(s4)
+ 898: 34020068 li v0,0x68
+ 89c: a2820000 sb v0,0(s4)
+ 8a0: 340a0041 li t2,0x41
+ 8a4: 340b0042 li t3,0x42
+ 8a8: 340c0043 li t4,0x43
+ 8ac: 340d0044 li t5,0x44
+ 8b0: 340e0045 li t6,0x45
+ 8b4: 34020064 li v0,0x64
+ 8b8: 3c03ffff lui v1,0xffff
+ 8bc: 34631234 ori v1,v1,0x1234
+ 8c0: 34040000 li a0,0x0
+ 8c4: 04400005 bltz v0,0x8dc
+ 8c8: a28a0000 sb t2,0(s4)
+ 8cc: a28b0000 sb t3,0(s4)
+ 8d0: 04600002 bltz v1,0x8dc
+ 8d4: a28c0000 sb t4,0(s4)
+ 8d8: a2960000 sb s6,0(s4)
+ 8dc: 04800002 bltz a0,0x8e8
+ 8e0: 00000000 nop
+ 8e4: a28d0000 sb t5,0(s4)
+ 8e8: a28e0000 sb t6,0(s4)
+ 8ec: a2970000 sb s7,0(s4)
+ 8f0: a2950000 sb s5,0(s4)
+ 8f4: 34020069 li v0,0x69
+ 8f8: a2820000 sb v0,0(s4)
+ 8fc: 340a0041 li t2,0x41
+ 900: 340b0042 li t3,0x42
+ 904: 340c0043 li t4,0x43
+ 908: 340d0044 li t5,0x44
+ 90c: 340e0045 li t6,0x45
+ 910: 340f0058 li t7,0x58
+ 914: 3c03ffff lui v1,0xffff
+ 918: 34631234 ori v1,v1,0x1234
+ 91c: 04100008 bltzal zero,0x940
+ 920: 00000000 nop
+ 924: a28a0000 sb t2,0(s4)
+ 928: 04700005 bltzal v1,0x940
+ 92c: 00000000 nop
+ 930: a28d0000 sb t5,0(s4)
+ 934: 10000006 b 0x950
+ 938: a28e0000 sb t6,0(s4)
+ 93c: a28f0000 sb t7,0(s4)
+ 940: a28b0000 sb t3,0(s4)
+ 944: 03e00008 jr ra
+ 948: a28c0000 sb t4,0(s4)
+ 94c: a2960000 sb s6,0(s4)
+ 950: a2970000 sb s7,0(s4)
+ 954: a2950000 sb s5,0(s4)
+ 958: 3402006a li v0,0x6a
+ 95c: a2820000 sb v0,0(s4)
+ 960: 340a0041 li t2,0x41
+ 964: 340b0042 li t3,0x42
+ 968: 340c0043 li t4,0x43
+ 96c: 340d0044 li t5,0x44
+ 970: 34020064 li v0,0x64
+ 974: 3403007b li v1,0x7b
+ 978: 3404007b li a0,0x7b
+ 97c: 14640005 bne v1,a0,0x994
+ 980: a28a0000 sb t2,0(s4)
+ 984: a28b0000 sb t3,0(s4)
+ 988: 14430002 bne v0,v1,0x994
+ 98c: a28c0000 sb t4,0(s4)
+ 990: a2960000 sb s6,0(s4)
+ 994: a28d0000 sb t5,0(s4)
+ 998: a2970000 sb s7,0(s4)
+ 99c: a2950000 sb s5,0(s4)
+ 9a0: 3402006b li v0,0x6b
+ 9a4: a2820000 sb v0,0(s4)
+ 9a8: 340a0041 li t2,0x41
+ 9ac: 340b0042 li t3,0x42
+ 9b0: 340f0058 li t7,0x58
+ 9b4: 08000270 j 0x9c0
+ 9b8: a28a0000 sb t2,0(s4)
+ 9bc: a28f0000 sb t7,0(s4)
+ 9c0: a28b0000 sb t3,0(s4)
+ 9c4: a2970000 sb s7,0(s4)
+ 9c8: a2950000 sb s5,0(s4)
+ 9cc: 3402006c li v0,0x6c
+ 9d0: a2820000 sb v0,0(s4)
+ 9d4: 340a0041 li t2,0x41
+ 9d8: 340b0042 li t3,0x42
+ 9dc: 340c0043 li t4,0x43
+ 9e0: 340d0044 li t5,0x44
+ 9e4: 340e0045 li t6,0x45
+ 9e8: 340f0058 li t7,0x58
+ 9ec: 0c000281 jal 0xa04
+ 9f0: a28a0000 sb t2,0(s4)
+ 9f4: a28d0000 sb t5,0(s4)
+ 9f8: 10000006 b 0xa14
+ 9fc: a28e0000 sb t6,0(s4)
+ a00: a28f0000 sb t7,0(s4)
+ a04: a28b0000 sb t3,0(s4)
+ a08: 03e00008 jr ra
+ a0c: a28c0000 sb t4,0(s4)
+ a10: a2960000 sb s6,0(s4)
+ a14: a2970000 sb s7,0(s4)
+ a18: a2950000 sb s5,0(s4)
+ a1c: 3402006d li v0,0x6d
+ a20: a2820000 sb v0,0(s4)
+ a24: 340a0041 li t2,0x41
+ a28: 340b0042 li t3,0x42
+ a2c: 340c0043 li t4,0x43
+ a30: 340d0044 li t5,0x44
+ a34: 340e0045 li t6,0x45
+ a38: 340f0058 li t7,0x58
+ a3c: 3c030000 lui v1,0x0
+ a40: 24630a5c addiu v1,v1,2652
+ a44: 0060f809 jalr v1
+ a48: a28a0000 sb t2,0(s4)
+ a4c: a28d0000 sb t5,0(s4)
+ a50: 10000006 b 0xa6c
+ a54: a28e0000 sb t6,0(s4)
+ a58: a28f0000 sb t7,0(s4)
+ a5c: a28b0000 sb t3,0(s4)
+ a60: 03e00008 jr ra
+ a64: a28c0000 sb t4,0(s4)
+ a68: a2960000 sb s6,0(s4)
+ a6c: a2970000 sb s7,0(s4)
+ a70: a2950000 sb s5,0(s4)
+ a74: 3402006e li v0,0x6e
+ a78: a2820000 sb v0,0(s4)
+ a7c: 340a0041 li t2,0x41
+ a80: 340b0042 li t3,0x42
+ a84: 340f0058 li t7,0x58
+ a88: 3c030000 lui v1,0x0
+ a8c: 24630a9c addiu v1,v1,2716
+ a90: 00600008 jr v1
+ a94: a28a0000 sb t2,0(s4)
+ a98: a28f0000 sb t7,0(s4)
+ a9c: a28b0000 sb t3,0(s4)
+ aa0: a2970000 sb s7,0(s4)
+ aa4: a2950000 sb s5,0(s4)
+ aa8: 3402006f li v0,0x6f
+ aac: a2820000 sb v0,0(s4)
+ ab0: 34020041 li v0,0x41
+ ab4: 00000000 nop
+ ab8: a2820000 sb v0,0(s4)
+ abc: a2970000 sb s7,0(s4)
+ ac0: a2950000 sb s5,0(s4)
+ ac4: 3402004c li v0,0x4c
+ ac8: a2820000 sb v0,0(s4)
+ acc: 3402006f li v0,0x6f
+ ad0: a2820000 sb v0,0(s4)
+ ad4: 34020061 li v0,0x61
+ ad8: a2820000 sb v0,0(s4)
+ adc: 34020064 li v0,0x64
+ ae0: a2820000 sb v0,0(s4)
+ ae4: a2970000 sb s7,0(s4)
+ ae8: a2950000 sb s5,0(s4)
+ aec: 34020061 li v0,0x61
+ af0: a2820000 sb v0,0(s4)
+ af4: 00181025 or v0,zero,t8
+ af8: 3c034142 lui v1,0x4142
+ afc: 34634344 ori v1,v1,0x4344
+ b00: ac430010 sw v1,16(v0)
+ b04: 80440010 lb a0,16(v0)
+ b08: a2840000 sb a0,0(s4)
+ b0c: 80440011 lb a0,17(v0)
+ b10: a2840000 sb a0,0(s4)
+ b14: 80440012 lb a0,18(v0)
+ b18: a2840000 sb a0,0(s4)
+ b1c: 80420013 lb v0,19(v0)
+ b20: a2820000 sb v0,0(s4)
+ b24: a2970000 sb s7,0(s4)
+ b28: a2950000 sb s5,0(s4)
+ b2c: 34020062 li v0,0x62
+ b30: a2820000 sb v0,0(s4)
+ b34: 00181025 or v0,zero,t8
+ b38: 3c034142 lui v1,0x4142
+ b3c: 34634344 ori v1,v1,0x4344
+ b40: ac430010 sw v1,16(v0)
+ b44: 80440010 lb a0,16(v0)
+ b48: a2840000 sb a0,0(s4)
+ b4c: 80440011 lb a0,17(v0)
+ b50: a2840000 sb a0,0(s4)
+ b54: 80440012 lb a0,18(v0)
+ b58: a2840000 sb a0,0(s4)
+ b5c: 80420013 lb v0,19(v0)
+ b60: a2820000 sb v0,0(s4)
+ b64: a2970000 sb s7,0(s4)
+ b68: a2950000 sb s5,0(s4)
+ b6c: 34020063 li v0,0x63
+ b70: a2820000 sb v0,0(s4)
+ b74: 00181025 or v0,zero,t8
+ b78: 3c030041 lui v1,0x41
+ b7c: 34630042 ori v1,v1,0x42
+ b80: ac430010 sw v1,16(v0)
+ b84: 84440010 lh a0,16(v0)
+ b88: a2840000 sb a0,0(s4)
+ b8c: 84420012 lh v0,18(v0)
+ b90: a2820000 sb v0,0(s4)
+ b94: a2970000 sb s7,0(s4)
+ b98: a2950000 sb s5,0(s4)
+ b9c: 34020064 li v0,0x64
+ ba0: a2820000 sb v0,0(s4)
+ ba4: 00181025 or v0,zero,t8
+ ba8: 3c030041 lui v1,0x41
+ bac: 34630042 ori v1,v1,0x42
+ bb0: ac430010 sw v1,16(v0)
+ bb4: 84440010 lh a0,16(v0)
+ bb8: a2840000 sb a0,0(s4)
+ bbc: 84420012 lh v0,18(v0)
+ bc0: a2820000 sb v0,0(s4)
+ bc4: a2970000 sb s7,0(s4)
+ bc8: a2950000 sb s5,0(s4)
+ bcc: 34020065 li v0,0x65
+ bd0: a2820000 sb v0,0(s4)
+ bd4: 00181025 or v0,zero,t8
+ bd8: 24030041 li v1,65
+ bdc: ac430010 sw v1,16(v0)
+ be0: 34030000 li v1,0x0
+ be4: 8c420010 lw v0,16(v0)
+ be8: a2820000 sb v0,0(s4)
+ bec: a2970000 sb s7,0(s4)
+ bf0: a2950000 sb s5,0(s4)
+ bf4: 34020066 li v0,0x66
+ bf8: a2820000 sb v0,0(s4)
+ bfc: 00181025 or v0,zero,t8
+ c00: 24030041 li v1,65
+ c04: ac430010 sw v1,16(v0)
+ c08: 34030000 li v1,0x0
+ c0c: 88420010 lwl v0,16(v0)
+ c10: 98420010 lwr v0,16(v0)
+ c14: a2820000 sb v0,0(s4)
+ c18: a2970000 sb s7,0(s4)
+ c1c: a2950000 sb s5,0(s4)
+ c20: 34020067 li v0,0x67
+ c24: a2820000 sb v0,0(s4)
+ c28: 34020041 li v0,0x41
+ c2c: a2820000 sb v0,0(s4)
+ c30: a2970000 sb s7,0(s4)
+ c34: a2950000 sb s5,0(s4)
+ c38: 34020068 li v0,0x68
+ c3c: a2820000 sb v0,0(s4)
+ c40: 00182025 or a0,zero,t8
+ c44: 34024142 li v0,0x4142
+ c48: a4820010 sh v0,16(a0)
+ c4c: 80830010 lb v1,16(a0)
+ c50: a2830000 sb v1,0(s4)
+ c54: 80820011 lb v0,17(a0)
+ c58: a2820000 sb v0,0(s4)
+ c5c: a2970000 sb s7,0(s4)
+ c60: a2950000 sb s5,0(s4)
+ c64: 34020069 li v0,0x69
+ c68: a2820000 sb v0,0(s4)
+ c6c: 00181025 or v0,zero,t8
+ c70: 3c034142 lui v1,0x4142
+ c74: 34634344 ori v1,v1,0x4344
+ c78: ac430010 sw v1,16(v0)
+ c7c: 80440010 lb a0,16(v0)
+ c80: a2840000 sb a0,0(s4)
+ c84: 80440011 lb a0,17(v0)
+ c88: a2840000 sb a0,0(s4)
+ c8c: 80440012 lb a0,18(v0)
+ c90: a2840000 sb a0,0(s4)
+ c94: 80420013 lb v0,19(v0)
+ c98: a2820000 sb v0,0(s4)
+ c9c: a2970000 sb s7,0(s4)
+ ca0: a2950000 sb s5,0(s4)
+ ca4: 3402006a li v0,0x6a
+ ca8: a2820000 sb v0,0(s4)
+ cac: 00181025 or v0,zero,t8
+ cb0: 3c034142 lui v1,0x4142
+ cb4: 34634344 ori v1,v1,0x4344
+ cb8: a8430010 swl v1,16(v0)
+ cbc: b8430010 swr v1,16(v0)
+ cc0: 80440010 lb a0,16(v0)
+ cc4: a2840000 sb a0,0(s4)
+ cc8: 80440011 lb a0,17(v0)
+ ccc: a2840000 sb a0,0(s4)
+ cd0: 80440012 lb a0,18(v0)
+ cd4: a2840000 sb a0,0(s4)
+ cd8: 80420013 lb v0,19(v0)
+ cdc: a2820000 sb v0,0(s4)
+ ce0: a2970000 sb s7,0(s4)
+ ce4: a2950000 sb s5,0(s4)
+ ce8: 3402004c li v0,0x4c
+ cec: a2820000 sb v0,0(s4)
+ cf0: 3402006f li v0,0x6f
+ cf4: a2820000 sb v0,0(s4)
+ cf8: 34020067 li v0,0x67
+ cfc: a2820000 sb v0,0(s4)
+ d00: 34020069 li v0,0x69
+ d04: a2820000 sb v0,0(s4)
+ d08: 34020063 li v0,0x63
+ d0c: a2820000 sb v0,0(s4)
+ d10: a2970000 sb s7,0(s4)
+ d14: a2950000 sb s5,0(s4)
+ d18: 34020061 li v0,0x61
+ d1c: a2820000 sb v0,0(s4)
+ d20: 34020741 li v0,0x741
+ d24: 340360f3 li v1,0x60f3
+ d28: 00432024 and a0,v0,v1
+ d2c: a2840000 sb a0,0(s4)
+ d30: a2970000 sb s7,0(s4)
+ d34: a2950000 sb s5,0(s4)
+ d38: 34020062 li v0,0x62
+ d3c: a2820000 sb v0,0(s4)
+ d40: 34020741 li v0,0x741
+ d44: 304460f3 andi a0,v0,0x60f3
+ d48: a2840000 sb a0,0(s4)
+ d4c: a2970000 sb s7,0(s4)
+ d50: a2950000 sb s5,0(s4)
+ d54: 34020063 li v0,0x63
+ d58: a2820000 sb v0,0(s4)
+ d5c: 3c020041 lui v0,0x41
+ d60: 00021c02 srl v1,v0,0x10
+ d64: a2830000 sb v1,0(s4)
+ d68: a2970000 sb s7,0(s4)
+ d6c: a2950000 sb s5,0(s4)
+ d70: 34020064 li v0,0x64
+ d74: a2820000 sb v0,0(s4)
+ d78: 3c02f0ff lui v0,0xf0ff
+ d7c: 3442f08e ori v0,v0,0xf08e
+ d80: 3c030f0f lui v1,0xf0f
+ d84: 34630f30 ori v1,v1,0xf30
+ d88: 00432027 nor a0,v0,v1
+ d8c: a2840000 sb a0,0(s4)
+ d90: a2970000 sb s7,0(s4)
+ d94: a2950000 sb s5,0(s4)
+ d98: 34020065 li v0,0x65
+ d9c: a2820000 sb v0,0(s4)
+ da0: 34020040 li v0,0x40
+ da4: 34030001 li v1,0x1
+ da8: 00432025 or a0,v0,v1
+ dac: a2840000 sb a0,0(s4)
+ db0: a2970000 sb s7,0(s4)
+ db4: a2950000 sb s5,0(s4)
+ db8: 34020066 li v0,0x66
+ dbc: a2820000 sb v0,0(s4)
+ dc0: 34020040 li v0,0x40
+ dc4: 34440001 ori a0,v0,0x1
+ dc8: a2840000 sb a0,0(s4)
+ dcc: a2970000 sb s7,0(s4)
+ dd0: a2950000 sb s5,0(s4)
+ dd4: 34020067 li v0,0x67
+ dd8: a2820000 sb v0,0(s4)
+ ddc: 3402f043 li v0,0xf043
+ de0: 3403f002 li v1,0xf002
+ de4: 00432026 xor a0,v0,v1
+ de8: a2840000 sb a0,0(s4)
+ dec: a2970000 sb s7,0(s4)
+ df0: a2950000 sb s5,0(s4)
+ df4: 34020068 li v0,0x68
+ df8: a2820000 sb v0,0(s4)
+ dfc: 3402f043 li v0,0xf043
+ e00: 3844f002 xori a0,v0,0xf002
+ e04: a2840000 sb a0,0(s4)
+ e08: a2970000 sb s7,0(s4)
+ e0c: a2950000 sb s5,0(s4)
+ e10: 08000384 j 0xe10
+ e14: 00000000 nop
+ e18: 00000000 nop
+ e1c: 00000000 nop
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem.data
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem_init.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem_init.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_data_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,7 @@
+`ifndef __DATA_INIT__
+`define __DATA_INIT__
+
+`define INIT_DATA_MEM defparam bank0.bank0.INIT_00 = 256'h0
+
+
+`endif
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem.asm
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem.code
===================================================================
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem_init.v
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem_init.v
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_inst_mem_init.v
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,7 @@
+`ifndef __INST_INIT__
+`define __INST_INIT__
+
+`define INIT_INST_MEM defparam bank0.INIT_00 = 256'h0
+
+
+`endif
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.asm
===================================================================
---
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.asm
(rev 0)
+++
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.asm
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,208 @@
+##################################################################
+# TITLE: Focus on store word !!!! Tester
+# DESCRIPTION:
+# This test assumes that address 0x00800010 is the UART write register
+# Successful tests will print out "A" or "AB" or "ABC" or ....
+# Missing letters or letters out of order indicate a failure.
+##################################################################
+
+.text 0x20
+.set noreorder
+
+ #These four instructions must be the first instructions
+ #convert.exe will correctly initialize $gp
+ lui $gp,0
+ ori $gp,$gp,0
+ #convert.exe will set $4=.sbss_start $5=.bss_end
+ lui $4,0
+ ori $4,$4,0
+ lui $5,0
+ ori $5,$5,0
+ lui $sp,0x0080
+ ori $sp,$sp,0x0000
+
+ lui $20,0x0080
+ ori $20,$20,0x0010 #serial port write address
+ ori $21,$0,'\n' #<CR> letter
+ ori $22,$0,'X' #'X' letter
+ ori $23,$0,'\r'
+ # lui $24,0x0080
+ ori $24,$24,0x0004 #temp memory
+
+
+ ######################################
+ #Load, Store, and Memory Control Instructions
+ ######################################
+ ori $2,$0,'L'
+ sb $2,0($20)
+ ori $2,$0,'o'
+ sb $2,0($20)
+ ori $2,$0,'a'
+ sb $2,0($20)
+ ori $2,$0,'d'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #a: LB
+ ori $2,$0,'a'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ ori $2,$0,'X'
+ sb $2,0($20)
+
+ #b: LBU
+ ori $2,$0,'b'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ ori $2,$0,'X'
+ sb $2,0($20)
+
+
+ #c: LH
+ ori $2,$0,'c'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x00410042
+ sw $3,16($2)
+ lh $4,16($2)
+ sb $4,0($20)
+ lh $2,18($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ ori $2,$0,'X'
+ sb $2,0($20)
+
+ #d: LHU
+ ori $2,$0,'d'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x00410042
+ sw $3,16($2)
+ lh $4,16($2)
+ sb $4,0($20)
+ lh $2,18($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #e: LW
+ ori $2,$0,'e'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,'A'
+ sw $3,16($2)
+ ori $3,$0,0
+ lw $2,16($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #f: LWL & LWR
+ ori $2,$0,'f'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,'A'
+ sw $3,16($2)
+ ori $3,$0,0
+ lwl $2,16($2)
+ lwr $2,16($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #g: SB
+ ori $2,$0,'g'
+ sb $2,0($20)
+ ori $2,$0,'A'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #h: SH
+ ori $2,$0,'h'
+ sb $2,0($20)
+ or $4,$0,$24
+ ori $2,$0,0x4142
+ sh $2,16($4)
+ lb $3,16($4)
+ sb $3,0($20)
+ lb $2,17($4)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #i: SW
+ ori $2,$0,'i'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ sw $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #j: SWL & SWR
+ ori $2,$0,'j'
+ sb $2,0($20)
+ or $2,$0,$24
+ li $3,0x41424344
+ swl $3,16($2)
+ swr $3,16($2)
+ lb $4,16($2)
+ sb $4,0($20)
+ lb $4,17($2)
+ sb $4,0($20)
+ lb $4,18($2)
+ sb $4,0($20)
+ lb $2,19($2)
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
+
+ #done
+ ori $2,$0,'D'
+ sb $2,0($20)
+ ori $2,$0,'O'
+ sb $2,0($20)
+ ori $2,$0,'N'
+ sb $2,0($20)
+ ori $2,$0,'E'
+ sb $2,0($20)
+ sb $23,0($20)
+ sb $21,0($20)
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.s
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/test_code_sw.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,174 @@
+
+strip_test_code_sw: file format elf32-tradlittlemips
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 3c1c0000 lui gp,0x0
+ 4: 379c0000 ori gp,gp,0x0
+ 8: 3c040000 lui a0,0x0
+ c: 34840000 ori a0,a0,0x0
+ 10: 3c050000 lui a1,0x0
+ 14: 34a50000 ori a1,a1,0x0
+ 18: 3c1d0080 lui sp,0x80
+ 1c: 37bd0000 ori sp,sp,0x0
+ 20: 3c140080 lui s4,0x80
+ 24: 36940010 ori s4,s4,0x10
+ 28: 3415000a li s5,0xa
+ 2c: 34160058 li s6,0x58
+ 30: 3417000d li s7,0xd
+ 34: 37180004 ori t8,t8,0x4
+ 38: 3402004c li v0,0x4c
+ 3c: a2820000 sb v0,0(s4)
+ 40: 3402006f li v0,0x6f
+ 44: a2820000 sb v0,0(s4)
+ 48: 34020061 li v0,0x61
+ 4c: a2820000 sb v0,0(s4)
+ 50: 34020064 li v0,0x64
+ 54: a2820000 sb v0,0(s4)
+ 58: a2970000 sb s7,0(s4)
+ 5c: a2950000 sb s5,0(s4)
+ 60: 34020061 li v0,0x61
+ 64: a2820000 sb v0,0(s4)
+ 68: 00181025 or v0,zero,t8
+ 6c: 3c034142 lui v1,0x4142
+ 70: 34634344 ori v1,v1,0x4344
+ 74: ac430010 sw v1,16(v0)
+ 78: 80440010 lb a0,16(v0)
+ 7c: a2840000 sb a0,0(s4)
+ 80: 80440011 lb a0,17(v0)
+ 84: a2840000 sb a0,0(s4)
+ 88: 80440012 lb a0,18(v0)
+ 8c: a2840000 sb a0,0(s4)
+ 90: 80420013 lb v0,19(v0)
+ 94: a2820000 sb v0,0(s4)
+ 98: a2970000 sb s7,0(s4)
+ 9c: a2950000 sb s5,0(s4)
+ a0: 34020058 li v0,0x58
+ a4: a2820000 sb v0,0(s4)
+ a8: 34020062 li v0,0x62
+ ac: a2820000 sb v0,0(s4)
+ b0: 00181025 or v0,zero,t8
+ b4: 3c034142 lui v1,0x4142
+ b8: 34634344 ori v1,v1,0x4344
+ bc: ac430010 sw v1,16(v0)
+ c0: 80440010 lb a0,16(v0)
+ c4: a2840000 sb a0,0(s4)
+ c8: 80440011 lb a0,17(v0)
+ cc: a2840000 sb a0,0(s4)
+ d0: 80440012 lb a0,18(v0)
+ d4: a2840000 sb a0,0(s4)
+ d8: 80420013 lb v0,19(v0)
+ dc: a2820000 sb v0,0(s4)
+ e0: a2970000 sb s7,0(s4)
+ e4: a2950000 sb s5,0(s4)
+ e8: 34020058 li v0,0x58
+ ec: a2820000 sb v0,0(s4)
+ f0: 34020063 li v0,0x63
+ f4: a2820000 sb v0,0(s4)
+ f8: 00181025 or v0,zero,t8
+ fc: 3c030041 lui v1,0x41
+ 100: 34630042 ori v1,v1,0x42
+ 104: ac430010 sw v1,16(v0)
+ 108: 84440010 lh a0,16(v0)
+ 10c: a2840000 sb a0,0(s4)
+ 110: 84420012 lh v0,18(v0)
+ 114: a2820000 sb v0,0(s4)
+ 118: a2970000 sb s7,0(s4)
+ 11c: a2950000 sb s5,0(s4)
+ 120: 34020058 li v0,0x58
+ 124: a2820000 sb v0,0(s4)
+ 128: 34020064 li v0,0x64
+ 12c: a2820000 sb v0,0(s4)
+ 130: 00181025 or v0,zero,t8
+ 134: 3c030041 lui v1,0x41
+ 138: 34630042 ori v1,v1,0x42
+ 13c: ac430010 sw v1,16(v0)
+ 140: 84440010 lh a0,16(v0)
+ 144: a2840000 sb a0,0(s4)
+ 148: 84420012 lh v0,18(v0)
+ 14c: a2820000 sb v0,0(s4)
+ 150: a2970000 sb s7,0(s4)
+ 154: a2950000 sb s5,0(s4)
+ 158: 34020065 li v0,0x65
+ 15c: a2820000 sb v0,0(s4)
+ 160: 00181025 or v0,zero,t8
+ 164: 24030041 li v1,65
+ 168: ac430010 sw v1,16(v0)
+ 16c: 34030000 li v1,0x0
+ 170: 8c420010 lw v0,16(v0)
+ 174: a2820000 sb v0,0(s4)
+ 178: a2970000 sb s7,0(s4)
+ 17c: a2950000 sb s5,0(s4)
+ 180: 34020066 li v0,0x66
+ 184: a2820000 sb v0,0(s4)
+ 188: 00181025 or v0,zero,t8
+ 18c: 24030041 li v1,65
+ 190: ac430010 sw v1,16(v0)
+ 194: 34030000 li v1,0x0
+ 198: 88420010 lwl v0,16(v0)
+ 19c: 98420010 lwr v0,16(v0)
+ 1a0: a2820000 sb v0,0(s4)
+ 1a4: a2970000 sb s7,0(s4)
+ 1a8: a2950000 sb s5,0(s4)
+ 1ac: 34020067 li v0,0x67
+ 1b0: a2820000 sb v0,0(s4)
+ 1b4: 34020041 li v0,0x41
+ 1b8: a2820000 sb v0,0(s4)
+ 1bc: a2970000 sb s7,0(s4)
+ 1c0: a2950000 sb s5,0(s4)
+ 1c4: 34020068 li v0,0x68
+ 1c8: a2820000 sb v0,0(s4)
+ 1cc: 00182025 or a0,zero,t8
+ 1d0: 34024142 li v0,0x4142
+ 1d4: a4820010 sh v0,16(a0)
+ 1d8: 80830010 lb v1,16(a0)
+ 1dc: a2830000 sb v1,0(s4)
+ 1e0: 80820011 lb v0,17(a0)
+ 1e4: a2820000 sb v0,0(s4)
+ 1e8: a2970000 sb s7,0(s4)
+ 1ec: a2950000 sb s5,0(s4)
+ 1f0: 34020069 li v0,0x69
+ 1f4: a2820000 sb v0,0(s4)
+ 1f8: 00181025 or v0,zero,t8
+ 1fc: 3c034142 lui v1,0x4142
+ 200: 34634344 ori v1,v1,0x4344
+ 204: ac430010 sw v1,16(v0)
+ 208: 80440010 lb a0,16(v0)
+ 20c: a2840000 sb a0,0(s4)
+ 210: 80440011 lb a0,17(v0)
+ 214: a2840000 sb a0,0(s4)
+ 218: 80440012 lb a0,18(v0)
+ 21c: a2840000 sb a0,0(s4)
+ 220: 80420013 lb v0,19(v0)
+ 224: a2820000 sb v0,0(s4)
+ 228: a2970000 sb s7,0(s4)
+ 22c: a2950000 sb s5,0(s4)
+ 230: 3402006a li v0,0x6a
+ 234: a2820000 sb v0,0(s4)
+ 238: 00181025 or v0,zero,t8
+ 23c: 3c034142 lui v1,0x4142
+ 240: 34634344 ori v1,v1,0x4344
+ 244: a8430010 swl v1,16(v0)
+ 248: b8430010 swr v1,16(v0)
+ 24c: 80440010 lb a0,16(v0)
+ 250: a2840000 sb a0,0(s4)
+ 254: 80440011 lb a0,17(v0)
+ 258: a2840000 sb a0,0(s4)
+ 25c: 80440012 lb a0,18(v0)
+ 260: a2840000 sb a0,0(s4)
+ 264: 80420013 lb v0,19(v0)
+ 268: a2820000 sb v0,0(s4)
+ 26c: a2970000 sb s7,0(s4)
+ 270: a2950000 sb s5,0(s4)
+ 274: 34020044 li v0,0x44
+ 278: a2820000 sb v0,0(s4)
+ 27c: 3402004f li v0,0x4f
+ 280: a2820000 sb v0,0(s4)
+ 284: 3402004e li v0,0x4e
+ 288: a2820000 sb v0,0(s4)
+ 28c: 34020045 li v0,0x45
+ 290: a2820000 sb v0,0(s4)
+ 294: a2970000 sb s7,0(s4)
+ 298: a2950000 sb s5,0(s4)
+ 29c: 00000000 nop
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.c
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.c
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.c
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,14 @@
+main()
+{
+int j;
+int k;
+j = 0x69;
+k = 0;
+k = 0;
+k = 0;
+k = 0;
+j = 'A';
+while(1){
+k++;
+}
+}
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.o
===================================================================
(Binary files differ)
Property changes on:
gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.o
___________________________________________________________________
Name: svn:mime-type
+ application/octet-stream
Added: gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.s
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.s
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/opencores/ucsys/tools/timtest.s
2007-10-26 22:21:30 UTC (rev 6709)
@@ -0,0 +1,26 @@
+
+strip_timtest: file format elf32-tradlittlemips
+
+Disassembly of section .text:
+
+00000000 <.text>:
+ 0: 3c1c0800 lui gp,0x800
+ 4: 279c0000 addiu gp,gp,0
+ 8: 0399e021 addu gp,gp,t9
+ c: 27bdffe8 addiu sp,sp,-24
+ 10: afbe0010 sw s8,16(sp)
+ 14: 03a0f021 move s8,sp
+ 18: 24020069 li v0,105
+ 1c: afc20008 sw v0,8(s8)
+ 20: afc0000c sw zero,12(s8)
+ 24: afc0000c sw zero,12(s8)
+ 28: afc0000c sw zero,12(s8)
+ 2c: afc0000c sw zero,12(s8)
+ 30: 24020041 li v0,65
+ 34: afc20008 sw v0,8(s8)
+ 38: 8fc2000c lw v0,12(s8)
+ 3c: 00000000 nop
+ 40: 24420001 addiu v0,v0,1
+ 44: 1000fffc b 0x38
+ 48: afc2000c sw v0,12(s8)
+ 4c: 00000000 nop
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- [Commit-gnuradio] r6709 - in gnuradio/branches/developers/matt/u2f/opencores/ucsys: . src src/tb src/uart/tb src/ucore src/ucore/tb tools,
matt <=