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[Commit-gnuradio] r6662 - in gnuradio/branches/developers/zhuochen/inban
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From: |
zhuochen |
|
Subject: |
[Commit-gnuradio] r6662 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 toplevel/usrp_inband_usb |
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Date: |
Sun, 21 Oct 2007 21:25:36 -0600 (MDT) |
Author: zhuochen
Date: 2007-10-21 21:25:36 -0600 (Sun, 21 Oct 2007)
New Revision: 6662
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_ram.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
New indentation and disabling of old register access
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,106 +1,106 @@
module chan_fifo_reader
- ( reset, tx_clock, tx_strobe, adc_time, samples_format,
+ (reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
- input wire reset ;
- input wire tx_clock ;
- input wire tx_strobe ; //signal to output tx_i and
tx_q
- input wire [31:0] adc_time ; //current time
- input wire [3:0] samples_format ;// not useful at this
point
- input wire [31:0] fifodata ; //the data input
- input wire pkt_waiting ; //signal the next packet is
ready
- output reg rdreq ; //actually an ack to the current
fifodata
- output reg skip ; //finish reading current packet
- output reg [15:0] tx_q ; //top 16 bit output of fifodata
- output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
- output reg underrun ;
- output reg tx_empty ; //cause 0 to be the output
- input wire [31:0] rssi;
- input wire [31:0] threshhold;
- input wire [31:0] rssi_wait;
+ input wire reset ;
+ input wire tx_clock ;
+ input wire tx_strobe ; //signal to output tx_i and
tx_q
+ input wire [31:0] adc_time ; //current time
+ input wire [3:0] samples_format ;// not useful at this point
+ input wire [31:0] fifodata ; //the data input
+ input wire pkt_waiting ; //signal the next packet is
ready
+ output reg rdreq ; //actually an ack to the current
fifodata
+ output reg skip ; //finish reading current packet
+ output reg [15:0] tx_q ; //top 16 bit output of fifodata
+ output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
+ output reg underrun ;
+ output reg tx_empty ; //cause 0 to be the output
+ input wire [31:0] rssi;
+ input wire [31:0] threshhold;
+ input wire [31:0] rssi_wait;
- output wire [14:0] debug;
- assign debug = {reader_state, trash, skip, timestamp[4:0],
adc_time[4:0]};
- // Should not be needed if adc clock rate < tx clock rate
- // Used only to debug
- `define JITTER 5
+ output wire [14:0] debug;
+ assign debug = {reader_state, trash, skip, timestamp[4:0], adc_time[4:0]};
+
+ // Should not be needed if adc clock rate < tx clock rate
+ // Used only to debug
+ `define JITTER 5
- //Samples format
- // 16 bits interleaved complex samples
- `define QI16 4'b0
+ //Samples format
+ // 16 bits interleaved complex samples
+ `define QI16 4'b0
- // States
- parameter IDLE = 3'd0;
- parameter HEADER = 3'd1;
- parameter TIMESTAMP = 3'd2;
- parameter WAIT = 3'd3;
- parameter WAITSTROBE = 3'd4;
- parameter SEND = 3'd5;
+ // States
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter TIMESTAMP = 3'd2;
+ parameter WAIT = 3'd3;
+ parameter WAITSTROBE = 3'd4;
+ parameter SEND = 3'd5;
- // Header format
- `define PAYLOAD 8:2
- `define ENDOFBURST 27
- `define STARTOFBURST 28
- `define RSSI_FLAG 26
+ // Header format
+ `define PAYLOAD 8:2
+ `define ENDOFBURST 27
+ `define STARTOFBURST 28
+ `define RSSI_FLAG 26
- /* State registers */
- reg [2:0] reader_state;
- /* Local registers */
- reg [6:0] payload_len;
- reg [6:0] read_len;
- reg [31:0] timestamp;
- reg burst;
- reg trash;
- reg
rssi_flag;
- reg [31:0] time_wait;
+ /* State registers */
+ reg [2:0] reader_state;
+ /* Local registers */
+ reg [6:0] payload_len;
+ reg [6:0] read_len;
+ reg [31:0] timestamp;
+ reg burst;
+ reg trash;
+ reg rssi_flag;
+ reg [31:0] time_wait;
- always @(posedge tx_clock)
- begin
- if (reset)
- begin
- reader_state <= IDLE;
- rdreq <= 0;
- skip <= 0;
- underrun <= 0;
- burst <= 0;
- tx_empty <= 1;
- tx_q <= 0;
- tx_i <= 0;
- trash <= 0;
- rssi_flag <= 0;
- time_wait <= 0;
+ always @(posedge tx_clock)
+ begin
+ if (reset)
+ begin
+ reader_state <= IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ underrun <= 0;
+ burst <= 0;
+ tx_empty <= 1;
+ tx_q <= 0;
+ tx_i <= 0;
+ trash <= 0;
+ rssi_flag <= 0;
+ time_wait <= 0;
end
else
- begin
+ begin
case (reader_state)
- IDLE:
+ IDLE:
begin
- /*
- * reset all the variables and wait for a
tx_strobe
- * it is assumed that the ram connected to this
fifo_reader
- * is a short hand fifo meaning that the header
to the next packet
- * is already available to this fifo_reader
when pkt_waiting is on
- */
- skip <=0;
- time_wait <= 0;
- if (pkt_waiting == 1)
- begin
- reader_state <= HEADER;
- rdreq <= 1;
- underrun <= 0;
- end
- if (burst == 1 && pkt_waiting == 0)
- underrun <= 1;
-
- if (tx_strobe == 1)
- tx_empty <= 1 ;
+ /*
+ * reset all the variables and wait for a tx_strobe
+ * it is assumed that the ram connected to this fifo_reader
+ * is a short hand fifo meaning that the header to the next
packet
+ * is already available to this fifo_reader when pkt_waiting is
on
+ */
+ skip <=0;
+ time_wait <= 0;
+ if (pkt_waiting == 1)
+ begin
+ reader_state <= HEADER;
+ rdreq <= 1;
+ underrun <= 0;
+ end
+ if (burst == 1 && pkt_waiting == 0)
+ underrun <= 1;
+ if (tx_strobe == 1)
+ tx_empty <= 1 ;
end
- /* Process header */
+ /* Process header */
HEADER:
- begin
+ begin
if (tx_strobe == 1)
tx_empty <= 1 ;
@@ -114,68 +114,65 @@
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
- if (trash == 1 &&
fifodata[`STARTOFBURST] == 0)
- begin
- skip <= 1;
- reader_state <= IDLE;
- rdreq <= 0;
- end
- else
- begin
- payload_len <= fifodata[`PAYLOAD] ;
- read_len <= 0;
- rdreq <= 1;
- reader_state <= TIMESTAMP;
- end
- end
+ if (trash == 1 && fifodata[`STARTOFBURST] == 0)
+ begin
+ skip <= 1;
+ reader_state <= IDLE;
+ rdreq <= 0;
+ end
+ else
+ begin
+ payload_len <= fifodata[`PAYLOAD] ;
+ read_len <= 0;
+ rdreq <= 1;
+ reader_state <= TIMESTAMP;
+ end
+ end
TIMESTAMP:
- begin
+ begin
timestamp <= fifodata;
reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
rdreq <= 0;
- end
+ end
- // Decide if we wait, send or discard samples
+ // Decide if we wait, send or discard samples
WAIT:
- begin
+ begin
if (tx_strobe == 1)
tx_empty <= 1 ;
time_wait <= time_wait + 32'd1;
- // Outdated
+ // Outdated
if ((timestamp < adc_time) ||
- (time_wait >= rssi_wait
&& rssi_wait != 0 && rssi_flag))
+ (time_wait >= rssi_wait && rssi_wait != 0 && rssi_flag))
begin
- trash <= 1;
- reader_state <= IDLE;
- skip <= 1;
+ trash <= 1;
+ reader_state <= IDLE;
+ skip <= 1;
end
// Let's send it
else if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
- begin
- if (rssi <= threshhold ||
rssi_flag == 0)
- begin
- trash <= 0;
- reader_state <= WAITSTROBE;
- end
- else
- reader_state <= WAIT;
- end
- else
- reader_state <= WAIT;
- // Wait a little bit more
- //else if (timestamp > adc_time + `JITTER)
- // reader_state <= WAIT;
- end
+ begin
+ if (rssi <= threshhold || rssi_flag == 0)
+ begin
+ trash <= 0;
+ reader_state <= WAITSTROBE;
+ end
+ else
+ reader_state <= WAIT;
+ end
+ else
+ reader_state <= WAIT;
+ end
// Wait for the transmit chain to be ready
WAITSTROBE:
- begin
+ begin
// If end of payload...
if (read_len == payload_len)
begin
@@ -189,11 +186,11 @@
reader_state <= SEND;
rdreq <= 1;
end
- end
+ end
- // Send the samples to the tx_chain
+ // Send the samples to the tx_chain
SEND:
- begin
+ begin
reader_state <= WAITSTROBE;
read_len <= read_len + 7'd1;
tx_empty <= 0;
@@ -213,13 +210,13 @@
tx_q <= fifodata[31:16];
end
endcase
- end
+ end
default:
- begin
- //error handling
+ begin
+ //error handling
reader_state <= IDLE;
- end
+ end
endcase
end
end
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_ram.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_ram.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/channel_ram.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,114 +1,107 @@
module channel_ram
- ( // System
- input txclk,
- input reset,
+ ( // System
+ input txclk, input reset,
+ // USB side
+ input [31:0] datain, input WR, input WR_done, output have_space,
+ // Reader side
+ output [31:0] dataout, input RD, input RD_done, output packet_waiting);
- // USB side
- input [31:0] datain,
- input WR,
- input WR_done,
- output have_space,
-
- // Reader side
- output [31:0] dataout,
- input RD,
- input RD_done,
- output packet_waiting);
+ reg [6:0] wr_addr, rd_addr;
+ reg [1:0] which_ram_wr, which_ram_rd;
+ reg [2:0] nb_packets;
- reg [6:0] wr_addr, rd_addr;
- reg [1:0] which_ram_wr, which_ram_rd;
- reg [2:0] nb_packets;
+ reg [31:0] ram0 [0:127];
+ reg [31:0] ram1 [0:127];
+ reg [31:0] ram2 [0:127];
+ reg [31:0] ram3 [0:127];
- reg [31:0] ram0 [0:127];
- reg [31:0] ram1 [0:127];
- reg [31:0] ram2 [0:127];
- reg [31:0] ram3 [0:127];
+ reg [31:0] dataout0;
+ reg [31:0] dataout1;
+ reg [31:0] dataout2;
+ reg [31:0] dataout3;
- reg [31:0] dataout0;
- reg [31:0] dataout1;
- reg [31:0] dataout2;
- reg [31:0] dataout3;
+ wire wr_done_int;
+ wire rd_done_int;
+ wire [6:0] rd_addr_final;
+ wire [1:0] which_ram_rd_final;
- wire wr_done_int;
- wire rd_done_int;
- wire [6:0] rd_addr_final;
- wire [1:0] which_ram_rd_final;
-
- // USB side
- always @(posedge txclk)
- if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+ // USB side
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
- always @(posedge txclk)
- if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
- always @(posedge txclk)
- if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
- always @(posedge txclk)
- if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
- always @(posedge txclk)
- if(reset)
- wr_addr <= 0;
- else if (WR_done)
- wr_addr <= 0;
- else if (WR)
- wr_addr <= wr_addr + 7'd1;
+ always @(posedge txclk)
+ if(reset)
+ wr_addr <= 0;
+ else if (WR_done)
+ wr_addr <= 0;
+ else if (WR)
+ wr_addr <= wr_addr + 7'd1;
- always @(posedge txclk)
- if(reset)
- which_ram_wr <= 0;
- else if (wr_done_int)
- which_ram_wr <= which_ram_wr + 2'd1;
+ always @(posedge txclk)
+ if(reset)
+ which_ram_wr <= 0;
+ else if (wr_done_int)
+ which_ram_wr <= which_ram_wr + 2'd1;
- assign have_space = (nb_packets < 3'd3);
+ assign have_space = (nb_packets < 3'd3);
- // Reader side
- // short hand fifo
- // rd_addr_final is what rd_addr is going to be next clock cycle
- // which_ram_rd_final is what which_ram_rd is going to be next clock
cycle
- always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
- always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
- always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
- always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
+ // Reader side
+ // short hand fifo
+ // rd_addr_final is what rd_addr is going to be next clock cycle
+ // which_ram_rd_final is what which_ram_rd is going to be next clock cycle
+ always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
+ always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
+ always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
+ always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
- assign dataout = (which_ram_rd_final[1]) ?
- (which_ram_rd_final[0] ?
dataout3 : dataout2) :
- (which_ram_rd_final[0] ?
dataout1 : dataout0);
+ assign dataout = (which_ram_rd_final[1]) ?
+ (which_ram_rd_final[0] ? dataout3 : dataout2) :
+ (which_ram_rd_final[0] ? dataout1 : dataout0);
- //RD_done is the only way to signal the end of one packet
- assign rd_done_int = RD_done;
+ //RD_done is the only way to signal the end of one packet
+ assign rd_done_int = RD_done;
- always @(posedge txclk)
- if (reset)
- rd_addr <= 0;
- else if (RD_done)
- rd_addr <= 0;
- else if (RD) rd_addr <= rd_addr + 7'd1;
+ always @(posedge txclk)
+ if (reset)
+ rd_addr <= 0;
+ else if (RD_done)
+ rd_addr <= 0;
+ else if (RD)
+ rd_addr <= rd_addr + 7'd1;
- assign rd_addr_final = (reset|RD_done) ? (6'd0) :
- ((RD)?(rd_addr+7'd1):rd_addr);
- always @(posedge txclk)
- if (reset)
- which_ram_rd <= 0;
- else if (rd_done_int)
- which_ram_rd <= which_ram_rd + 2'd1;
+ assign rd_addr_final = (reset|RD_done) ? (6'd0) :
+ ((RD)?(rd_addr+7'd1):rd_addr);
+
+ always @(posedge txclk)
+ if (reset)
+ which_ram_rd <= 0;
+ else if (rd_done_int)
+ which_ram_rd <= which_ram_rd + 2'd1;
- assign which_ram_rd_final = (reset) ? (2'd0):
+ assign which_ram_rd_final = (reset) ? (2'd0):
((rd_done_int) ? (which_ram_rd + 2'd1) :
which_ram_rd);
- //packet_waiting is set to zero if rd_done_int is high
- //because there is no guarantee that nb_packets will be pos.
- //assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
- assign packet_waiting = (nb_packets > 1) | ((nb_packets ==
1)&(~rd_done_int));
- always @(posedge txclk)
- if (reset)
- nb_packets <= 0;
- else if (wr_done_int & ~rd_done_int)
- nb_packets <= nb_packets + 3'd1;
- else if (rd_done_int & ~wr_done_int)
- nb_packets <= nb_packets - 3'd1;
+ //packet_waiting is set to zero if rd_done_int is high
+ //because there is no guarantee that nb_packets will be pos.
+
+ assign packet_waiting = (nb_packets > 1) | ((nb_packets ==
1)&(~rd_done_int));
+ always @(posedge txclk)
+ if (reset)
+ nb_packets <= 0;
+ else if (wr_done_int & ~rd_done_int)
+ nb_packets <= nb_packets + 3'd1;
+ else if (rd_done_int & ~wr_done_int)
+ nb_packets <= nb_packets - 3'd1;
-endmodule
\ No newline at end of file
+endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,296 +1,305 @@
-module cmd_reader(
- //System
- input reset,
- input txclk,
- input [31:0] adc_time,
- //FX2 Side
- output reg skip,
- output reg rdreq,
- input [31:0] fifodata,
- input pkt_waiting,
- //Rx side
- input rx_WR_enabled,
- output reg [15:0] rx_databus,
- output reg rx_WR,
- output reg rx_WR_done,
- //register io
- input wire [31:0] reg_data_out,
- output reg [31:0] reg_data_in,
- output reg [6:0] reg_addr,
- output reg [1:0] reg_io_enable,
- output wire [14:0] debug,
- output reg stop,
- output reg [15:0] stop_time
- );
+module cmd_reader
+ (//System
+ input reset, input txclk, input [31:0] adc_time,
+ //FX2 Side
+ output reg skip, output reg rdreq,
+ input [31:0] fifodata, input pkt_waiting,
+ //Rx side
+ input rx_WR_enabled, output reg [15:0] rx_databus,
+ output reg rx_WR, output reg rx_WR_done,
+ //register io
+ input wire [31:0] reg_data_out, output reg [31:0] reg_data_in,
+ output reg [6:0] reg_addr, output reg [1:0] reg_io_enable,
+ output wire [14:0] debug, output reg stop, output reg [15:0] stop_time);
- // States
- parameter IDLE = 4'd0;
- parameter HEADER = 4'd1;
- parameter TIMESTAMP = 4'd2;
- parameter WAIT = 4'd3;
- parameter TEST = 4'd4;
- parameter SEND = 4'd5;
- parameter PING = 4'd6;
- parameter WRITE_REG = 4'd7;
- parameter WRITE_REG_MASKED = 4'd8;
- parameter READ_REG = 4'd9;
- parameter DELAY = 4'd14;
+ // States
+ parameter IDLE = 4'd0;
+ parameter HEADER = 4'd1;
+ parameter TIMESTAMP = 4'd2;
+ parameter WAIT = 4'd3;
+ parameter TEST = 4'd4;
+ parameter SEND = 4'd5;
+ parameter PING = 4'd6;
+ parameter WRITE_REG = 4'd7;
+ parameter WRITE_REG_MASKED = 4'd8;
+ parameter READ_REG = 4'd9;
+ parameter DELAY = 4'd14;
- `define OP_PING_FIXED 8'd0
- `define OP_PING_FIXED_REPLY 8'd1
- `define OP_WRITE_REG 8'd2
- `define OP_WRITE_REG_MASKED 8'd3
- `define OP_READ_REG 8'd4
- `define OP_READ_REG_REPLY 8'd5
- `define OP_DELAY 8'd12
+ `define OP_PING_FIXED 8'd0
+ `define OP_PING_FIXED_REPLY 8'd1
+ `define OP_WRITE_REG 8'd2
+ `define OP_WRITE_REG_MASKED 8'd3
+ `define OP_READ_REG 8'd4
+ `define OP_READ_REG_REPLY 8'd5
+ `define OP_DELAY 8'd12
- reg [6:0] payload;
- reg [6:0] payload_read;
- reg [3:0] state;
- reg [15:0] high;
- reg [15:0] low;
- reg pending;
- reg [31:0] value0;
- reg [31:0] value1;
- reg [31:0] value2;
- reg [1:0] lines_in;
- reg [1:0] lines_out;
- reg [1:0] lines_out_total;
+ reg [6:0] payload;
+ reg [6:0] payload_read;
+ reg [3:0] state;
+ reg [15:0] high;
+ reg [15:0] low;
+ reg pending;
+ reg [31:0] value0;
+ reg [31:0] value1;
+ reg [31:0] value2;
+ reg [1:0] lines_in;
+ reg [1:0] lines_out;
+ reg [1:0] lines_out_total;
- `define JITTER 5
- `define OP_CODE 31:24
- `define PAYLOAD 8:2
+ `define JITTER 5
+ `define OP_CODE 31:24
+ `define PAYLOAD 8:2
- wire [7:0] ops;
- assign ops = value0[`OP_CODE];
- assign debug = {state[3:0], lines_out[1:0], pending, rx_WR,
rx_WR_enabled, value0[2:0], ops[2:0]};
+ wire [7:0] ops;
+ assign ops = value0[`OP_CODE];
+ assign debug = {state[3:0], lines_out[1:0], pending, rx_WR, rx_WR_enabled,
value0[2:0], ops[2:0]};
- always @(posedge txclk)
- if (reset)
- begin
- pending <= 0;
- state <= IDLE;
- skip <= 0;
- rdreq <= 0;
- rx_WR <= 0;
- reg_io_enable <= 0;
- reg_data_in <= 0;
- reg_addr <= 0;
- stop <= 0;
- end
- else case (state)
- IDLE : begin
- payload_read <= 0;
- skip <= 0;
- lines_in <= 0;
- if (pkt_waiting)
- begin
- state <= HEADER;
- rdreq <= 1;
- end
- end
+ always @(posedge txclk)
+ if (reset)
+ begin
+ pending <= 0;
+ state <= IDLE;
+ skip <= 0;
+ rdreq <= 0;
+ rx_WR <= 0;
+ reg_io_enable <= 0;
+ reg_data_in <= 0;
+ reg_addr <= 0;
+ stop <= 0;
+ end
+ else case (state)
+ IDLE :
+ begin
+ payload_read <= 0;
+ skip <= 0;
+ lines_in <= 0;
+ if(pkt_waiting)
+ begin
+ state <= HEADER;
+ rdreq <= 1;
+ end
+ end
+
+ HEADER :
+ begin
+ payload <= fifodata[`PAYLOAD];
+ state <= TIMESTAMP;
+ end
+
+ TIMESTAMP :
+ begin
+ value0 <= fifodata;
+ state <= WAIT;
+ rdreq <= 0;
+ end
- HEADER : begin
- payload <= fifodata[`PAYLOAD];
- state <= TIMESTAMP;
- end
+ WAIT :
+ begin
+ // Let's send it
+ if ((value0 <= adc_time + `JITTER
+ && value0 > adc_time)
+ || value0 == 32'hFFFFFFFF)
+ state <= TEST;
+ // Wait a little bit more
+ else if (value0 > adc_time + `JITTER)
+ state <= WAIT;
+ // Outdated
+ else if (value0 < adc_time)
+ begin
+ state <= IDLE;
+ skip <= 1;
+ end
+ end
- TIMESTAMP : begin
- value0 <= fifodata;
- state <= WAIT;
- rdreq <= 0;
- end
-
- WAIT : begin
- // Let's send it
- if ((value0 <= adc_time + `JITTER
- && value0 > adc_time)
- || value0 == 32'hFFFFFFFF)
- state <= TEST;
- // Wait a little bit more
- else if (value0 > adc_time + `JITTER)
- state <= WAIT;
- // Outdated
- else if (value0 < adc_time)
- begin
+ TEST :
+ begin
+ reg_io_enable <= 0;
+ rx_WR <= 0;
+ rx_WR_done <= 1;
+ stop <= 0;
+ if (payload_read == payload)
+ begin
+ skip <= 1;
+ state <= IDLE;
+ rdreq <= 0;
+ end
+ else
+ begin
+ value0 <= fifodata;
+ lines_in <= 2'd1;
+ rdreq <= 1;
+ payload_read <= payload_read + 7'd1;
+ lines_out <= 0;
+ case (fifodata[`OP_CODE])
+ `OP_PING_FIXED:
+ begin
+ state <= PING;
+ end
+ `OP_WRITE_REG:
+ begin
+ state <= WRITE_REG;
+ pending <= 1;
+ end
+ `OP_WRITE_REG_MASKED:
+ begin
+ state <= WRITE_REG_MASKED;
+ pending <= 1;
+ end
+ `OP_READ_REG:
+ begin
+ state <= READ_REG;
+ end
+ `OP_DELAY:
+ begin
+ state <= DELAY;
+ end
+ default:
+ begin
+ //error, skip this packet
+ skip <= 1;
state <= IDLE;
- skip <= 1;
- end
- end
+ end
+ endcase
+ end
+ end
- TEST : begin
- reg_io_enable <= 0;
- rx_WR <= 0;
- rx_WR_done <= 1;
- stop <= 0;
- if (payload_read == payload)
- begin
- skip <= 1;
- state <= IDLE;
- rdreq <= 0;
- end
- else
- begin
- value0 <= fifodata;
- lines_in <= 2'd1;
- rdreq <= 1;
- payload_read <= payload_read +
7'd1;
- lines_out <= 0;
- case (fifodata[`OP_CODE])
- `OP_PING_FIXED: begin
- state <= PING;
- end
- `OP_WRITE_REG: begin
- state <=
WRITE_REG;
- pending <= 1;
- end
- `OP_WRITE_REG_MASKED:
begin
- state <=
WRITE_REG_MASKED;
- pending <= 1;
- end
- `OP_READ_REG: begin
- state <=
READ_REG;
- end
- `OP_DELAY: begin
- state <= DELAY;
- end
- default: begin
- //error, skip this
packet
- skip <= 1;
- state <= IDLE;
- end
- endcase
- end
- end
+ SEND:
+ begin
+ rdreq <= 0;
+ rx_WR_done <= 0;
+ if (pending)
+ begin
+ rx_WR <= 1;
+ rx_databus <= high;
+ pending <= 0;
+ if (lines_out == lines_out_total)
+ state <= TEST;
+ else case (ops)
+ `OP_READ_REG:
+ begin
+ state <= READ_REG;
+ end
+ default:
+ begin
+ state <= TEST;
+ end
+ endcase
+ end
+ else
+ begin
+ if (rx_WR_enabled)
+ begin
+ rx_WR <= 1;
+ rx_databus <= low;
+ pending <= 1;
+ lines_out <= lines_out + 2'd1;
+ end
+ else
+ rx_WR <= 0;
+ end
+ end
- SEND: begin
- rdreq <= 0;
- rx_WR_done <= 0;
- if (pending)
- begin
- rx_WR <= 1;
- rx_databus <= high;
- pending <= 0;
- if (lines_out ==
lines_out_total)
- state <= TEST;
- else case (ops)
- `OP_READ_REG: begin
- state <=
READ_REG;
- end
- default: begin
- state <= TEST;
- end
- endcase
- end
- else
- begin
- if (rx_WR_enabled)
- begin
- rx_WR <= 1;
- rx_databus <= low;
- pending <= 1;
- lines_out <= lines_out
+ 2'd1;
- end
- else
- rx_WR <= 0;
- end
- end
+ PING:
+ begin
+ rx_WR <= 0;
+ rdreq <= 0;
+ rx_WR_done <= 0;
+ lines_out_total <= 2'd1;
+ pending <= 0;
+ state <= SEND;
+ high <= {`OP_PING_FIXED_REPLY, 8'd2};
+ low <= value0[15:0];
+ end
- PING: begin
- rx_WR <= 0;
- rdreq <= 0;
- rx_WR_done <= 0;
- lines_out_total <= 2'd1;
- pending <= 0;
- state <= SEND;
- high <= {`OP_PING_FIXED_REPLY, 8'd2};
- low <= value0[15:0];
- end
+ READ_REG:
+ begin
+ rx_WR <= 0;
+ rx_WR_done <= 0;
+ rdreq <= 0;
+ lines_out_total <= 2'd2;
+ pending <= 0;
+ state <= SEND;
+ if (lines_out == 0)
+ begin
+ high <= {`OP_READ_REG_REPLY, 8'd6};
+ low <= value0[15:0];
+ reg_io_enable <= 2'd3;
+ reg_addr <= value0[6:0];
+ end
+ else
+ begin
+ high <= reg_data_out[31:16];
+ low <= reg_data_out[15:0];
+ end
+ end
- READ_REG: begin
- rx_WR <= 0;
- rx_WR_done <= 0;
- rdreq <= 0;
- lines_out_total <= 2'd2;
- pending <= 0;
- state <= SEND;
- if (lines_out == 0)
- begin
- high <= {`OP_READ_REG_REPLY,
8'd6};
- low <= value0[15:0];
- reg_io_enable <= 2'd3;
- reg_addr <= value0[6:0];
- end
- else
- begin
- high <= reg_data_out[31:16];
- low <= reg_data_out[15:0];
- end
- end
+ WRITE_REG:
+ begin
+ rx_WR <= 0;
+ if (pending)
+ pending <= 0;
+ else
+ begin
+ if (lines_in == 2'd1)
+ begin
+ payload_read <= payload_read + 7'd1;
+ lines_in <= lines_in + 2'd1;
+ value1 <= fifodata;
+ rdreq <= 0;
+ end
+ else
+ begin
+ reg_io_enable <= 2'd2;
+ reg_data_in <= value1;
+ reg_addr <= value0[6:0];
+ state <= TEST;
+ end
+ end
+ end
- WRITE_REG: begin
- rx_WR <= 0;
- if (pending)
- pending <= 0;
- else
- begin
- if (lines_in == 2'd1)
- begin
- payload_read <=
payload_read + 7'd1;
- lines_in <= lines_in +
2'd1;
- value1 <= fifodata;
- rdreq <= 0;
- end
- else
- begin
- reg_io_enable <= 2'd2;
- reg_data_in <= value1;
- reg_addr <= value0[6:0];
- state <= TEST;
- end
- end
- end
+ WRITE_REG_MASKED:
+ begin
+ rx_WR <= 0;
+ if (pending)
+ pending <= 0;
+ else
+ begin
+ if (lines_in == 2'd1)
+ begin
+ rdreq <= 1;
+ payload_read <= payload_read + 7'd1;
+ lines_in <= lines_in + 2'd1;
+ value1 <= fifodata;
+ end
+ else if (lines_in == 2'd2)
+ begin
+ rdreq <= 0;
+ payload_read <= payload_read + 7'd1;
+ lines_in <= lines_in + 2'd1;
+ value2 <= fifodata;
+ end
+ else
+ begin
+ reg_io_enable <= 2'd2;
+ reg_data_in <= (value1 & value2);
+ reg_addr <= value0[6:0];
+ state <= TEST;
+ end
+ end
+ end
- WRITE_REG_MASKED: begin
- rx_WR <= 0;
- if (pending)
- pending <= 0;
- else
- begin
- if (lines_in == 2'd1)
- begin
- rdreq <= 1;
- payload_read <=
payload_read + 7'd1;
- lines_in <= lines_in +
2'd1;
- value1 <= fifodata;
- end
- else if (lines_in == 2'd2)
- begin
- rdreq <= 0;
- payload_read <=
payload_read + 7'd1;
- lines_in <= lines_in +
2'd1;
- value2 <= fifodata;
- end
- else
- begin
- reg_io_enable <= 2'd2;
- reg_data_in <= (value1
& value2);
- reg_addr <= value0[6:0];
- state <= TEST;
- end
- end
- end
+ DELAY :
+ begin
+ rdreq <= 0;
+ stop <= 1;
+ stop_time <= value0[15:0];
+ state <= TEST;
+ end
- DELAY : begin
- rdreq <= 0;
- stop <= 1;
- stop_time <= value0[15:0];
- state <= TEST;
- end
-
- default : begin
- //error state handling
- state <= IDLE;
- end
- endcase
-endmodule
\ No newline at end of file
+ default :
+ begin
+ //error state handling
+ state <= IDLE;
+ end
+ endcase
+endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,57 +1,25 @@
module register_io
- (clk, reset, enable, addr, datain, dataout, debugbus, addr_wr, data_wr,
strobe_wr,
- rssi_0, rssi_1, rssi_2, rssi_3, threshhold, rssi_wait, reg_0, reg_1,
reg_2, reg_3,
- atr_tx_delay, atr_rx_delay, master_controls, debug_en, interp_rate,
decim_rate,
- atr_mask_0, atr_txval_0, atr_rxval_0, atr_mask_1, atr_txval_1,
atr_rxval_1,
- atr_mask_2, atr_txval_2, atr_rxval_2, atr_mask_3, atr_txval_3,
atr_rxval_3,
- txa_refclk, txb_refclk, rxa_refclk, rxb_refclk, misc, txmux);
-
- input clk;
- input reset;
- input wire [1:0] enable;
- input wire [6:0] addr;
- input wire [31:0] datain;
- output reg [31:0] dataout;
- output wire [15:0] debugbus;
- output reg [6:0] addr_wr;
- output reg [31:0] data_wr;
- output wire strobe_wr;
- input wire [31:0] rssi_0;
- input wire [31:0] rssi_1;
- input wire [31:0] rssi_2;
- input wire [31:0] rssi_3;
- output wire [31:0] threshhold;
- output wire [31:0] rssi_wait;
- input wire [15:0] reg_0;
- input wire [15:0] reg_1;
- input wire [15:0] reg_2;
- input wire [15:0] reg_3;
- input wire [11:0] atr_tx_delay;
- input wire [11:0] atr_rx_delay;
- input wire [7:0] master_controls;
- input wire [3:0] debug_en;
- input wire [15:0] atr_mask_0;
- input wire [15:0] atr_txval_0;
- input wire [15:0] atr_rxval_0;
- input wire [15:0] atr_mask_1;
- input wire [15:0] atr_txval_1;
- input wire [15:0] atr_rxval_1;
- input wire [15:0] atr_mask_2;
- input wire [15:0] atr_txval_2;
- input wire [15:0] atr_rxval_2;
- input wire [15:0] atr_mask_3;
- input wire [15:0] atr_txval_3;
- input wire [15:0] atr_rxval_3;
- input wire [7:0] txa_refclk;
- input wire [7:0] txb_refclk;
- input wire [7:0] rxa_refclk;
- input wire [7:0] rxb_refclk;
- input wire [7:0] interp_rate;
- input wire [7:0] decim_rate;
- input wire [7:0] misc;
- input wire [31:0] txmux;
-
- wire [31:0] bundle[43:0];
+ ( // System
+ input clk, input reset, input wire [1:0] enable,
+ input wire [6:0] addr, input wire [31:0] datain,
+ output reg [31:0] dataout, output wire [15:0] debugbus,
+ output reg [6:0] addr_wr, output reg [31:0] data_wr, output wire
strobe_wr,
+ // output for rssi
+ output wire [31:0] threshhold, output wire [31:0] rssi_wait,
+ // Input data lines
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2, input wire [31:0] rssi_3,
+ input wire [15:0] reg_0, input wire [15:0] reg_1, input wire [15:0]
reg_2, input wire [15:0] reg_3,
+ input wire [11:0] atr_tx_delay, input wire [11:0] atr_rx_delay, input
wire [7:0] master_controls,
+ input wire [3:0] debug_en, input wire [7:0] interp_rate, input wire [7:0]
decim_rate,
+ input wire [15:0] atr_mask_0, input wire [15:0] atr_txval_0, input wire
[15:0] atr_rxval_0,
+ input wire [15:0] atr_mask_1, input wire [15:0] atr_txval_1, input wire
[15:0] atr_rxval_1,
+ input wire [15:0] atr_mask_2, input wire [15:0] atr_txval_2, input wire
[15:0] atr_rxval_2,
+ input wire [15:0] atr_mask_3, input wire [15:0] atr_txval_3, input wire
[15:0] atr_rxval_3,
+ input wire [7:0] txa_refclk, input wire [7:0] txb_refclk, input wire
[7:0] rxa_refclk, input wire [7:0] rxb_refclk,
+ input wire [7:0] misc, input wire [31:0] txmux);
+
+ // assigning wires according to their address
+ wire [31:0] bundle[43:0];
assign bundle[0] = 32'hFFFFFFFF;
assign bundle[1] = 32'hFFFFFFFF;
assign bundle[2] = {20'd0, atr_tx_delay};
@@ -97,57 +65,58 @@
assign bundle[42] = {24'd0, txb_refclk};
assign bundle[43] = {24'd0, rxb_refclk};
- reg strobe;
- wire [31:0] out[7:0];
- assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
- assign threshhold = out[1];
- assign rssi_wait = out[2];
- assign strobe_wr = strobe;
+ reg strobe;
+ wire [31:0] out[7:0];
+ assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+ assign threshhold = out[1];
+ assign rssi_wait = out[2];
+ assign strobe_wr = strobe;
- always @(*)
- if (reset | ~enable[1])
- begin
- strobe <= 0;
- dataout <= 0;
- end
- else
- begin
- if (enable[0])
- begin
- //read
- if (addr <= 7'd43)
- dataout <= bundle[addr];
- else if (addr <= 7'd57 && addr >= 7'd50)
- dataout <= out[addr-7'd50];
- else
- dataout <= 32'hFFFFFFFF;
- strobe <= 0;
- end
- else
- begin
- //write
- dataout <= dataout;
- strobe <= 1;
- data_wr <= datain;
- addr_wr <= addr;
- end
- end
+ always @(*)
+ if (reset | ~enable[1])
+ begin
+ strobe <= 0;
+ dataout <= 0;
+ end
+ else
+ begin
+ if (enable[0])
+ begin
+ //read
+ if (addr <= 7'd43)
+ dataout <= bundle[addr];
+ else if (addr <= 7'd57 && addr >= 7'd50)
+ dataout <= out[addr-7'd50];
+ else
+ dataout <= 32'hFFFFFFFF;
+ strobe <= 0;
+ end
+ else
+ begin
+ //write
+ dataout <= dataout;
+ strobe <= 1;
+ data_wr <= datain;
+ addr_wr <= addr;
+ end
+ end
- //register declarations
- setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
- setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
- setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
- setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
- setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
- setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
- setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
- setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
- .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
-endmodule
\ No newline at end of file
+ //user defined registers declarations
+ setting_reg #(50) setting_reg0(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
+ setting_reg #(51) setting_reg1(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
+ setting_reg #(52) setting_reg2(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
+ setting_reg #(53) setting_reg3(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
+ setting_reg #(54) setting_reg4(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
+ setting_reg #(55) setting_reg5(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
+ setting_reg #(56) setting_reg6(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
+ setting_reg #(57) setting_reg7(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
+
+endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,179 +1,144 @@
//`include "../../firmware/include/fpga_regs_common.v"
//`include "../../firmware/include/fpga_regs_standard.v"
module rx_buffer_inband
- ( input usbclk,
- input bus_reset,
- input reset, // DSP side reset (used here), do not reset registers
+ ( //System
+ input usbclk, input bus_reset, input reset, // DSP side reset (used
here), do not reset registers
input reset_regs, //Only reset registers
- output [15:0] usbdata,
- input RD,
- output wire have_pkt_rdy,
- output reg rx_overrun,
- input wire [3:0] channels,
- input wire [15:0] ch_0,
- input wire [15:0] ch_1,
- input wire [15:0] ch_2,
- input wire [15:0] ch_3,
- input wire [15:0] ch_4,
- input wire [15:0] ch_5,
- input wire [15:0] ch_6,
- input wire [15:0] ch_7,
- input rxclk,
- input rxstrobe,
- input clear_status,
- input [6:0] serial_addr,
- input [31:0] serial_data,
- input serial_strobe,
- output wire [15:0] debugbus,
-
- //Connection with tx_inband
- input rx_WR,
- input [15:0] rx_databus,
- input rx_WR_done,
- output reg rx_WR_enabled,
- //signal strength
- input wire [31:0] rssi_0, input wire [31:0] rssi_1,
- input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_underrun
- );
+ output [15:0] usbdata, input RD, output wire have_pkt_rdy,
+ output reg rx_overrun, input wire [3:0] channels,
+ input wire [15:0] ch_0, input wire [15:0] ch_1,
+ input wire [15:0] ch_2, input wire [15:0] ch_3,
+ input wire [15:0] ch_4, input wire [15:0] ch_5,
+ input wire [15:0] ch_6, input wire [15:0] ch_7,
+ input rxclk, input rxstrobe, input clear_status,
+ input [6:0] serial_addr, input [31:0] serial_data,
+ input serial_strobe, output wire [15:0] debugbus,
+ //Connection with tx_inband
+ input rx_WR, input [15:0] rx_databus,
+ input rx_WR_done, output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3,
+ input wire [1:0] tx_underrun);
- parameter NUM_CHAN = 1;
- genvar i ;
+ parameter NUM_CHAN = 1;
+ genvar i ;
- // FX2 Bug Fix
- reg [8:0] read_count;
- always @(negedge usbclk)
- if(bus_reset)
- read_count <= #1 9'd0;
- else if(RD & ~read_count[8])
- read_count <= #1 read_count + 9'd1;
- else
- read_count <= #1 RD ? read_count : 9'b0;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
- // Time counter
- reg [31:0] adctime;
- always @(posedge rxclk)
- if (reset)
- adctime <= 0;
- else if (rxstrobe)
- adctime <= adctime + 1;
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
- // USB side fifo
- wire [11:0] rdusedw;
- wire [11:0] wrusedw;
- wire [15:0] fifodata;
- wire WR;
- wire have_space;
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
- fifo_4kx16_dc rx_usb_fifo (
- .aclr ( reset ),
- .data ( fifodata ),
- .rdclk ( ~usbclk ),
- .rdreq ( RD & ~read_count[8] ),
- .wrclk ( rxclk ),
- .wrreq ( WR ),
- .q ( usbdata ),
- .rdempty ( ),
- .rdusedw ( rdusedw ),
- .wrfull ( ),
- .wrusedw ( wrusedw ) );
+ fifo_4kx16_dc rx_usb_fifo
+ (.aclr (reset), .data (fifodata),
+ .rdclk (~usbclk), .rdreq (RD & ~read_count[8]),
+ .wrclk (rxclk), .wrreq (WR), .q (usbdata),
+ .rdusedw (rdusedw), .wrusedw (wrusedw));
- assign have_pkt_rdy = (rdusedw >= 12'd256);
- assign have_space = (wrusedw < 12'd760);
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
- // Rx side fifos
- wire chan_rdreq;
- wire [15:0] chan_fifodata;
- wire [9:0] chan_usedw;
- wire [NUM_CHAN:0] chan_empty;
- wire [3:0] rd_select;
- wire [NUM_CHAN:0] rx_full;
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
- packet_builder #(NUM_CHAN) rx_pkt_builer (
- .rxclk ( rxclk ),
- .reset ( reset ),
- .adctime ( adctime ),
- .channels ( 4'd1 ),
- .chan_rdreq ( chan_rdreq ),
- .chan_fifodata ( chan_fifodata ),
- .chan_empty ( chan_empty ),
- .rd_select ( rd_select ),
- .chan_usedw ( chan_usedw ),
- .WR ( WR ),
- .fifodata ( fifodata ),
- .have_space ( have_space ),
- .rssi_0(rssi_0), .rssi_1(rssi_1),
- .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .underrun(tx_underrun));
+ packet_builder #(NUM_CHAN) rx_pkt_builer
+ (.rxclk (rxclk), .reset (reset),
+ .adctime (adctime), .channels (4'd1),
+ .chan_rdreq (chan_rdreq), .chan_fifodata (chan_fifodata),
+ .chan_empty (chan_empty), .rd_select (rd_select),
+ .chan_usedw (chan_usedw), .WR (WR), .fifodata (fifodata),
+ .have_space (have_space), .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2), .rssi_3(rssi_3), .debugbus(debug),
.underrun(tx_underrun));
- // Detect overrun
- always @(posedge rxclk)
- if(reset)
- rx_overrun <= 1'b0;
- else if(rx_full[0])
- rx_overrun <= 1'b1;
- else if(clear_status)
- rx_overrun <= 1'b0;
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
- reg [6:0] test;
- always @(posedge rxclk)
- if (reset)
- test <= 0;
- else
- test <= test + 7'd1;
+ reg [6:0] test;
+
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 7'd1;
- // TODO write this genericly
- wire [15:0]ch[NUM_CHAN:0];
- assign ch[0] = ch_0;
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+
+ wire cmd_empty;
- wire cmd_empty;
- always @(posedge rxclk)
- if(reset)
- rx_WR_enabled <= 1;
- else if(cmd_empty)
- rx_WR_enabled <= 1;
- else if(rx_WR_done)
- rx_WR_enabled <= 0;
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
- wire [15:0] dataout [0:NUM_CHAN];
- wire [9:0] usedw [0:NUM_CHAN];
- wire empty[0:NUM_CHAN];
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+ wire empty [0:NUM_CHAN];
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_fifos
- wire rdreq;
+
+ wire rdreq;
+ assign rdreq = (rd_select == i) & chan_rdreq;
- assign rdreq = (rd_select == i) & chan_rdreq;
- //assign chan_empty[i] = usedw[i] < 10'd126;
- fifo_1kx16 rx_chan_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( ch[i] ),
- .rdreq ( rdreq ),
- .wrreq ( ~rx_full[i] & rxstrobe),
- .empty (empty[i]),
- .full (rx_full[i]),
- .q ( dataout[i]),
- .usedw ( usedw[i]),
- .almost_empty(chan_empty[i])
- );
+ fifo_1kx16 rx_chan_fifo
+ (.aclr (reset), .clock (rxclk), .data (ch[i]),
+ .rdreq (rdreq), .wrreq (~rx_full[i] & rxstrobe),
+ .empty (empty[i]), .full (rx_full[i]), .q ( dataout[i]),
+ .usedw ( usedw[i]), .almost_empty(chan_empty[i]));
+
end
- endgenerate
- wire [7:0] debug;
- fifo_1kx16 rx_cmd_fifo (
- .aclr ( reset ),
- .clock ( rxclk ),
- .data ( rx_databus ),
- .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
- .wrreq ( rx_WR & rx_WR_enabled),
- .empty ( cmd_empty),
- .full ( rx_full[NUM_CHAN] ),
- .q ( dataout[NUM_CHAN]),
- .usedw ( usedw[NUM_CHAN] )
- );
- assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
- assign chan_fifodata = dataout[rd_select];
- assign chan_usedw = usedw[rd_select];
- assign debugbus = {rxstrobe, chan_rdreq, debug,
- rx_full[0], chan_empty[0], empty[0],
have_space, RD, rxclk};
+
+ endgenerate
+
+ wire [7:0] debug;
+
+ fifo_1kx16 rx_cmd_fifo
+ (.aclr (reset), .clock (rxclk), .data (rx_databus),
+ .rdreq ((rd_select == NUM_CHAN) & chan_rdreq),
+ .wrreq (rx_WR & rx_WR_enabled), .empty(cmd_empty),
+ .full (rx_full[NUM_CHAN]),
+ .q ( dataout[NUM_CHAN]), .usedw (usedw[NUM_CHAN]));
+
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {rxstrobe, chan_rdreq, debug,
+ rx_full[0], chan_empty[0], empty[0], have_space, RD,
rxclk};
+
endmodule
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -1,229 +1,146 @@
module tx_buffer_inband
- ( usbclk, bus_reset, reset, usbdata, WR, have_space,
- channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
- tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
- clear_status, tx_empty, debugbus,
- rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
- reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2,
- rssi_3, rssi_wait, threshhold, tx_underrun, stop, stop_time
- );
+ ( //System
+ input wire usbclk, input wire bus_reset, input wire reset,
+ input wire [15:0] usbdata, output wire have_space, input wire [3:0]
channels,
+ //output transmit signals
+ output wire [15:0] tx_i_0, output wire [15:0] tx_q_0,
+ output wire [15:0] tx_i_1, output wire [15:0] tx_q_1,
+ output wire [15:0] tx_i_2, output wire [15:0] tx_q_2,
+ output wire [15:0] tx_i_3, output wire [15:0] tx_q_3,
+ input wire txclk, input wire txstrobe, input wire WR,
+ input wire clear_status, output wire tx_empty, output wire [15:0]
debugbus,
+ //command reader io
+ output wire [15:0] rx_databus, output wire rx_WR, output wire rx_WR_done,
+ input wire rx_WR_enabled,
+ //register io
+ output wire reg_io_enable, output wire [31:0] reg_data_in, output wire
[6:0] reg_addr,
+ input wire [31:0] reg_data_out,
+ //input characteristic signals
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1, input wire [31:0]
rssi_2,
+ input wire [31:0] rssi_3, input wire [31:0] rssi_wait, input wire [31:0]
threshhold,
+ output wire [NUM_CHAN-1:0] tx_underrun,
+ //system stop
+ output wire stop, output wire [15:0] stop_time);
- parameter NUM_CHAN = 2 ;
- /* Debug paramters */
- parameter STROBE_RATE_0 = 8'd1 ;
- parameter STROBE_RATE_1 = 8'd2 ;
+ parameter NUM_CHAN = 2 ;
+ /* Debug paramters */
+ parameter STROBE_RATE_0 = 8'd1 ;
+ parameter STROBE_RATE_1 = 8'd2 ;
- input wire usbclk ;
- input wire bus_reset ; // Used here for the 257-Hack to
fix the FX2 bug
- input wire reset ; // standard DSP-side reset
- input wire [15:0] usbdata ;
- input wire WR ;
- input wire txclk ;
- input wire txstrobe ;
- input wire rx_WR_enabled;
- /* Not used yet */
- input wire [3:0] channels ;
- input wire clear_status ;
- /*register io*/
- input wire [31:0]reg_data_out;
- // rssi
- input wire [31:0]rssi_0;
- input wire [31:0]rssi_1;
- input wire [31:0]rssi_2;
- input wire [31:0]rssi_3;
- input wire [31:0]threshhold;
- input wire [31:0]rssi_wait;
- output wire have_space ;
- output wire tx_empty ;
- output wire [15:0] tx_i_0 ;
- output wire [15:0] tx_q_0 ;
- output wire [15:0] tx_i_1 ;
- output wire [15:0] tx_q_1 ;
- output wire [15:0] debugbus ;
- /* Not used yet */
- output wire [15:0] tx_i_2 ;
- output wire [15:0] tx_q_2 ;
- output wire [15:0] tx_i_3 ;
- output wire [15:0] tx_q_3 ;
-
- output wire [15:0] rx_databus ;
- output wire rx_WR;
- output wire rx_WR_done;
- /* reg_io */
- output wire [31:0] reg_data_in;
- output wire [6:0] reg_addr;
- output wire [1:0] reg_io_enable;
- output wire [NUM_CHAN-1:0] tx_underrun;
- /*stoppage*/
- output wire stop;
- output wire [15:0] stop_time;
-
- /* To generate channel readers */
- genvar i ;
+ /* To generate channel readers */
+ genvar i ;
- /* These will eventually be external register */
- reg [31:0] adc_time ;
- wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
- wire [31:0] rssi [3:0];
- assign rssi[0] = rssi_0;
- assign rssi[1] = rssi_1;
- assign rssi[2] = rssi_2;
- assign rssi[3] = rssi_3;
+ /* These will eventually be external register */
+ reg [31:0] adc_time ;
+ wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+ wire [31:0] rssi [3:0];
+ assign rssi[0] = rssi_0;
+ assign rssi[1] = rssi_1;
+ assign rssi[2] = rssi_2;
+ assign rssi[3] = rssi_3;
- always @(posedge txclk)
- if (reset)
- adc_time <= 0;
- else if (txstrobe)
- adc_time <= adc_time + 1;
+ always @(posedge txclk)
+ if (reset)
+ adc_time <= 0;
+ else if (txstrobe)
+ adc_time <= adc_time + 1;
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
- wire [31:0] tx_data_bus ;
- wire [NUM_CHAN:0] chan_WR ;
- wire [NUM_CHAN:0] chan_done ;
+ wire [31:0] tx_data_bus ;
+ wire [NUM_CHAN:0] chan_WR ;
+ wire [NUM_CHAN:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] chan_underrun ;
- wire [NUM_CHAN:0] chan_txempty ;
+ wire [NUM_CHAN:0] chan_underrun ;
+ wire [NUM_CHAN:0] chan_txempty ;
- /* Conections between tx_data_packet_fifo and
+ /* Conections between tx_data_packet_fifo and
its reader + strobe generator */
- wire [31:0] chan_fifodata [NUM_CHAN:0] ;
- wire chan_pkt_waiting [NUM_CHAN:0] ;
- wire chan_rdreq [NUM_CHAN:0] ;
- wire chan_skip [NUM_CHAN:0] ;
- wire [NUM_CHAN:0] chan_have_space ;
- wire chan_txstrobe [NUM_CHAN-1:0] ;
+ wire [31:0] chan_fifodata [NUM_CHAN:0] ;
+ wire chan_pkt_waiting [NUM_CHAN:0] ;
+ wire chan_rdreq [NUM_CHAN:0] ;
+ wire chan_skip [NUM_CHAN:0] ;
+ wire [NUM_CHAN:0] chan_have_space ;
+ wire chan_txstrobe [NUM_CHAN-1:0] ;
- wire [14:0] debug;
+ wire [14:0] debug;
- /* Outputs to transmit chains */
- wire [15:0] tx_i [NUM_CHAN-1:0] ;
- wire [15:0] tx_q [NUM_CHAN-1:0] ;
+ /* Outputs to transmit chains */
+ wire [15:0] tx_i [NUM_CHAN-1:0] ;
+ wire [15:0] tx_q [NUM_CHAN-1:0] ;
- /* TODO: Figure out how to write this genericly */
- assign have_space = chan_have_space[0] & chan_have_space[1];
- assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
- assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
- assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
- assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
- assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
+ /* TODO: Figure out how to write this genericly */
+ assign have_space = chan_have_space[0] & chan_have_space[1];
+ assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
+ assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
+ assign tx_q_0 = chan_txempty[0] ? 16'b0 : tx_q[0] ;
+ assign tx_i_1 = chan_txempty[1] ? 16'b0 : tx_i[1] ;
+ assign tx_q_1 = chan_txempty[1] ? 16'b0 : tx_q[1] ;
- /* Debug statement */
- assign txstrobe_rate[0] = STROBE_RATE_0 ;
- assign txstrobe_rate[1] = STROBE_RATE_1 ;
- assign tx_q_2 = 16'b0 ;
- assign tx_i_2 = 16'b0 ;
- assign tx_q_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
- assign tx_i_3 = 16'b0 ;
+ /* Debug statement */
+ assign txstrobe_rate[0] = STROBE_RATE_0 ;
+ assign txstrobe_rate[1] = STROBE_RATE_1 ;
+ assign tx_q_2 = 16'b0 ;
+ assign tx_i_2 = 16'b0 ;
+ assign tx_q_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
+ assign tx_i_3 = 16'b0 ;
- assign debugbus = {debug, txclk};
+ assign debugbus = {debug, txclk};
- wire [31:0] usbdata_final;
- wire WR_final;
+ wire [31:0] usbdata_final;
+ wire WR_final;
- tx_packer tx_usb_packer
- (
- .bus_reset (bus_reset),
- .usbclk (usbclk),
- .WR_fx2 (WR),
- .usbdata (usbdata),
- .reset (reset),
- .txclk (txclk),
- .usbdata_final (usbdata_final),
- .WR_final (WR_final)
- );
+ tx_packer tx_usb_packer
+ (.bus_reset(bus_reset), .usbclk(usbclk), .WR_fx2(WR),
+ .usbdata(usbdata), .reset(reset), .txclk(txclk),
+ .usbdata_final(usbdata_final), .WR_final(WR_final));
- channel_demux channel_demuxer
- (
- .usbdata_final (usbdata_final),
- .WR_final (WR_final),
- .reset (reset),
- .txclk (txclk),
- .WR_channel (chan_WR),
- .WR_done_channel (chan_done),
- .ram_data (tx_data_bus)
- );
+ channel_demux channel_demuxer
+ (.usbdata_final(usbdata_final), .WR_final(WR_final),
+ .reset(reset), .txclk(txclk), .WR_channel(chan_WR),
+ .WR_done_channel(chan_done), .ram_data(tx_data_bus));
- generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
- begin : generate_channel_readers
- assign tx_underrun[i] = chan_underrun[i];
- channel_ram tx_data_packet_fifo
- ( .reset (reset),
- .txclk (txclk),
- .datain (tx_data_bus),
- .WR (chan_WR[i]),
- .WR_done (chan_done[i]),
- .have_space (chan_have_space[i]),
- .dataout (chan_fifodata[i]),
- .packet_waiting (chan_pkt_waiting[i]),
- .RD (chan_rdreq[i]),
- .RD_done (chan_skip[i])
- );
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_readers
+ assign tx_underrun[i] = chan_underrun[i];
- chan_fifo_reader tx_chan_reader
- ( .reset (reset),
- .tx_clock (txclk),
- .tx_strobe (txstrobe),
- .adc_time (adc_time),
- .samples_format (4'b0),
- .tx_q (tx_q[i]),
- .tx_i (tx_i[i]),
- .underrun (chan_underrun[i]),
- .skip (chan_skip[i]),
- .rdreq (chan_rdreq[i]),
- .fifodata (chan_fifodata[i]),
- .pkt_waiting (chan_pkt_waiting[i]),
- .tx_empty (chan_txempty[i]),
- .rssi (rssi[i]),
- .threshhold (threshhold),
- .rssi_wait (rssi_wait)
- );
-
+ channel_ram tx_data_packet_fifo
+ (.reset(reset), .txclk(txclk), .datain(tx_data_bus),
+ .WR(chan_WR[i]), .WR_done(chan_done[i]),
+ .have_space(chan_have_space[i]), .dataout(chan_fifodata[i]),
+ .packet_waiting(chan_pkt_waiting[i]), .RD(chan_rdreq[i]),
+ .RD_done(chan_skip[i]));
+
+ chan_fifo_reader tx_chan_reader
+ (.reset(reset), .tx_clock(txclk), .tx_strobe(txstrobe),
+ .adc_time(adc_time), .samples_format(4'b0),
+ .tx_q(tx_q[i]), .tx_i(tx_i[i]), .underrun(chan_underrun[i]),
+ .skip(chan_skip[i]), .rdreq(chan_rdreq[i]),
+ .fifodata(chan_fifodata[i]), .pkt_waiting(chan_pkt_waiting[i]),
+ .tx_empty(chan_txempty[i]), .rssi(rssi[i]),
+ .threshhold(threshhold), .rssi_wait(rssi_wait));
end
endgenerate
- channel_ram tx_cmd_packet_fifo
- ( .reset (reset),
- .txclk (txclk),
- .datain (tx_data_bus),
- .WR (chan_WR[NUM_CHAN]),
- .WR_done (chan_done[NUM_CHAN]),
- .have_space (chan_have_space[NUM_CHAN]),
- .dataout (chan_fifodata[NUM_CHAN]),
- .packet_waiting (chan_pkt_waiting[NUM_CHAN]),
- .RD (chan_rdreq[NUM_CHAN]),
- .RD_done (chan_skip[NUM_CHAN])
- );
+ channel_ram tx_cmd_packet_fifo
+ (.reset(reset), .txclk(txclk), .datain(tx_data_bus), .WR(chan_WR[NUM_CHAN]),
+ .WR_done(chan_done[NUM_CHAN]), .have_space(chan_have_space[NUM_CHAN]),
+ .dataout(chan_fifodata[NUM_CHAN]),
.packet_waiting(chan_pkt_waiting[NUM_CHAN]),
+ .RD(chan_rdreq[NUM_CHAN]), .RD_done(chan_skip[NUM_CHAN]));
-
- cmd_reader tx_cmd_reader
- ( .reset (reset),
- .txclk (txclk),
- .adc_time
(adc_time),
- .skip
(chan_skip[NUM_CHAN]),
- .rdreq
(chan_rdreq[NUM_CHAN]),
- .fifodata
(chan_fifodata[NUM_CHAN]),
- .pkt_waiting
(chan_pkt_waiting[NUM_CHAN]),
- .rx_databus
(rx_databus),
- .rx_WR (rx_WR),
- .rx_WR_done
(rx_WR_done),
- .rx_WR_enabled (rx_WR_enabled),
- .reg_data_in (reg_data_in),
- .reg_data_out (reg_data_out),
- .reg_addr
(reg_addr),
- .reg_io_enable (reg_io_enable),
- .debug (debug),
- .stop (stop),
- .stop_time
(stop_time)
- );
-
-
-
+ cmd_reader tx_cmd_reader
+ (.reset(reset), .txclk(txclk), .adc_time(adc_time),
.skip(chan_skip[NUM_CHAN]),
+ .rdreq(chan_rdreq[NUM_CHAN]), .fifodata(chan_fifodata[NUM_CHAN]),
+ .pkt_waiting(chan_pkt_waiting[NUM_CHAN]), .rx_databus(rx_databus),
+ .rx_WR(rx_WR), .rx_WR_done(rx_WR_done), .rx_WR_enabled(rx_WR_enabled),
+ .reg_data_in(reg_data_in), .reg_data_out(reg_data_out),
.reg_addr(reg_addr),
+ .reg_io_enable(reg_io_enable), .debug(debug), .stop(stop),
.stop_time(stop_time));
+
endmodule // tx_buffer
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev2/std_inband.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/rbf/rev4/std_inband.rbf
===================================================================
(Binary files differ)
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-22 02:58:29 UTC (rev 6661)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-10-22 03:25:36 UTC (rev 6662)
@@ -361,12 +361,12 @@
wire [6:0] addr_db;
wire [31:0] data_db;
wire strobe_db;
- assign serial_strobe = strobe_db | strobe_wr;
- assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
- assign serial_data = (strobe_db)? (data_db) : (data_wr);
- //assign serial_strobe = strobe_wr;
- //assign serial_data = data_wr;
- //assign serial_addr = addr_wr;
+ //assign serial_strobe = strobe_db | strobe_wr;
+ //assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
+ //assign serial_data = (strobe_db)? (data_db) : (data_wr);
+ assign serial_strobe = strobe_wr;
+ assign serial_data = data_wr;
+ assign serial_addr = addr_wr;
//wires for register connection
wire [11:0] atr_tx_delay;
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- [Commit-gnuradio] r6662 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib rbf/rev2 rbf/rev4 toplevel/usrp_inband_usb,
zhuochen <=