[Commit-gnuradio] r6605 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-10-09 18:39:11 -0600 (Tue, 09 Oct 2007)
New Revision: 6605

Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
Log:
partially working inband signalling


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v  2007-10-09 
20:10:04 UTC (rev 6604)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v  2007-10-10 
00:39:11 UTC (rev 6605)
@@ -1,4 +1,5 @@
 
+`define DSP_CORE_TX_BASE 128
 
 module tx_control
   #(parameter FIFOSIZE = 10)
@@ -17,10 +18,9 @@
      output rd_error_o,
      
      // To DSP Core
-     output [15:0] bb_i,
-     output [15:0] bb_q,
-     output run_tx,
-     input rd_ack
+     output [31:0] sample,
+     output run,
+     output strobe
      );
 
    // Buffer interface to internal FIFO
@@ -42,18 +42,139 @@
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K
    wire    sop_o, eop_o;
+   wire [31:0] data_o;
+   
    longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) txfifo
      (.clk(clk),.rst(rst),
       .datain({rd_sop_i,rd_eop_i,rd_dat_i}), .write(write), .full(full),
-      .dataout({sop_o,eop_o,bb_i,bb_q}), .read(read), .empty(empty)
+      .dataout({sop_o,eop_o,data_o}), .read(read), .empty(empty)
       );
 
    // Internal FIFO to DSP interface
+   reg [31:0]  next_time;
+   reg                next_time_valid;
+   reg [31:0]  next_sample;
+   reg                next_sample_valid;
+   reg [31:0]  next_flags;
+   reg                next_flags_valid;
+   reg [2:0]   ibs_state;
+   reg                next_eop;
    
-   //     Inband signalling support needs to go in here...
-   assign  run_tx = ~empty;
-   assign  read = rd_ack & ~empty;
+   localparam  IBS_IDLE = 0;
+   localparam  IBS_HAVE_FLAGS = 1;
+   localparam  IBS_HAVE_TIME = 2;
+   localparam  IBS_WAIT = 3;
+   localparam  IBS_RUNNING = 4;
+   localparam  IBS_CONT_BURST = 5;
+   localparam  IBS_CONT_BURST2 = 6;
+   localparam  IBS_UNDERRUN = 7;
 
-   assign  underrun = rd_ack & empty;
+   wire        too_late = 0;
+   wire        go_now = ( master_time == next_time );
+   wire        eob = next_flags[0];
+   wire        sob = next_flags[1];
    
+   always @(posedge clk)
+     if(rst)
+       begin
+         ibs_state <= IBS_IDLE;
+         next_time_valid <= 0;
+         next_sample_valid <= 0;
+         next_flags_valid <=0;
+       end
+     else
+       case(ibs_state)
+        IBS_IDLE :
+          if(~empty & sop_o)
+            begin
+               ibs_state <= IBS_HAVE_FLAGS;
+               next_flags <= data_o;
+               next_flags_valid <= 1;
+            end
+          else
+            next_flags_valid <= 0;
+        IBS_HAVE_FLAGS :
+          if(~sob)
+            ibs_state <= IBS_UNDERRUN;
+          else if(~empty)
+            begin
+               ibs_state <= IBS_HAVE_TIME;
+               next_time <= data_o;
+               next_time_valid <= 1;
+            end
+        IBS_HAVE_TIME :
+          if(~empty)
+            begin
+               ibs_state <= IBS_WAIT;
+               next_sample <= data_o;
+               next_eop <= eop_o;
+               next_sample_valid <= 1;
+            end
+        IBS_WAIT :
+          if(too_late)
+            ibs_state <= IBS_UNDERRUN;
+          else if(go_now)
+            ibs_state <= IBS_RUNNING;
+        IBS_RUNNING :
+          if(strobe)
+            if(~next_sample_valid)
+              ibs_state <= IBS_UNDERRUN;
+            else
+              if(next_eop & eob)
+                ibs_state <= IBS_IDLE;
+              else if(next_eop)
+                ibs_state <= IBS_CONT_BURST;
+              else if(~empty)
+                begin
+                   next_sample <= data_o;
+                   next_eop <= eop_o;
+                end
+              else
+                next_sample <= 0;
+          else
+            if(~empty & ~next_sample_valid)
+              begin
+                 next_sample <= data_o;
+                 next_eop <= eop_o;
+                 next_sample_valid <= 1;
+              end
+        IBS_CONT_BURST :
+          if(strobe)
+            ibs_state <= IBS_UNDERRUN;
+          else if(~empty & sop_o)
+            begin
+               ibs_state <= IBS_CONT_BURST2;
+               next_flags <= data_o;
+            end
+        IBS_CONT_BURST2 :
+          if(strobe)
+            ibs_state <= IBS_UNDERRUN;
+          else if(sob)
+            ibs_state <= IBS_UNDERRUN;
+          else if(~empty)
+            begin
+               ibs_state <= IBS_RUNNING;
+               next_sample_valid <= 0;
+            end
+        IBS_UNDERRUN :
+          // clear out junk
+          ;
+       endcase // case(ibs_state)
+   
+   assign      run = ((ibs_state == IBS_RUNNING) | 
+                     (ibs_state == IBS_CONT_BURST) | 
+                     (ibs_state==IBS_CONT_BURST2));
+   assign      waiting = (ibs_state == IBS_WAIT);
+   assign      read = ~empty & ~waiting & ~(run & ~strobe);
+   assign      underrun = (ibs_state == IBS_UNDERRUN);
+
+   wire [7:0]  interp_rate;
+   setting_reg #(.my_addr(`DSP_CORE_TX_BASE+2)) sr_2
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(interp_rate),.changed());
+
+   strobe_gen 
strobe_gen(.clock(clk),.reset(rst),.enable(run),.rate(interp_rate),
+                        .strobe_in(run),.strobe(strobe) );
+
+   assign      sample = next_sample;      
 endmodule // tx_control