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[Commit-gnuradio] r6596 - usrp-hw/trunk/sym/generated
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r6596 - usrp-hw/trunk/sym/generated |
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Date: |
Mon, 8 Oct 2007 15:30:13 -0600 (MDT) |
Author: matt
Date: 2007-10-08 15:30:13 -0600 (Mon, 08 Oct 2007)
New Revision: 6596
Added:
usrp-hw/trunk/sym/generated/XC3SD1800ACS484.csv
usrp-hw/trunk/sym/generated/spi-flash-so16.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-BOTCLK.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-CFG.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO0.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO1.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO2.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO3.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-JTAG.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-LHCLK.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-PWR.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-RHCLK.src
usrp-hw/trunk/sym/generated/xc3sd1800acs484-TOPCLK.src
usrp-hw/trunk/sym/generated/xilinxgen484
Modified:
usrp-hw/trunk/sym/generated/Makefile
Log:
new fpga, spi flash
Modified: usrp-hw/trunk/sym/generated/Makefile
===================================================================
--- usrp-hw/trunk/sym/generated/Makefile 2007-10-08 19:28:07 UTC (rev
6595)
+++ usrp-hw/trunk/sym/generated/Makefile 2007-10-08 21:30:13 UTC (rev
6596)
@@ -175,9 +175,22 @@
adl5330-AMP.sym \
ad8362-PWR.sym \
ad8362-SIG.sym \
- lp38692mp.sym
+ lp38692mp.sym \
+ xc3sd1800acs484-CFG.sym \
+ xc3sd1800acs484-TOPCLK.sym \
+ xc3sd1800acs484-BOTCLK.sym \
+ xc3sd1800acs484-IO0.sym \
+ xc3sd1800acs484-IO1.sym \
+ xc3sd1800acs484-IO2.sym \
+ xc3sd1800acs484-IO3.sym \
+ xc3sd1800acs484-LHCLK.sym \
+ xc3sd1800acs484-RHCLK.sym \
+ xc3sd1800acs484-JTAG.sym \
+ xc3sd1800acs484-PWR.sym \
+ spi-flash-so16.sym
+
all : $(SOURCES)
clean :
Added: usrp-hw/trunk/sym/generated/XC3SD1800ACS484.csv
===================================================================
--- usrp-hw/trunk/sym/generated/XC3SD1800ACS484.csv
(rev 0)
+++ usrp-hw/trunk/sym/generated/XC3SD1800ACS484.csv 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,485 @@
+PIN,XC3SD1800ACS484_PIN,XC3SD1800ACS484_BANK,TYPE,DIFF_PAIR,ROW,ROW_#,COLUMN
+A1,GND,GND,GND,,A,1,1
+A2,PROG_B,VCCAUX,CONFIG,,A,1,2
+A3,IO_L30N_0,0,I/O,TRUE,A,1,3
+A4,IO_L28N_0,0,I/O,TRUE,A,1,4
+A5,IO_L25N_0,0,I/O,TRUE,A,1,5
+A6,IO_L25P_0,0,I/O,TRUE,A,1,6
+A7,IO_L24N_0/VREF_0,0,VREF,TRUE,A,1,7
+A8,IO_L20P_0/GCLK10,0,GCLK,TRUE,A,1,8
+A9,IO_L18P_0/GCLK6,0,GCLK,TRUE,A,1,9
+A10,IP_0,0,INPUT,,A,1,10
+A11,IO_L15N_0,0,I/O,TRUE,A,1,11
+A12,IP_0,0,INPUT,,A,1,12
+A13,IO_L11P_0,0,I/O,TRUE,A,1,13
+A14,IO_L10P_0,0,I/O,TRUE,A,1,14
+A15,IP_0,0,INPUT,,A,1,15
+A16,IO_L06P_0/VREF_0,0,VREF,TRUE,A,1,16
+A17,IO_L06N_0,0,I/O,TRUE,A,1,17
+A18,IP_0,0,INPUT,,A,1,18
+A19,IO_L07N_0,0,I/O,TRUE,A,1,19
+A20,IO_0,0,I/O,,A,1,20
+A21,TCK,VCCAUX,JTAG,,A,1,21
+A22,GND,GND,GND,,A,1,22
+AA1,IP_L39N_3/VREF_3,3,VREF,TRUE,AA,21,1
+AA2,VCCAUX,VCCAUX,VCCAUX,,AA,21,2
+AA3,IO_L01P_2/M1,2,DUAL,TRUE,AA,21,3
+AA4,IO_L04N_2,2,I/O,TRUE,AA,21,4
+AA5,VCCO_2,2,VCCO,,AA,21,5
+AA6,IP_2,2,INPUT,,AA,21,6
+AA7,GND,GND,GND,,AA,21,7
+AA8,IO_L08N_2,2,I/O,TRUE,AA,21,8
+AA9,VCCO_2,2,VCCO,,AA,21,9
+AA10,IO_L12N_2/D6,2,DUAL,TRUE,AA,21,10
+AA11,GND,GND,GND,,AA,21,11
+AA12,IO_L16P_2/GCLK14,2,GCLK,TRUE,AA,21,12
+AA13,VCCO_2,2,VCCO,,AA,21,13
+AA14,IO_L18N_2/GCLK2,2,GCLK,TRUE,AA,21,14
+AA15,IO_L19P_2,2,I/O,TRUE,AA,21,15
+AA16,GND,GND,GND,,AA,21,16
+AA17,IO_L22P_2/AWAKE,2,PWRMGMT,TRUE,AA,21,17
+AA18,VCCO_2,2,VCCO,,AA,21,18
+AA19,IO_L27N_2,2,I/O,TRUE,AA,21,19
+AA20,IO_L30P_2,2,I/O,TRUE,AA,21,20
+AA21,VCCAUX,VCCAUX,VCCAUX,,AA,21,21
+AA22,IO_L02N_1/LDC0,1,DUAL,TRUE,AA,21,22
+AB1,GND,GND,GND,,AB,22,1
+AB2,IP_2/VREF_2,2,VREF,,AB,22,2
+AB3,IO_L01N_2/M0,2,DUAL,TRUE,AB,22,3
+AB4,IO_L04P_2,2,I/O,TRUE,AB,22,4
+AB5,IO_L05P_2,2,I/O,TRUE,AB,22,5
+AB6,IO_L05N_2,2,I/O,TRUE,AB,22,6
+AB7,IO_L08P_2,2,I/O,TRUE,AB,22,7
+AB8,IO_L09P_2/VS1,2,DUAL,TRUE,AB,22,8
+AB9,IO_L09N_2/VS0,2,DUAL,TRUE,AB,22,9
+AB10,IO_L12P_2/D7,2,DUAL,TRUE,AB,22,10
+AB11,IP_2/VREF_2,2,VREF,,AB,22,11
+AB12,IO_L16N_2/GCLK15,2,GCLK,TRUE,AB,22,12
+AB13,IO_L18P_2,2,GCLK,TRUE,AB,22,13
+AB14,IO_L19N_2,2,I/O,TRUE,AB,22,14
+AB15,IP_2,2,INPUT,,AB,22,15
+AB16,IO_L22N_2/DOUT,2,DUAL,TRUE,AB,22,16
+AB17,IO_L23P_2,2,I/O,TRUE,AB,22,17
+AB18,IO_L23N_2,2,I/O,TRUE,AB,22,18
+AB19,IO_L27P_2,2,I/O,TRUE,AB,22,19
+AB20,IO_L30N_2,2,I/O,TRUE,AB,22,20
+AB21,DONE,VCCAUX,CONFIG,,AB,22,21
+AB22,GND,GND,GND,,AB,22,22
+B1,TMS,VCCAUX,JTAG,,B,2,1
+B2,VCCAUX,VCCAUX,VCCAUX,,B,2,2
+B3,IO_L30P_0,0,I/O,TRUE,B,2,3
+B4,IO_L28P_0,0,I/O,TRUE,B,2,4
+B5,VCCO_0,0,VCCO,,B,2,5
+B6,IO_L24P_0,0,I/O,TRUE,B,2,6
+B7,GND,GND,GND,,B,2,7
+B8,IO_L20N_0/GCLK11,0,GCLK,TRUE,B,2,8
+B9,IO_L18N_0/GCLK7,0,GCLK,TRUE,B,2,9
+B10,VCCO_0,0,VCCO,,B,2,10
+B11,IO_L15P_0,0,I/O,TRUE,B,2,11
+B12,GND,GND,GND,,B,2,12
+B13,IO_L11N_0,0,I/O,TRUE,B,2,13
+B14,VCCO_0,0,VCCO,,B,2,14
+B15,IO_L10N_0,0,I/O,TRUE,B,2,15
+B16,GND,GND,GND,,B,2,16
+B17,IO_L03P_0,0,I/O,TRUE,B,2,17
+B18,VCCO_0,0,VCCO,,B,2,18
+B19,IO_L02N_0,0,I/O,TRUE,B,2,19
+B20,IO_L07P_0,0,I/O,TRUE,B,2,20
+B21,VCCAUX,VCCAUX,VCCAUX,,B,2,21
+B22,TDO,VCCAUX,JTAG,,B,2,22
+C1,IO_L02N_3,3,I/O,TRUE,C,3,1
+C2,IO_L02P_3,3,I/O,TRUE,C,3,2
+C3,GND,GND,GND,,C,3,3
+C4,IO_L29N_0,0,I/O,TRUE,C,3,4
+C5,IP_0,0,INPUT,,C,3,5
+C6,IO_L21P_0,0,I/O,TRUE,C,3,6
+C7,IO_L26P_0,0,I/O,TRUE,C,3,7
+C8,IO_L22P_0,0,I/O,TRUE,C,3,8
+C9,IO_L16P_0,0,I/O,TRUE,C,3,9
+C10,IP_0,0,INPUT,,C,3,10
+C11,IP_0/VREF_0,0,VREF,,C,3,11
+C12,IO_L14N_0,0,I/O,TRUE,C,3,12
+C13,IO_L14P_0,0,I/O,TRUE,C,3,13
+C14,IP_0,0,INPUT,,C,3,14
+C15,IO_L12N_0/VREF_0,0,VREF,TRUE,C,3,15
+C16,IO_L08N_0,0,I/O,TRUE,C,3,16
+C17,IO_L03N_0,0,I/O,TRUE,C,3,17
+C18,IO_L02P_0/VREF_0,0,VREF,TRUE,C,3,18
+C19,IO_L01N_0,0,I/O,TRUE,C,3,19
+C20,GND,GND,GND,,C,3,20
+C21,IP_L39N_1,1,INPUT,TRUE,C,3,21
+C22,IP_L39P_1/VREF_1,1,VREF,TRUE,C,3,22
+D1,IP_L04P_3,3,INPUT,TRUE,D,4,1
+D2,TDI,VCCAUX,JTAG,,D,4,2
+D3,IP_L08P_3,3,INPUT,TRUE,D,4,3
+D4,IP_L08N_3,3,INPUT,TRUE,D,4,4
+D5,IO_L29P_0,0,I/O,TRUE,D,4,5
+D6,IO_L21N_0,0,I/O,TRUE,D,4,6
+D7,IO_L26N_0,0,I/O,TRUE,D,4,7
+D8,GND,GND,GND,,D,4,8
+D9,IO_L22N_0,0,I/O,TRUE,D,4,9
+D10,IO_L16N_0,0,I/O,TRUE,D,4,10
+D11,GND,GND,GND,,D,4,11
+D12,VCCAUX,VCCAUX,VCCAUX,,D,4,12
+D13,IO_L09N_0,0,I/O,TRUE,D,4,13
+D14,IO_L12P_0,0,I/O,TRUE,D,4,14
+D15,IO_L08P_0,0,I/O,TRUE,D,4,15
+D16,GND,GND,GND,,D,4,16
+D17,IP_0,0,INPUT,,D,4,17
+D18,IP_0,0,INPUT,,D,4,18
+D19,IO_L01P_0,0,I/O,TRUE,D,4,19
+D20,IO_L36P_1/A20,1,DUAL,TRUE,D,4,20
+D21,IO_L37P_1/A22,1,DUAL,TRUE,D,4,21
+D22,IO_L37N_1/A23,1,DUAL,TRUE,D,4,22
+E1,IP_L04N_3/VREF_3,3,VREF,TRUE,E,5,1
+E2,VCCO_3,3,VCCO,,E,5,2
+E3,IO_L09P_3,3,I/O,TRUE,E,5,3
+E4,IO_L09N_3,3,I/O,TRUE,E,5,4
+E5,VCCAUX,VCCAUX,VCCAUX,,E,5,5
+E6,IP_0,0,INPUT,,E,5,6
+E7,IO_L31P_0/VREF_0,0,VREF,TRUE,E,5,7
+E8,IO_L27N_0,0,I/O,TRUE,E,5,8
+E9,VCCO_0,0,VCCO,,E,5,9
+E10,IP_0,0,INPUT,,E,5,10
+E11,IO_L19N_0/GCLK9,0,GCLK,TRUE,E,5,11
+E12,IO_L17P_0/GCLK4,0,GCLK,TRUE,E,5,12
+E13,IO_L09P_0,0,I/O,TRUE,E,5,13
+E14,VCCO_0,0,VCCO,,E,5,14
+E15,IO_L05P_0,0,I/O,TRUE,E,5,15
+E16,IO_L04P_0,0,I/O,TRUE,E,5,16
+E17,IP_0,0,INPUT,,E,5,17
+E18,VCCAUX,VCCAUX,VCCAUX,,E,5,18
+E19,IO_L36N_1/A21,1,DUAL,TRUE,E,5,19
+E20,IO_L35N_1,1,I/O,TRUE,E,5,20
+E21,VCCO_1,1,VCCO,,E,5,21
+E22,IO_L33N_1,1,I/O,TRUE,E,5,22
+F1,IO_L06N_3,3,I/O,TRUE,F,6,1
+F2,IO_L06P_3,3,I/O,TRUE,F,6,2
+F3,IO_L01P_3,3,I/O,TRUE,F,6,3
+F4,IO_L03P_3,3,I/O,TRUE,F,6,4
+F5,IO_L03N_3,3,I/O,TRUE,F,6,5
+F6,GND,GND,GND,,F,6,6
+F7,IO_L31N_0/PUDC_B,0,DUAL,TRUE,F,6,7
+F8,IO_L27P_0,0,I/O,TRUE,F,6,8
+F9,IO_L23N_0,0,I/O,TRUE,F,6,9
+F10,IO_L19P_0/GCLK8,0,GCLK,TRUE,F,6,10
+F11,IO_L17N_0/GCLK5,0,GCLK,TRUE,F,6,11
+F12,IP_0,0,INPUT,,F,6,12
+F13,IO_L13N_0,0,I/O,TRUE,F,6,13
+F14,IO_L13P_0,0,I/O,TRUE,F,6,14
+F15,IO_L05N_0,0,I/O,TRUE,F,6,15
+F16,IO_L04N_0,0,I/O,TRUE,F,6,16
+F17,GND,GND,GND,,F,6,17
+F18,IO_L38N_1/A25,1,DUAL,TRUE,F,6,18
+F19,IO_L38P_1/A24,1,DUAL,TRUE,F,6,19
+F20,IO_L30N_1/A19,1,DUAL,TRUE,F,6,20
+F21,IO_L35P_1,1,I/O,TRUE,F,6,21
+F22,IO_L33P_1,1,I/O,TRUE,F,6,22
+G1,IO_L11P_3,3,I/O,TRUE,G,7,1
+G2,GND,GND,GND,,G,7,2
+G3,IO_L01N_3,3,I/O,TRUE,G,7,3
+G4,GND,GND,GND,,G,7,4
+G5,IO_L07P_3,3,I/O,TRUE,G,7,5
+G6,IO_L07N_3,3,I/O,TRUE,G,7,6
+G7,VCCINT,VCCINT,VCCINT,,G,7,7
+G8,IO_L23P_0,0,I/O,TRUE,G,7,8
+G9,GND,GND,GND,,G,7,9
+G10,VCCAUX,VCCAUX,VCCAUX,,G,7,10
+G11,GND,GND,GND,,G,7,11
+G12,VCCAUX,VCCAUX,VCCAUX,,G,7,12
+G13,GND,GND,GND,,G,7,13
+G14,VCCAUX,VCCAUX,VCCAUX,,G,7,14
+G15,GND,GND,GND,,G,7,15
+G16,VCCINT,VCCINT,VCCINT,,G,7,16
+G17,IO_L34P_1,1,I/O,TRUE,G,7,17
+G18,IO_L34N_1,1,I/O,TRUE,G,7,18
+G19,IO_L30P_1/A18,1,DUAL,TRUE,G,7,19
+G20,IP_L31N_1,1,INPUT,TRUE,G,7,20
+G21,GND,GND,GND,,G,7,21
+G22,IO_L28N_1,1,I/O,TRUE,G,7,22
+H1,IO_L11N_3,3,I/O,TRUE,H,8,1
+H2,IO_L14P_3,3,I/O,TRUE,H,8,2
+H3,IO_L05P_3,3,I/O,TRUE,H,8,3
+H4,IO_L05N_3,3,I/O,TRUE,H,8,4
+H5,IO_L10P_3,3,I/O,TRUE,H,8,5
+H6,IO_L10N_3,3,I/O,TRUE,H,8,6
+H7,GND,GND,GND,,H,8,7
+H8,GND,GND,GND,,H,8,8
+H9,VCCINT,VCCINT,VCCINT,,H,8,9
+H10,GND,GND,GND,,H,8,10
+H11,VCCINT,VCCINT,VCCINT,,H,8,11
+H12,GND,GND,GND,,H,8,12
+H13,VCCINT,VCCINT,VCCINT,,H,8,13
+H14,GND,GND,GND,,H,8,14
+H15,VCCINT,VCCINT,VCCINT,,H,8,15
+H16,GND,GND,GND,,H,8,16
+H17,IO_L26P_1/A14,1,DUAL,TRUE,H,8,17
+H18,IO_L26N_1/A15,1,DUAL,TRUE,H,8,18
+H19,GND,GND,GND,,H,8,19
+H20,IO_L32N_1,1,I/O,TRUE,H,8,20
+H21,IP_L31P_1/VREF_1,1,VREF,TRUE,H,8,21
+H22,IO_L28P_1,1,I/O,TRUE,H,8,22
+J1,IO_L14N_3/VREF_3,3,VREF,TRUE,J,9,1
+J2,VCCO_3,3,VCCO,,J,9,2
+J3,IP_L16P_3,3,INPUT,TRUE,J,9,3
+J4,IP_L16N_3,3,INPUT,TRUE,J,9,4
+J5,VCCO_3,3,VCCO,,J,9,5
+J6,IP_L12P_3,3,INPUT,TRUE,J,9,6
+J7,IP_L12N_3/VREF_3,3,VREF,TRUE,J,9,7
+J8,VCCINT,VCCINT,VCCINT,,J,9,8
+J9,GND,GND,GND,,J,9,9
+J10,VCCINT,VCCINT,VCCINT,,J,9,10
+J11,GND,GND,GND,,J,9,11
+J12,VCCINT,VCCINT,VCCINT,,J,9,12
+J13,GND,GND,GND,,J,9,13
+J14,VCCINT,VCCINT,VCCINT,,J,9,14
+J15,GND,GND,GND,,J,9,15
+J16,VCCAUX,VCCAUX,VCCAUX,,J,9,16
+J17,IO_L29N_1/A17,1,DUAL,TRUE,J,9,17
+J18,VCCO_1,1,VCCO,,J,9,18
+J19,IO_L32P_1,1,I/O,TRUE,J,9,19
+J20,IO_L25N_1/A13,1,DUAL,TRUE,J,9,20
+J21,IP_L27P_1,1,INPUT,TRUE,J,9,21
+J22,IP_L27N_1,1,INPUT,TRUE,J,9,22
+K1,IO_L19P_3/LHCLK2,3,LHCLK,TRUE,K,10,1
+K2,IO_L17P_3,3,I/O,TRUE,K,10,2
+K3,IO_L17N_3,3,I/O,TRUE,K,10,3
+K4,IO_L13P_3,3,I/O,TRUE,K,10,4
+K5,IO_L13N_3,3,I/O,TRUE,K,10,5
+K6,IO_L15P_3,3,I/O,TRUE,K,10,6
+K7,VCCAUX,VCCAUX,VCCAUX,,K,10,7
+K8,GND,GND,GND,,K,10,8
+K9,VCCINT,VCCINT,VCCINT,,K,10,9
+K10,GND,GND,GND,,K,10,10
+K11,VCCINT,VCCINT,VCCINT,,K,10,11
+K12,GND,GND,GND,,K,10,12
+K13,VCCINT,VCCINT,VCCINT,,K,10,13
+K14,GND,GND,GND,,K,10,14
+K15,VCCINT,VCCINT,VCCINT,,K,10,15
+K16,IO_L29P_1/A16,1,DUAL,TRUE,K,10,16
+K17,IP_L23N_1,1,INPUT,TRUE,K,10,17
+K18,IO_L24N_1,1,I/O,TRUE,K,10,18
+K19,IO_L24P_1,1,I/O,TRUE,K,10,19
+K20,IO_L25P_1/A12,1,DUAL,TRUE,K,10,20
+K21,VCCO_1,1,VCCO,,K,10,21
+K22,IO_L22N_1/A11,1,DUAL,TRUE,K,10,22
+L1,IO_L19N_3/IRDY2/LHCLK3,3,LHCLK,TRUE,L,11,1
+L2,GND,GND,GND,,L,11,2
+L3,IO_L20P_3/LHCLK4,3,LHCLK,TRUE,L,11,3
+L4,VCCAUX,VCCAUX,VCCAUX,,L,11,4
+L5,IO_L15N_3,3,I/O,TRUE,L,11,5
+L6,IO_L18P_3/LHCLK0,3,LHCLK,TRUE,L,11,6
+L7,GND,GND,GND,,L,11,7
+L8,VCCINT,VCCINT,VCCINT,,L,11,8
+L9,GND,GND,GND,,L,11,9
+L10,VCCINT,VCCINT,VCCINT,,L,11,10
+L11,GND,GND,GND,,L,11,11
+L12,VCCINT,VCCINT,VCCINT,,L,11,12
+L13,GND,GND,GND,,L,11,13
+L14,VCCINT,VCCINT,VCCINT,,L,11,14
+L15,GND,GND,GND,,L,11,15
+L16,VCCAUX,VCCAUX,VCCAUX,,L,11,16
+L17,IO_L21N_1/RHCLK7,1,RHCLK,TRUE,L,11,17
+L18,IP_L23P_1/VREF_1,1,VREF,TRUE,L,11,18
+L19,GND,GND,GND,,L,11,19
+L20,IO_L20N_1/RHCLK5,1,RHCLK,TRUE,L,11,20
+L21,IO_L20P_1/RHCLK4,1,RHCLK,TRUE,L,11,21
+L22,IO_L22P_1/A10,1,DUAL,TRUE,L,11,22
+M1,IO_L22P_3/VREF_3,3,VREF,TRUE,M,12,1
+M2,IO_L20N_3/LHCLK5,3,LHCLK,TRUE,M,12,2
+M3,IP_L23P_3,3,INPUT,TRUE,M,12,3
+M4,GND,GND,GND,,M,12,4
+M5,IO_L18N_3/LHCLK1,3,LHCLK,TRUE,M,12,5
+M6,IO_L21P_3/TRDY2/LHCLK6,3,LHCLK,TRUE,M,12,6
+M7,VCCAUX,VCCAUX,VCCAUX,,M,12,7
+M8,GND,GND,GND,,M,12,8
+M9,VCCINT,VCCINT,VCCINT,,M,12,9
+M10,GND,GND,GND,,M,12,10
+M11,VCCINT,VCCINT,VCCINT,,M,12,11
+M12,GND,GND,GND,,M,12,12
+M13,VCCINT,VCCINT,VCCINT,,M,12,13
+M14,GND,GND,GND,,M,12,14
+M15,VCCINT,VCCINT,VCCINT,,M,12,15
+M16,GND,GND,GND,,M,12,16
+M17,IO_L18N_1/RHCLK1,1,RHCLK,TRUE,M,12,17
+M18,IO_L21P_1/IRDY1/RHCLK6,1,RHCLK,TRUE,M,12,18
+M19,VCCAUX,VCCAUX,VCCAUX,,M,12,19
+M20,IO_L19N_1/TRDY1/RHCLK3,1,RHCLK,TRUE,M,12,20
+M21,GND,GND,GND,,M,12,21
+M22,IO_L17N_1/A9,1,DUAL,TRUE,M,12,22
+N1,IO_L22N_3,3,I/O,TRUE,N,13,1
+N2,VCCO_3,3,VCCO,,N,13,2
+N3,IP_L31P_3,3,INPUT,TRUE,N,13,3
+N4,IP_L23N_3,3,INPUT,TRUE,N,13,4
+N5,IO_L24N_3,3,I/O,TRUE,N,13,5
+N6,IO_L24P_3,3,I/O,TRUE,N,13,6
+N7,IO_L21N_3/LHCLK7,3,LHCLK,TRUE,N,13,7
+N8,VCCINT,VCCINT,VCCINT,,N,13,8
+N9,GND,GND,GND,,N,13,9
+N10,VCCINT,VCCINT,VCCINT,,N,13,10
+N11,GND,GND,GND,,N,13,11
+N12,VCCINT,VCCINT,VCCINT,,N,13,12
+N13,GND,GND,GND,,N,13,13
+N14,VCCINT,VCCINT,VCCINT,,N,13,14
+N15,GND,GND,GND,,N,13,15
+N16,VCCAUX,VCCAUX,VCCAUX,,N,13,16
+N17,IO_L13P_1/A2,1,DUAL,TRUE,N,13,17
+N18,IO_L18P_1/RHCLK0,1,RHCLK,TRUE,N,13,18
+N19,IO_L15N_1/A7,1,DUAL,TRUE,N,13,19
+N20,IO_L15P_1/A6,1,DUAL,TRUE,N,13,20
+N21,IO_L19P_1/RHCLK2,1,RHCLK,TRUE,N,13,21
+N22,IO_L17P_1/A8,1,DUAL,TRUE,N,13,22
+P1,IO_L25P_3,3,I/O,TRUE,P,14,1
+P2,IO_L25N_3,3,I/O,TRUE,P,14,2
+P3,IP_L31N_3,3,INPUT,TRUE,P,14,3
+P4,IO_L32P_3/VREF_3,3,VREF,TRUE,P,14,4
+P5,VCCO_3,3,VCCO,,P,14,5
+P6,IO_L26P_3,3,I/O,TRUE,P,14,6
+P7,VCCAUX,VCCAUX,VCCAUX,,P,14,7
+P8,GND,GND,GND,,P,14,8
+P9,VCCINT,VCCINT,VCCINT,,P,14,9
+P10,GND,GND,GND,,P,14,10
+P11,VCCINT,VCCINT,VCCINT,,P,14,11
+P12,GND,GND,GND,,P,14,12
+P13,VCCINT,VCCINT,VCCINT,,P,14,13
+P14,GND,GND,GND,,P,14,14
+P15,VCCINT,VCCINT,VCCINT,,P,14,15
+P16,IO_L13N_1/A3,1,DUAL,TRUE,P,14,16
+P17,IP_L12N_1/VREF_1,1,VREF,TRUE,P,14,17
+P18,VCCO_1,1,VCCO,,P,14,18
+P19,IO_L10P_1,1,I/O,TRUE,P,14,19
+P20,IP_L16N_1,1,INPUT,TRUE,P,14,20
+P21,VCCO_1,1,VCCO,,P,14,21
+P22,IO_L14N_1/A5,1,DUAL,TRUE,P,14,22
+R1,IO_L28N_3,3,I/O,TRUE,R,15,1
+R2,IO_L28P_3,3,I/O,TRUE,R,15,2
+R3,IO_L34P_3,3,I/O,TRUE,R,15,3
+R4,GND,GND,GND,,R,15,4
+R5,IO_L32N_3,3,I/O,TRUE,R,15,5
+R6,IO_L26N_3,3,I/O,TRUE,R,15,6
+R7,GND,GND,GND,,R,15,7
+R8,VCCINT,VCCINT,VCCINT,,R,15,8
+R9,GND,GND,GND,,R,15,9
+R10,VCCINT,VCCINT,VCCINT,,R,15,10
+R11,GND,GND,GND,,R,15,11
+R12,VCCINT,VCCINT,VCCINT,,R,15,12
+R13,GND,GND,GND,,R,15,13
+R14,VCCINT,VCCINT,VCCINT,,R,15,14
+R15,GND,GND,GND,,R,15,15
+R16,GND,GND,GND,,R,15,16
+R17,IP_L12P_1,1,INPUT,TRUE,R,15,17
+R18,IO_L10N_1,1,I/O,TRUE,R,15,18
+R19,IO_L07P_1,1,I/O,TRUE,R,15,19
+R20,IO_L07N_1,1,I/O,TRUE,R,15,20
+R21,IP_L16P_1/VREF_1,1,VREF,TRUE,R,15,21
+R22,IO_L14P_1/A4,1,DUAL,TRUE,R,15,22
+T1,IO_L30P_3,3,I/O,TRUE,T,16,1
+T2,GND,GND,GND,,T,16,2
+T3,IP_L27P_3,3,INPUT,TRUE,T,16,3
+T4,IO_L34N_3,3,I/O,TRUE,T,16,4
+T5,IO_L29N_3,3,I/O,TRUE,T,16,5
+T6,IO_L29P_3,3,I/O,TRUE,T,16,6
+T7,VCCINT,VCCINT,VCCINT,,T,16,7
+T8,GND,GND,GND,,T,16,8
+T9,VCCAUX,VCCAUX,VCCAUX,,T,16,9
+T10,GND,GND,GND,,T,16,10
+T11,VCCAUX,VCCAUX,VCCAUX,,T,16,11
+T12,GND,GND,GND,,T,16,12
+T13,VCCAUX,VCCAUX,VCCAUX,,T,16,13
+T14,GND,GND,GND,,T,16,14
+T15,GND,GND,GND,,T,16,15
+T16,VCCINT,VCCINT,VCCINT,,T,16,16
+T17,IO_L05N_1,1,I/O,TRUE,T,16,17
+T18,IO_L05P_1,1,I/O,TRUE,T,16,18
+T19,GND,GND,GND,,T,16,19
+T20,IO_L09N_1,1,I/O,TRUE,T,16,20
+T21,GND,GND,GND,,T,16,21
+T22,IO_L11N_1/VREF_1,1,VREF,TRUE,T,16,22
+U1,IO_L30N_3,3,I/O,TRUE,U,17,1
+U2,IO_L33P_3,3,I/O,TRUE,U,17,2
+U3,IP_L27N_3,3,INPUT,TRUE,U,17,3
+U4,IO_L38P_3,3,I/O,TRUE,U,17,4
+U5,IO_L38N_3,3,I/O,TRUE,U,17,5
+U6,GND,GND,GND,,U,17,6
+U7,IO_L02N_2/CSO_B,2,DUAL,TRUE,U,17,7
+U8,IO_L11N_2,2,I/O,TRUE,U,17,8
+U9,IO_L10N_2,2,I/O,TRUE,U,17,9
+U10,IO_L14N_2/D4,2,DUAL,TRUE,U,17,10
+U11,GND,GND,GND,,U,17,11
+U12,IO_L17P_2/GCLK0,2,GCLK,TRUE,U,17,12
+U13,IO_L20P_2,2,I/O,TRUE,U,17,13
+U14,IO_L25P_2,2,I/O,TRUE,U,17,14
+U15,IO_L25N_2,2,I/O,TRUE,U,17,15
+U16,IO_L28P_2,2,I/O,TRUE,U,17,16
+U17,GND,GND,GND,,U,17,17
+U18,IO_L01P_1/HDC,1,DUAL,TRUE,U,17,18
+U19,IO_L01N_1/LDC2,1,DUAL,TRUE,U,17,19
+U20,IO_L09P_1,1,I/O,TRUE,U,17,20
+U21,IP_L08N_1/VREF_1,1,VREF,TRUE,U,17,21
+U22,IO_L11P_1,1,I/O,TRUE,U,17,22
+V1,IO_L33N_3,3,I/O,TRUE,V,18,1
+V2,VCCO_3,3,VCCO,,V,18,2
+V3,IO_L36N_3,3,I/O,TRUE,V,18,3
+V4,IO_L36P_3,3,I/O,TRUE,V,18,4
+V5,VCCAUX,VCCAUX,VCCAUX,,V,18,5
+V6,IO_L02P_2/M2,2,DUAL,TRUE,V,18,6
+V7,IO_L11P_2,2,I/O,TRUE,V,18,7
+V8,IO_L06N_2,2,I/O,TRUE,V,18,8
+V9,VCCO_2,2,VCCO,,V,18,9
+V10,IO_L10P_2,2,I/O,TRUE,V,18,10
+V11,IO_L14P_2/D5,2,DUAL,TRUE,V,18,11
+V12,IO_L17N_2/GCLK1,2,GCLK,TRUE,V,18,12
+V13,IO_L20N_2/MOSI/CSI_B,2,DUAL,TRUE,V,18,13
+V14,VCCO_2,2,VCCO,,V,18,14
+V15,IP_2/VREF_2,2,VREF,,V,18,15
+V16,IO_L28N_2,2,I/O,TRUE,V,18,16
+V17,IO_L31N_2/CCLK,2,DUAL,TRUE,V,18,17
+V18,VCCAUX,VCCAUX,VCCAUX,,V,18,18
+V19,SUSPEND,1,PWRMGMT,,V,18,19
+V20,IO_L03N_1/A1,1,DUAL,TRUE,V,18,20
+V21,VCCO_1,1,VCCO,,V,18,21
+V22,IP_L08P_1,1,INPUT,TRUE,V,18,22
+W1,IO_L35N_3,3,I/O,TRUE,W,19,1
+W2,IO_L37N_3,3,I/O,TRUE,W,19,2
+W3,IO_L37P_3,3,I/O,TRUE,W,19,3
+W4,IP_2/VREF_2,2,VREF,,W,19,4
+W5,IO_L03P_2,2,I/O,TRUE,W,19,5
+W6,IO_L07N_2/VS2,2,DUAL,TRUE,W,19,6
+W7,GND,GND,GND,,W,19,7
+W8,IO_L06P_2,2,I/O,TRUE,W,19,8
+W9,IP_2/VREF_2,2,VREF,,W,19,9
+W10,IP_2,2,INPUT,,W,19,10
+W11,VCCAUX,VCCAUX,VCCAUX,,W,19,11
+W12,GND,GND,GND,,W,19,12
+W13,IP_2/VREF_2,2,VREF,,W,19,13
+W14,IO_L21N_2,2,I/O,TRUE,W,19,14
+W15,IO_L24P_2/INIT_B,2,DUAL,TRUE,W,19,15
+W16,GND,GND,GND,,W,19,16
+W17,IO_L31P_2/D0/DIN/MISO,2,DUAL,TRUE,W,19,17
+W18,IP_2/VREF_2,2,VREF,,W,19,18
+W19,IO_L03P_1/A0,1,DUAL,TRUE,W,19,19
+W20,IP_L04N_1/VREF_1,1,VREF,TRUE,W,19,20
+W21,IP_L04P_1,1,INPUT,TRUE,W,19,21
+W22,IO_L06P_1,1,I/O,TRUE,W,19,22
+Y1,IO_L35P_3,3,I/O,TRUE,Y,20,1
+Y2,IP_L39P_3,3,INPUT,TRUE,Y,20,2
+Y3,GND,GND,GND,,Y,20,3
+Y4,IO_L03N_2,2,I/O,TRUE,Y,20,4
+Y5,IO_L07P_2/RDWR_B,2,DUAL,TRUE,Y,20,5
+Y6,IP_2,2,INPUT,,Y,20,6
+Y7,IP_2,2,INPUT,,Y,20,7
+Y8,IO_L13P_2,2,I/O,TRUE,Y,20,8
+Y9,IO_L13N_2,2,I/O,TRUE,Y,20,9
+Y10,IO_L15N_2/GCLK13,2,GCLK,TRUE,Y,20,10
+Y11,IO_L15P_2/GCLK12,2,GCLK,TRUE,Y,20,11
+Y12,IP_2,2,INPUT,,Y,20,12
+Y13,IO_L21P_2,2,I/O,TRUE,Y,20,13
+Y14,IP_2/VREF_2,2,VREF,,Y,20,14
+Y15,IO_L24N_2/D3,2,DUAL,TRUE,Y,20,15
+Y16,IO_L29N_2,2,I/O,TRUE,Y,20,16
+Y17,IO_L29P_2,2,I/O,TRUE,Y,20,17
+Y18,IO_L26P_2/D2,2,DUAL,TRUE,Y,20,18
+Y19,IO_L26N_2/D1,2,DUAL,TRUE,Y,20,19
+Y20,GND,GND,GND,,Y,20,20
+Y21,IO_L02P_1/LDC1,1,DUAL,TRUE,Y,20,21
+Y22,IO_L06N_1,1,I/O,TRUE,Y,20,22
Added: usrp-hw/trunk/sym/generated/spi-flash-so16.src
===================================================================
--- usrp-hw/trunk/sym/generated/spi-flash-so16.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/spi-flash-so16.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,69 @@
+# This is the template file for creating symbols with tragesym
+# every line starting with '#' is a comment line.
+
+[options]
+# rotate_labels rotates the pintext of top and bottom pins
+# wordswap swaps labels if the pin is on the right side an looks like this:
+# "PB1 (CLK)"
+wordswap=yes
+rotate_labels=no
+sort_labels=no
+generate_pinseq=yes
+sym_width=1400
+pinwidthvertikal=400
+pinwidthhorizontal=400
+
+[geda_attr]
+# name will be printed in the top of the symbol
+# if you have a device with slots, you'll have to use slot= and slotdef=
+# use comment= if there are special information you want to add
+version=20060906
+name=SPI-FLASH-SO16
+device=SPI-FLASH-SO16
+refdes=U?
+footprint==SO16
+description=Many vendors SPI Flash, 3.3V
+documentation=NA
+author=mettus
+numslots=0
+#slot=1
+#slotdef=1:
+#slotdef=2:
+#slotdef=3:
+#slotdef=4:
+comment=Intel QH25Fxx0S33, ST M25Pxx
+#comment=
+#comment=
+
+[pins]
+# tabseparated list of pin descriptions
+# pinnr is the physical number of the pin
+# seq is the pinseq= attribute, leave it blank if it doesn't matter
+# type can be (in, out, io, oc, oe, pas, tp, tri, clk, pwr)
+# style can be (line,dot,clk,dotclk,none). none if only want to add a net
+# posit. can be (l,r,t,b) or empty for nets
+# net specifies the name of the Vcc or GND name
+# label represents the pinlabel.
+# negation lines can be added with _Q_
+# if you want to add a "_" or "\" use "\_" and "\\" as escape sequences
+#-----------------------------------------------------
+#pinnr seq type style posit. net label
+#-----------------------------------------------------
+7 in dot l \_SEL\_
+16 in clk l SCLK
+15 in line l MOSI
+8 out line l MISO
+
+1 in dot l \_HOLD\_
+9 in dot l \_W\_
+
+2 pwr line r Vcc
+3 in line r NC
+4 in line r NC
+5 in line r NC
+6 in line r NC
+11 in line r NC
+12 in line r NC
+13 in line r NC
+14 in line r NC
+10 pwr line r Vss
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-BOTCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-BOTCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-BOTCLK.src 2007-10-08
21:30:13 UTC (rev 6596)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-BOTCLK
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA12 clk clk l IO_L16P_2/GCLK14
+AA14 clk clk l IO_L18N_2/GCLK2
+AB12 clk clk l IO_L16N_2/GCLK15
+AB13 clk clk l IO_L18P_2
+U12 clk clk l IO_L17P_2/GCLK0
+V12 clk clk l IO_L17N_2/GCLK1
+Y10 clk clk l IO_L15N_2/GCLK13
+Y11 clk clk l IO_L15P_2/GCLK12
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-CFG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-CFG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-CFG.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,45 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-CFG
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A2 io line b PROG_B
+AA3 io line r IO_L01P_2/M1
+AA10 io line r IO_L12N_2/D6
+AA17 io line b IO_L22P_2/AWAKE
+AB3 io line r IO_L01N_2/M0
+AB8 io line r IO_L09P_2/VS1
+AB9 io line r IO_L09N_2/VS0
+AB10 io line r IO_L12P_2/D7
+AB16 io line r IO_L22N_2/DOUT
+AB21 io line b DONE
+F7 io line l IO_L31N_0/PUDC_B
+U7 io line r IO_L02N_2/CSO_B
+U10 io line r IO_L14N_2/D4
+V6 io line r IO_L02P_2/M2
+V11 io line r IO_L14P_2/D5
+V13 io line r IO_L20N_2/MOSI/CSI_B
+V17 io line r IO_L31N_2/CCLK
+V19 io line b SUSPEND
+W6 io line r IO_L07N_2/VS2
+W15 io line r IO_L24P_2/INIT_B
+W17 io line r IO_L31P_2/D0/DIN/MISO
+Y5 io line r IO_L07P_2/RDWR_B
+Y15 io line r IO_L24N_2/D3
+Y18 io line r IO_L26P_2/D2
+Y19 io line r IO_L26N_2/D1
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO0.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO0.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO0.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,94 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-IO0
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A3 io line l IO_L30N_0
+A4 io line l IO_L28N_0
+A5 io line l IO_L25N_0
+A6 io line l IO_L25P_0
+A7 io line r IO_L24N_0/VREF_0
+A10 in line r IP_0
+A11 io line l IO_L15N_0
+A12 in line r IP_0
+A13 io line l IO_L11P_0
+A14 io line l IO_L10P_0
+A15 in line r IP_0
+A16 io line r IO_L06P_0/VREF_0
+A17 io line l IO_L06N_0
+A18 in line r IP_0
+A19 io line l IO_L07N_0
+A20 io line l IO_0
+B3 io line l IO_L30P_0
+B4 io line l IO_L28P_0
+B5 pwr line b VCCO_0
+B6 io line l IO_L24P_0
+B10 pwr line b VCCO_0
+B11 io line l IO_L15P_0
+B13 io line l IO_L11N_0
+B14 pwr line b VCCO_0
+B15 io line l IO_L10N_0
+B17 io line l IO_L03P_0
+B18 pwr line b VCCO_0
+B19 io line l IO_L02N_0
+B20 io line l IO_L07P_0
+C4 io line l IO_L29N_0
+C5 in line r IP_0
+C6 io line l IO_L21P_0
+C7 io line l IO_L26P_0
+C8 io line l IO_L22P_0
+C9 io line l IO_L16P_0
+C10 in line r IP_0
+C11 io line r IP_0/VREF_0
+C12 io line l IO_L14N_0
+C13 io line l IO_L14P_0
+C14 in line r IP_0
+C15 io line r IO_L12N_0/VREF_0
+C16 io line l IO_L08N_0
+C17 io line l IO_L03N_0
+C18 io line r IO_L02P_0/VREF_0
+C19 io line l IO_L01N_0
+D5 io line l IO_L29P_0
+D6 io line l IO_L21N_0
+D7 io line l IO_L26N_0
+D9 io line l IO_L22N_0
+D10 io line l IO_L16N_0
+D13 io line l IO_L09N_0
+D14 io line l IO_L12P_0
+D15 io line l IO_L08P_0
+D17 in line r IP_0
+D18 in line r IP_0
+D19 io line l IO_L01P_0
+E6 in line r IP_0
+E7 io line r IO_L31P_0/VREF_0
+E8 io line l IO_L27N_0
+E9 pwr line b VCCO_0
+E10 in line r IP_0
+E13 io line l IO_L09P_0
+E14 pwr line b VCCO_0
+E15 io line l IO_L05P_0
+E16 io line l IO_L04P_0
+E17 in line r IP_0
+F8 io line l IO_L27P_0
+F9 io line l IO_L23N_0
+F12 in line r IP_0
+F13 io line l IO_L13N_0
+F14 io line l IO_L13P_0
+F15 io line l IO_L05N_0
+F16 io line l IO_L04N_0
+G8 io line l IO_L23P_0
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO1.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO1.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO1.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,96 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-IO1
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA22 io line l IO_L02N_1/LDC0
+C21 in line r IP_L39N_1
+C22 io line r IP_L39P_1/VREF_1
+D20 io line l IO_L36P_1/A20
+D21 io line l IO_L37P_1/A22
+D22 io line l IO_L37N_1/A23
+E19 io line l IO_L36N_1/A21
+E20 io line l IO_L35N_1
+E21 pwr line b VCCO_1
+E22 io line l IO_L33N_1
+F18 io line l IO_L38N_1/A25
+F19 io line l IO_L38P_1/A24
+F20 io line l IO_L30N_1/A19
+F21 io line l IO_L35P_1
+F22 io line l IO_L33P_1
+G17 io line l IO_L34P_1
+G18 io line l IO_L34N_1
+G19 io line l IO_L30P_1/A18
+G20 in line r IP_L31N_1
+G22 io line l IO_L28N_1
+H17 io line l IO_L26P_1/A14
+H18 io line l IO_L26N_1/A15
+H20 io line l IO_L32N_1
+H21 io line r IP_L31P_1/VREF_1
+H22 io line l IO_L28P_1
+J17 io line l IO_L29N_1/A17
+J18 pwr line b VCCO_1
+J19 io line l IO_L32P_1
+J20 io line l IO_L25N_1/A13
+J21 in line r IP_L27P_1
+J22 in line r IP_L27N_1
+K16 io line l IO_L29P_1/A16
+K17 in line r IP_L23N_1
+K18 io line l IO_L24N_1
+K19 io line l IO_L24P_1
+K20 io line l IO_L25P_1/A12
+K21 pwr line b VCCO_1
+K22 io line l IO_L22N_1/A11
+L18 io line r IP_L23P_1/VREF_1
+L22 io line l IO_L22P_1/A10
+M22 io line l IO_L17N_1/A9
+N17 io line l IO_L13P_1/A2
+N19 io line l IO_L15N_1/A7
+N20 io line l IO_L15P_1/A6
+N22 io line l IO_L17P_1/A8
+P16 io line l IO_L13N_1/A3
+P17 io line r IP_L12N_1/VREF_1
+P18 pwr line b VCCO_1
+P19 io line l IO_L10P_1
+P20 in line r IP_L16N_1
+P21 pwr line b VCCO_1
+P22 io line l IO_L14N_1/A5
+R17 in line r IP_L12P_1
+R18 io line l IO_L10N_1
+R19 io line l IO_L07P_1
+R20 io line l IO_L07N_1
+R21 io line r IP_L16P_1/VREF_1
+R22 io line l IO_L14P_1/A4
+T17 io line l IO_L05N_1
+T18 io line l IO_L05P_1
+T20 io line l IO_L09N_1
+T22 io line r IO_L11N_1/VREF_1
+U18 io line l IO_L01P_1/HDC
+U19 io line l IO_L01N_1/LDC2
+U20 io line l IO_L09P_1
+U21 io line r IP_L08N_1/VREF_1
+U22 io line l IO_L11P_1
+V20 io line l IO_L03N_1/A1
+V21 pwr line b VCCO_1
+V22 in line r IP_L08P_1
+W19 io line l IO_L03P_1/A0
+W20 io line r IP_L04N_1/VREF_1
+W21 in line r IP_L04P_1
+W22 io line l IO_L06P_1
+Y21 io line l IO_L02P_1/LDC1
+Y22 io line l IO_L06N_1
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO2.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO2.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO2.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,73 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-IO2
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA4 io line l IO_L04N_2
+AA5 pwr line b VCCO_2
+AA6 in line r IP_2
+AA8 io line l IO_L08N_2
+AA9 pwr line b VCCO_2
+AA13 pwr line b VCCO_2
+AA15 io line l IO_L19P_2
+AA18 pwr line b VCCO_2
+AA19 io line l IO_L27N_2
+AA20 io line l IO_L30P_2
+AB2 io line r IP_2/VREF_2
+AB4 io line l IO_L04P_2
+AB5 io line l IO_L05P_2
+AB6 io line l IO_L05N_2
+AB7 io line l IO_L08P_2
+AB11 io line r IP_2/VREF_2
+AB14 io line l IO_L19N_2
+AB15 in line r IP_2
+AB17 io line l IO_L23P_2
+AB18 io line l IO_L23N_2
+AB19 io line l IO_L27P_2
+AB20 io line l IO_L30N_2
+U8 io line l IO_L11N_2
+U9 io line l IO_L10N_2
+U13 io line l IO_L20P_2
+U14 io line l IO_L25P_2
+U15 io line l IO_L25N_2
+U16 io line l IO_L28P_2
+V7 io line l IO_L11P_2
+V8 io line l IO_L06N_2
+V9 pwr line b VCCO_2
+V10 io line l IO_L10P_2
+V14 pwr line b VCCO_2
+V15 io line r IP_2/VREF_2
+V16 io line l IO_L28N_2
+W4 io line r IP_2/VREF_2
+W5 io line l IO_L03P_2
+W8 io line l IO_L06P_2
+W9 io line r IP_2/VREF_2
+W10 in line r IP_2
+W13 io line r IP_2/VREF_2
+W14 io line l IO_L21N_2
+W18 io line r IP_2/VREF_2
+Y4 io line l IO_L03N_2
+Y6 in line r IP_2
+Y7 in line r IP_2
+Y8 io line l IO_L13P_2
+Y9 io line l IO_L13N_2
+Y12 in line r IP_2
+Y13 io line l IO_L21P_2
+Y14 io line r IP_2/VREF_2
+Y16 io line l IO_L29N_2
+Y17 io line l IO_L29P_2
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO3.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO3.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-IO3.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,96 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-IO3
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+AA1 io line r IP_L39N_3/VREF_3
+C1 io line l IO_L02N_3
+C2 io line l IO_L02P_3
+D1 in line r IP_L04P_3
+D3 in line r IP_L08P_3
+D4 in line r IP_L08N_3
+E1 io line r IP_L04N_3/VREF_3
+E2 pwr line b VCCO_3
+E3 io line l IO_L09P_3
+E4 io line l IO_L09N_3
+F1 io line l IO_L06N_3
+F2 io line l IO_L06P_3
+F3 io line l IO_L01P_3
+F4 io line l IO_L03P_3
+F5 io line l IO_L03N_3
+G1 io line l IO_L11P_3
+G3 io line l IO_L01N_3
+G5 io line l IO_L07P_3
+G6 io line l IO_L07N_3
+H1 io line l IO_L11N_3
+H2 io line l IO_L14P_3
+H3 io line l IO_L05P_3
+H4 io line l IO_L05N_3
+H5 io line l IO_L10P_3
+H6 io line l IO_L10N_3
+J1 io line r IO_L14N_3/VREF_3
+J2 pwr line b VCCO_3
+J3 in line r IP_L16P_3
+J4 in line r IP_L16N_3
+J5 pwr line b VCCO_3
+J6 in line r IP_L12P_3
+J7 io line r IP_L12N_3/VREF_3
+K2 io line l IO_L17P_3
+K3 io line l IO_L17N_3
+K4 io line l IO_L13P_3
+K5 io line l IO_L13N_3
+K6 io line l IO_L15P_3
+L5 io line l IO_L15N_3
+M1 io line r IO_L22P_3/VREF_3
+M3 in line r IP_L23P_3
+N1 io line l IO_L22N_3
+N2 pwr line b VCCO_3
+N3 in line r IP_L31P_3
+N4 in line r IP_L23N_3
+N5 io line l IO_L24N_3
+N6 io line l IO_L24P_3
+P1 io line l IO_L25P_3
+P2 io line l IO_L25N_3
+P3 in line r IP_L31N_3
+P4 io line r IO_L32P_3/VREF_3
+P5 pwr line b VCCO_3
+P6 io line l IO_L26P_3
+R1 io line l IO_L28N_3
+R2 io line l IO_L28P_3
+R3 io line l IO_L34P_3
+R5 io line l IO_L32N_3
+R6 io line l IO_L26N_3
+T1 io line l IO_L30P_3
+T3 in line r IP_L27P_3
+T4 io line l IO_L34N_3
+T5 io line l IO_L29N_3
+T6 io line l IO_L29P_3
+U1 io line l IO_L30N_3
+U2 io line l IO_L33P_3
+U3 in line r IP_L27N_3
+U4 io line l IO_L38P_3
+U5 io line l IO_L38N_3
+V1 io line l IO_L33N_3
+V2 pwr line b VCCO_3
+V3 io line l IO_L36N_3
+V4 io line l IO_L36P_3
+W1 io line l IO_L35N_3
+W2 io line l IO_L37N_3
+W3 io line l IO_L37P_3
+Y1 io line l IO_L35P_3
+Y2 in line r IP_L39P_3
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-JTAG.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-JTAG.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-JTAG.src 2007-10-08
21:30:13 UTC (rev 6596)
@@ -0,0 +1,24 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-JTAG
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A21 io line l TCK
+B1 io line l TMS
+B22 io line l TDO
+D2 io line l TDI
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-LHCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-LHCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-LHCLK.src 2007-10-08
21:30:13 UTC (rev 6596)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-LHCLK
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+K1 clk clk l IO_L19P_3/LHCLK2
+L1 clk clk l IO_L19N_3/IRDY2/LHCLK3
+L3 clk clk l IO_L20P_3/LHCLK4
+L6 clk clk l IO_L18P_3/LHCLK0
+M2 clk clk l IO_L20N_3/LHCLK5
+M5 clk clk l IO_L18N_3/LHCLK1
+M6 clk clk l IO_L21P_3/TRDY2/LHCLK6
+N7 clk clk l IO_L21N_3/LHCLK7
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-PWR.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-PWR.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-PWR.src 2007-10-08 21:30:13 UTC
(rev 6596)
@@ -0,0 +1,164 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-PWR
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A1 pwr line r GND
+A22 pwr line r GND
+AA2 pwr line l VCCAUX
+AA7 pwr line r GND
+AA11 pwr line r GND
+AA16 pwr line r GND
+AA21 pwr line l VCCAUX
+AB1 pwr line r GND
+AB22 pwr line r GND
+B2 pwr line l VCCAUX
+B7 pwr line r GND
+B12 pwr line r GND
+B16 pwr line r GND
+B21 pwr line l VCCAUX
+C3 pwr line r GND
+C20 pwr line r GND
+D8 pwr line r GND
+D11 pwr line r GND
+D12 pwr line l VCCAUX
+D16 pwr line r GND
+E5 pwr line l VCCAUX
+E18 pwr line l VCCAUX
+F6 pwr line r GND
+F17 pwr line r GND
+G2 pwr line r GND
+G4 pwr line r GND
+G7 pwr line l VCCINT
+G9 pwr line r GND
+G10 pwr line l VCCAUX
+G11 pwr line r GND
+G12 pwr line l VCCAUX
+G13 pwr line r GND
+G14 pwr line l VCCAUX
+G15 pwr line r GND
+G16 pwr line l VCCINT
+G21 pwr line r GND
+H7 pwr line r GND
+H8 pwr line r GND
+H9 pwr line l VCCINT
+H10 pwr line r GND
+H11 pwr line l VCCINT
+H12 pwr line r GND
+H13 pwr line l VCCINT
+H14 pwr line r GND
+H15 pwr line l VCCINT
+H16 pwr line r GND
+H19 pwr line r GND
+J8 pwr line l VCCINT
+J9 pwr line r GND
+J10 pwr line l VCCINT
+J11 pwr line r GND
+J12 pwr line l VCCINT
+J13 pwr line r GND
+J14 pwr line l VCCINT
+J15 pwr line r GND
+J16 pwr line l VCCAUX
+K7 pwr line l VCCAUX
+K8 pwr line r GND
+K9 pwr line l VCCINT
+K10 pwr line r GND
+K11 pwr line l VCCINT
+K12 pwr line r GND
+K13 pwr line l VCCINT
+K14 pwr line r GND
+K15 pwr line l VCCINT
+L2 pwr line r GND
+L4 pwr line l VCCAUX
+L7 pwr line r GND
+L8 pwr line l VCCINT
+L9 pwr line r GND
+L10 pwr line l VCCINT
+L11 pwr line r GND
+L12 pwr line l VCCINT
+L13 pwr line r GND
+L14 pwr line l VCCINT
+L15 pwr line r GND
+L16 pwr line l VCCAUX
+L19 pwr line r GND
+M4 pwr line r GND
+M7 pwr line l VCCAUX
+M8 pwr line r GND
+M9 pwr line l VCCINT
+M10 pwr line r GND
+M11 pwr line l VCCINT
+M12 pwr line r GND
+M13 pwr line l VCCINT
+M14 pwr line r GND
+M15 pwr line l VCCINT
+M16 pwr line r GND
+M19 pwr line l VCCAUX
+M21 pwr line r GND
+N8 pwr line l VCCINT
+N9 pwr line r GND
+N10 pwr line l VCCINT
+N11 pwr line r GND
+N12 pwr line l VCCINT
+N13 pwr line r GND
+N14 pwr line l VCCINT
+N15 pwr line r GND
+N16 pwr line l VCCAUX
+P7 pwr line l VCCAUX
+P8 pwr line r GND
+P9 pwr line l VCCINT
+P10 pwr line r GND
+P11 pwr line l VCCINT
+P12 pwr line r GND
+P13 pwr line l VCCINT
+P14 pwr line r GND
+P15 pwr line l VCCINT
+R4 pwr line r GND
+R7 pwr line r GND
+R8 pwr line l VCCINT
+R9 pwr line r GND
+R10 pwr line l VCCINT
+R11 pwr line r GND
+R12 pwr line l VCCINT
+R13 pwr line r GND
+R14 pwr line l VCCINT
+R15 pwr line r GND
+R16 pwr line r GND
+T2 pwr line r GND
+T7 pwr line l VCCINT
+T8 pwr line r GND
+T9 pwr line l VCCAUX
+T10 pwr line r GND
+T11 pwr line l VCCAUX
+T12 pwr line r GND
+T13 pwr line l VCCAUX
+T14 pwr line r GND
+T15 pwr line r GND
+T16 pwr line l VCCINT
+T19 pwr line r GND
+T21 pwr line r GND
+U6 pwr line r GND
+U11 pwr line r GND
+U17 pwr line r GND
+V5 pwr line l VCCAUX
+V18 pwr line l VCCAUX
+W7 pwr line r GND
+W11 pwr line l VCCAUX
+W12 pwr line r GND
+W16 pwr line r GND
+Y3 pwr line r GND
+Y20 pwr line r GND
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-RHCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-RHCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-RHCLK.src 2007-10-08
21:30:13 UTC (rev 6596)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-RHCLK
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+L17 clk clk l IO_L21N_1/RHCLK7
+L20 clk clk l IO_L20N_1/RHCLK5
+L21 clk clk l IO_L20P_1/RHCLK4
+M17 clk clk l IO_L18N_1/RHCLK1
+M18 clk clk l IO_L21P_1/IRDY1/RHCLK6
+M20 clk clk l IO_L19N_1/TRDY1/RHCLK3
+N18 clk clk l IO_L18P_1/RHCLK0
+N21 clk clk l IO_L19P_1/RHCLK2
Added: usrp-hw/trunk/sym/generated/xc3sd1800acs484-TOPCLK.src
===================================================================
--- usrp-hw/trunk/sym/generated/xc3sd1800acs484-TOPCLK.src
(rev 0)
+++ usrp-hw/trunk/sym/generated/xc3sd1800acs484-TOPCLK.src 2007-10-08
21:30:13 UTC (rev 6596)
@@ -0,0 +1,28 @@
+
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-TOPCLK
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+A8 clk clk l IO_L20P_0/GCLK10
+A9 clk clk l IO_L18P_0/GCLK6
+B8 clk clk l IO_L20N_0/GCLK11
+B9 clk clk l IO_L18N_0/GCLK7
+E11 clk clk l IO_L19N_0/GCLK9
+E12 clk clk l IO_L17P_0/GCLK4
+F10 clk clk l IO_L19P_0/GCLK8
+F11 clk clk l IO_L17N_0/GCLK5
Added: usrp-hw/trunk/sym/generated/xilinxgen484
===================================================================
--- usrp-hw/trunk/sym/generated/xilinxgen484 (rev 0)
+++ usrp-hw/trunk/sym/generated/xilinxgen484 2007-10-08 21:30:13 UTC (rev
6596)
@@ -0,0 +1,125 @@
+#!/usr/bin/python
+
+import re
+matchstr = re.compile("_")
+
+def writepin(file,number,name,linetype,pintype,pos):
+ #newname = matchstr.sub("\\_",name)
+ newname = name
+ file.write("%s\t\t%s\t%s\t%s\t\t%s\n" %
(number,pintype,linetype,pos,newname))
+
+pinfile = open ('XC3SD1800ACS484.csv','r')
+
+boilerplate = '''
+[options]
+wordswap=yes
+rotate_labels=yes
+sort_labels=yes
+generate_pinseq=yes
+sym_width=3200
+pinwidthvertikal=400
+pinwidthhorizontal=400
+[geda_attr]
+version=20060906
+name=XC3SD1800ACS484-%s
+device=XC3SD1800ACS484
+refdes=U?
+footprint=CS484
+description=Xilinx Spartan 3A-DSP 1800 CS484
+documentation=http://www.xilinx.com
+author=xilinxgen.py
+numslots=0
+[pins]
+'''
+
+configfile = open ('xc3sd1800acs484-CFG.src', 'w')
+configfile.write(boilerplate % ("CFG",))
+
+jtagfile = open ('xc3sd1800acs484-JTAG.src', 'w')
+jtagfile.write(boilerplate % ("JTAG",))
+powerfile = open ('xc3sd1800acs484-PWR.src', 'w')
+powerfile.write(boilerplate % ("PWR",))
+topclockfile = open ('xc3sd1800acs484-TOPCLK.src', 'w')
+topclockfile.write(boilerplate % ("TOPCLK",))
+botclockfile = open ('xc3sd1800acs484-BOTCLK.src', 'w')
+botclockfile.write(boilerplate % ("BOTCLK",))
+lhclockfile = open ('xc3sd1800acs484-LHCLK.src', 'w')
+lhclockfile.write(boilerplate % ("LHCLK",))
+rhclockfile = open ('xc3sd1800acs484-RHCLK.src', 'w')
+rhclockfile.write(boilerplate % ("RHCLK",))
+
+iofiles = [0] * 4
+for i in range(4):
+ iofiles[i] = open ( ('xc3sd1800acs484-IO%d.src' % (i,)), 'w')
+ iofiles[i].write(boilerplate % ('IO%d' % (i,),))
+
+dummy = pinfile.readline()
+lines = pinfile.readlines()
+
+for line in lines:
+ elements = line.strip().split(',')
+
+ pintype = elements[3]
+ #nc = elements[5] == "N.C."
+
+ #if(elements[5] != elements[9]) and not nc:
+ # print "error"
+ # print elements
+
+ #if nc and pintype != 'I/O' and pintype != 'VREF':
+ # print "error"
+ # print elements
+
+ if(pintype == 'GND'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','r')
+ elif(pintype == 'VCCAUX'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+ elif(pintype == 'VCCO'):
+ #writepin(powerfile,elements[3],elements[6],'line','pwr','l')
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','pwr','b')
+ elif(pintype == 'VCCINT'):
+ writepin(powerfile,elements[0],elements[1],'line','pwr','l')
+
+ elif(pintype == 'JTAG'):
+ writepin(jtagfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'CONFIG'):
+ writepin(configfile,elements[0],elements[1],'line','io','b')
+
+ elif(pintype == 'PWRMGMT'):
+ writepin(configfile,elements[0],elements[1],'line','io','b')
+
+ elif(pintype == 'DUAL'):
+ if(int(elements[2]) == 1): # All these are for BPI mode, so just put
in bank 1
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+ elif(int(elements[2]) == 2):
+ writepin(configfile,elements[0],elements[1],'line','io','r')
+ else:
+ writepin(configfile,elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'GCLK'):
+ if(int(elements[2]) == 0):
+ writepin(topclockfile,elements[0],elements[1],'clk','clk','l')
+ else:
+ writepin(botclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'LHCLK'):
+ writepin(lhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'RHCLK'):
+ writepin(rhclockfile,elements[0],elements[1],'clk','clk','l')
+
+ elif(pintype == 'VREF'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','r')
+
+ elif(pintype == 'I/O'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','io','l')
+
+ elif(pintype == 'INPUT'):
+
writepin(iofiles[int(elements[2])],elements[0],elements[1],'line','in','r')
+
+ elif(pintype == 'DCI'):
+ writepin(iofiles[int(elements[12])],elements[3],"%s/DCI" %
(elements[6],),'line','io','l')
+
+ else:
+ print elements
Property changes on: usrp-hw/trunk/sym/generated/xilinxgen484
___________________________________________________________________
Name: svn:executable
+ *
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