[Commit-gnuradio] r6591 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-10-05 15:09:02 -0600 (Fri, 05 Oct 2007)
New Revision: 6591

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
Log:
random changes, seems to work, I don't trust the Xilinx tools


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-05 00:20:23 UTC (rev 6590)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ucf       
2007-10-05 21:09:02 UTC (rev 6591)
@@ -302,24 +302,17 @@
 #PACE: Start of PACE Area Constraints
 #PACE: Start of PACE Prohibit Constraints
 #PACE: End of Constraints generated by PACE
-NET "clk_fpga_p" TNM_NET = "clk_fpga_p";
-TIMESPEC "TS_clk_fpga_p" = PERIOD "clk_fpga_p" 10 ns HIGH 50 %;
-#NET "RAM_CE1n" TNM_NET = "RAM_CE1n";
-#TIMESPEC "TS_RAM_CE1n" = PERIOD "RAM_CE1n" 40 ns HIGH 50 %;
-#NET "wb_clk" TNM_NET = "wb_clk"
-#TIMESPEC "TS_wb_clk" = PERIOD "wb_clk" "TS_dsp_clk" * 2
-NET "cpld_clk" TNM_NET = "cpld_clk";
-NET "dsp_clk" TNM_NET = "dsp_clk";
-TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
-#TIMESPEC "TS_aux_to_dsp" = FROM "RAM_CE1n" TO "dsp_clk"  TIG;
-#TIMESPEC "TS_dsp_to_aux" = FROM "dsp_clk" TO "RAM_CE1n"  TIG;
+NET "clk_muxed" TNM_NET = "clk_muxed";
+TIMESPEC "TS_clk_muxed" = PERIOD "clk_muxed" 10 ns HIGH 50 %;
 NET "clk_to_mac" TNM_NET = "clk_to_mac";
 TIMESPEC "TS_clk_to_mac" = PERIOD "clk_to_mac" 8 ns HIGH 50 %;
+NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
+TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;
+NET "cpld_clk" TNM_NET = "cpld_clk";
+TIMESPEC "TS_cpld_clk" = PERIOD "cpld_clk" 40 ns HIGH 50 %;
 NET "GMII_RX_CLK" TNM_NET = "GMII_RX_CLK";
 TIMESPEC "TS_GMII_RX_CLK" = PERIOD "GMII_RX_CLK" 8 ns HIGH 50 %;
 NET "GMII_TX_CLK" TNM_NET = "GMII_TX_CLK";
 TIMESPEC "TS_GMII_TX_CLK" = PERIOD "GMII_TX_CLK" 8 ns HIGH 50 %;
 NET "ser_rx_clk" TNM_NET = "ser_rx_clk";
 TIMESPEC "TS_ser_rx_clk" = PERIOD "ser_rx_clk" 10 ns HIGH 50 %;
-NET "u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" TNM_NET = 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT";
-TIMESPEC "TS_u2_basic_MAC_top_U_Clk_ctrl_U_1_CLK_DIV2_OUT" = PERIOD 
"u2_basic/MAC_top/U_Clk_ctrl/U_1_CLK_DIV2/OUT" 16 ns HIGH 50 %;