[Commit-gnuradio] r6579 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-10-03 01:40:14 -0600 (Wed, 03 Oct 2007)
New Revision: 6579

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
fix a timing problem on the wishbone bus.  Writes now take 1 cycle, but reads 
take 2


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-10-03 04:58:51 UTC (rev 6578)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-10-03 07:40:14 UTC (rev 6579)
@@ -185,16 +185,25 @@
                             
.i2(rd2_error_i),.i3(rd3_error_i),.o(rd_error_i[i]));
        end // block: gen_buffer
    endgenerate
-   
+
+   //----------------------------------------------------------------------
    // Wishbone Outputs
-   assign wb_dat_o = buf_doa[which_buf];
 
+   // Use the following lines if ram output and mux can be made fast enough
    //always @(posedge wb_clk_i)
-   //  if(wb_stb_i)
-   //    wb_dat_o <= buf_doa[which_buf];
-   
+   //  wb_ack_o <= wb_stb_i;
+   //assign wb_dat_o = buf_doa[which_buf];
+
+   // Use this if we can't make the RAM+MUX fast enough
+   reg [31:0] wb_dat_o_reg;
+   reg               stb_d1;
    always @(posedge wb_clk_i)
-     wb_ack_o <= wb_stb_i;
+     begin
+       wb_dat_o_reg <= buf_doa[which_buf];
+       stb_d1 <= wb_stb_i;
+       wb_ack_o <= (stb_d1 & ~wb_ack_o) | (wb_we_i & wb_stb_i);
+     end
+   assign     wb_dat_o = wb_dat_o_reg;
    
    assign wb_err_o = 1'b0;  // Unused for now
    assign wb_rty_o = 1'b0;  // Unused for now