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[Commit-gnuradio] r6560 - in gnuradio/branches/developers/zhuochen/inban
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From: |
zhuochen |
|
Subject: |
[Commit-gnuradio] r6560 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb |
|
Date: |
Fri, 28 Sep 2007 12:04:46 -0600 (MDT) |
Author: zhuochen
Date: 2007-09-28 12:04:44 -0600 (Fri, 28 Sep 2007)
New Revision: 6560
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
Most registers works, delay works.
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/cmd_reader.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -18,7 +18,9 @@
output reg [31:0] reg_data_in,
output reg [6:0] reg_addr,
output reg [1:0] reg_io_enable,
- output wire [14:0] debug
+ output wire [14:0] debug,
+ output reg stop,
+ output reg [15:0] stop_time
);
// States
@@ -74,6 +76,7 @@
reg_io_enable <= 0;
reg_data_in <= 0;
reg_addr <= 0;
+ stop <= 0;
end
else case (state)
IDLE : begin
@@ -119,6 +122,7 @@
reg_io_enable <= 0;
rx_WR <= 0;
rx_WR_done <= 1;
+ stop <= 0;
if (payload_read == payload)
begin
skip <= 1;
@@ -279,9 +283,9 @@
DELAY : begin
rdreq <= 0;
- value1 <= value1 + 32'd1;
- if (value0[15:0] == value1[15:0])
- state <= TEST;
+ stop <= 1;
+ stop_time <= value0[15:0];
+ state <= TEST;
end
default : begin
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/packet_builder.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -16,7 +16,7 @@
input have_space,
input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire
[31:0]rssi_2,
input wire [31:0]rssi_3, output wire [7:0] debugbus,
- input [NUM_CHAN:0] overrun, input [NUM_CHAN:0] underrun);
+ input [NUM_CHAN:0] underrun);
// States
@@ -39,6 +39,7 @@
`define UNDERRUN 14
`define OVERRUN 15
+ reg [NUM_CHAN:0] overrun;
reg [2:0] state;
reg [8:0] read_length;
reg [8:0] payload_len;
@@ -58,6 +59,7 @@
begin
if (reset)
begin
+ overrun <= 0;
WR <= 0;
rd_select <= 0;
chan_rdreq <= 0;
@@ -68,15 +70,24 @@
else case (state)
`IDLE: begin
chan_rdreq <= #1 0;
- if (have_space)
+ //check if the channel is full
+ if(~chan_empty[check_next])
begin
- if(~chan_empty[check_next])
- begin
+ if (have_space)
+ begin
+ //transmit if the usb buffer
have space
state <= #1 `HEADER1;
- rd_select <= #1 check_next;
- end
- check_next <= #1 (check_next ==
channels ? 4'd0 : check_next + 4'd1);
- end
+ overrun[check_next] <= 0;
+ end
+ else
+ begin
+ //wait if the usb buffer is
full and set overrun
+ state <= #1 `IDLE;
+ overrun[check_next] <= 1;
+ end
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next == channels ? 4'd0
: check_next + 4'd1);
end
`HEADER1: begin
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -1,15 +1,18 @@
module register_io
(input clk, input reset, input wire [1:0] enable, input wire [6:0]
addr,
input wire [31:0] datain, output reg [31:0] dataout, output wire
[15:0] debugbus,
+ output reg [6:0] addr_wr, output reg [31:0] data_wr, output wire
strobe_wr,
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- output wire [31:0] threshhold, output wire [31:0] rssi_wait);
+ output wire [31:0] threshhold, output wire [31:0] rssi_wait,
+ input wire [31:0] readback_0, input wire [31:0] readback_1);
reg strobe;
wire [31:0] out[7:0];
assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
assign threshhold = out[1];
assign rssi_wait = out[2];
+ assign strobe_wr = strobe;
always @(*)
if (reset | ~enable[1])
@@ -22,23 +25,45 @@
if (enable[0])
begin
//read
- if (addr == 7'd9)
- dataout <= rssi_0;
- else if (addr == 7'd10)
- dataout <= rssi_1;
- else if (addr == 7'd11)
- dataout <= rssi_2;
- else if (addr == 7'd12)
- dataout <= rssi_3;
- else
- dataout <= out[addr[2:0]];
- strobe <= 0;
- end
+ case (addr)
+ 7'd9:
+ begin
+ dataout <= rssi_0;
+ end
+ 7'd10:
+ begin
+ dataout <= rssi_1;
+ end
+ 7'd11:
+ begin
+ dataout <= rssi_2;
+ end
+ 7'd12:
+ begin
+ dataout <= rssi_3;
+ end
+ 7'd32:
+ begin
+ dataout <= readback_0;
+ end
+ 7'd33:
+ begin
+ dataout <= readback_1;
+ end
+ default:
+ begin
+ dataout <= out[addr[2:0]];
+ end
+ endcase
+ strobe <= 0;
+ end
else
begin
//write
dataout <= dataout;
strobe <= 1;
+ data_wr <= datain;
+ addr_wr <= addr;
end
end
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -34,7 +34,7 @@
//signal strength
input wire [31:0] rssi_0, input wire [31:0] rssi_1,
input wire [31:0] rssi_2, input wire [31:0] rssi_3,
- input wire [1:0] tx_overrun, input wire [1:0] tx_underrun
+ input wire [1:0] tx_underrun
);
parameter NUM_CHAN = 1;
@@ -104,7 +104,7 @@
.have_space ( have_space ),
.rssi_0(rssi_0), .rssi_1(rssi_1),
.rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug),
- .overrun(tx_overrun), .underrun(tx_underrun));
+ .underrun(tx_underrun));
// Detect overrun
always @(posedge rxclk)
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -5,7 +5,7 @@
clear_status, tx_empty, debugbus,
rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2,
- rssi_3, rssi_wait, threshhold, tx_underrun
+ rssi_3, rssi_wait, threshhold, tx_underrun, stop, stop_time
);
parameter NUM_CHAN = 2 ;
@@ -55,7 +55,10 @@
output wire [6:0] reg_addr;
output wire [1:0] reg_io_enable;
output wire [NUM_CHAN-1:0] tx_underrun;
-
+ /*stoppage*/
+ output wire stop;
+ output wire [15:0] stop_time;
+
/* To generate channel readers */
genvar i ;
@@ -215,7 +218,9 @@
.reg_data_out (reg_data_out),
.reg_addr
(reg_addr),
.reg_io_enable (reg_io_enable),
- .debug (debug)
+ .debug (debug),
+ .stop (stop),
+ .stop_time
(stop_time)
);
Modified:
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-27 23:37:55 UTC (rev 6559)
+++
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-28 18:04:44 UTC (rev 6560)
@@ -97,8 +97,6 @@
// Tri-state bus macro
bustri bustri( .data(usbdata_out),.enabledt(OE),.tridata(usbdata) );
- assign clk64 = master_clk;
-
wire [15:0] ch0tx,ch1tx,ch2tx,ch3tx; //,ch4tx,ch5tx,ch6tx,ch7tx;
wire [15:0] ch0rx,ch1rx,ch2rx,ch3rx,ch4rx,ch5rx,ch6rx,ch7rx;
@@ -129,19 +127,7 @@
assign bb_tx_q0 = ch1tx;
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
-
-wire [6:0] reg_addr;
-wire [31:0] reg_data_out;
-wire [31:0] reg_data_in;
-wire [1:0] reg_io_enable;
-wire [31:0] rssi_threshhold;
-wire [31:0] rssi_wait;
-register_io register_control
-(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
- .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
- .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
-wire [1:0] tx_overrun;
wire [1:0] tx_underrun;
`ifdef TX_IN_BAND
@@ -166,7 +152,8 @@
.reg_io_enable(reg_io_enable),
.debugbus(),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
- .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .stop(stop), .stop_time(stop_time));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
@@ -283,7 +270,7 @@
.rx_WR_enabled(rx_WR_enabled),
.debugbus(tx_debugbus),
.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3),
- .tx_overrun(tx_overrun), .tx_underrun(tx_underrun));
+ .tx_underrun(tx_underrun));
`else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
@@ -357,11 +344,45 @@
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .serial_addr(addr_db),.serial_data(data_db),.serial_strobe(strobe_db),
.readback_0({io_rx_a,io_tx_a}),.readback_1({io_rx_b,io_tx_b}),.readback_2(capabilities),.readback_3(32'hf0f0931a),
.readback_4(rssi_0),.readback_5(rssi_1),.readback_6(rssi_2),.readback_7(rssi_3)
);
+ wire [6:0] reg_addr;
+ wire [31:0] reg_data_out;
+ wire [31:0] reg_data_in;
+ wire [1:0] reg_io_enable;
+ wire [31:0] rssi_threshhold;
+ wire [31:0] rssi_wait;
+ wire [6:0] addr_wr;
+ wire [31:0] data_wr;
+ wire strobe_wr;
+ wire [6:0] addr_db;
+ wire [31:0] data_db;
+ wire strobe_db;
+ assign serial_strobe = strobe_db | strobe_wr;
+ assign serial_addr = (strobe_db)? (addr_db) : (addr_wr);
+ assign serial_data = (strobe_db)? (data_db) : (addr_db);
+
+ register_io register_control
+
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
+ .dataout(reg_data_out), .data_wr(data_wr), .addr_wr(addr_wr),
.strobe_wr(strobe_wr),
+ .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait),
+ .readback_0(interp_rate), .readback_1(decim_rate));
+
+ reg [15:0] timestop;
+ wire stop;
+ wire [15:0] stop_time;
+ assign clk64 = (timestop == 0) ? master_clk : 0;
+ always @(posedge master_clk)
+ if (timestop[15:0] != 0)
+ timestop <= timestop - 16'd1;
+ else if (stop)
+ timestop <= stop_time;
+
+
wire [15:0] reg_0,reg_1,reg_2,reg_3;
master_control master_control
( .master_clk(clk64),.usbclk(usbclk),
@@ -374,8 +395,8 @@
.rx_sample_strobe(rx_sample_strobe),.strobe_decim(strobe_decim),
.tx_empty(tx_empty),
//.debug_0(rx_a_a),.debug_1(ddc0_in_i),
- .debug_0(tx_debugbus),.debug_1(tx_debugbus),
-
.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun
== 0),rx_overrun,decim_rate}),
+ //.debug_0(tx_debugbus),.debug_1(tx_debugbus),
+
//.debug_2({rx_sample_strobe,strobe_decim,serial_strobe,serial_addr}),.debug_3({rx_dsp_reset,tx_dsp_reset,rx_bus_reset,tx_bus_reset,enable_rx,(tx_underrun
== 0),rx_overrun,decim_rate}),
.reg_0(reg_0),.reg_1(reg_1),.reg_2(reg_2),.reg_3(reg_3) );
io_pins io_pins
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zhuochen <=