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[Commit-gnuradio] r6557 - in gnuradio/branches/developers/matt/u2f: cont
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6557 - in gnuradio/branches/developers/matt/u2f: control_lib sdr_lib top/u2_basic |
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Date: |
Thu, 27 Sep 2007 13:23:06 -0600 (MDT) |
Author: matt
Date: 2007-09-27 13:23:06 -0600 (Thu, 27 Sep 2007)
New Revision: 6557
Added:
gnuradio/branches/developers/matt/u2f/control_lib/nsgpio.v
Modified:
gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
added underrun and overrun interrupts, and new style gpios
Added: gnuradio/branches/developers/matt/u2f/control_lib/nsgpio.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/nsgpio.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/nsgpio.v 2007-09-27
19:23:06 UTC (rev 6557)
@@ -0,0 +1,115 @@
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// OpenCores Simple General Purpose IO core ////
+//// ////
+//// Author: Richard Herveille ////
+//// address@hidden ////
+//// www.asics.ws ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+//// ////
+//// Copyright (C) 2002 Richard Herveille ////
+//// address@hidden ////
+//// ////
+//// This source file may be used and distributed without ////
+//// restriction provided that this copyright statement is not ////
+//// removed from the file and that any derivative work contains ////
+//// the original copyright notice and the associated disclaimer.////
+//// ////
+//// THIS SOFTWARE IS PROVIDED ``AS IS'' AND WITHOUT ANY ////
+//// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED ////
+//// TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS ////
+//// FOR A PARTICULAR PURPOSE. IN NO EVENT SHALL THE AUTHOR ////
+//// OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, ////
+//// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES ////
+//// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ////
+//// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR ////
+//// BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF ////
+//// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT ////
+//// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT ////
+//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
+//// POSSIBILITY OF SUCH DAMAGE. ////
+//// ////
+/////////////////////////////////////////////////////////////////////
+
+// Registers:
+//
+// 0x00: Control Register <io[7:0]>
+// bits 7:0 R/W Input/Output '1' = output mode
+// '0' = input mode
+// 0x01: Line Register
+// bits 7:0 R Status Current GPIO pin level
+// W Output GPIO pin output level
+//
+//
+// HOWTO:
+//
+// Use a pin as an input:
+//
+// Use a pin as an output:
+
+
+
+module nsgpio
+ (input clk_i, input rst_i,
+ input cyc_i, input stb_i, input [3:0] adr_i, input we_i, input [31:0]
dat_i,
+ output reg [31:0] dat_o, output reg ack_o,
+ input [31:0] internal_sig, input [31:0] debug, inout [31:0] gpio
+ );
+
+ reg [63:0] ctrl;
+ reg [31:0] line;
+ reg [31:0] lgpio; // LatchedGPIO pins
+
+ wire wb_acc = cyc_i & stb_i; // WISHBONE access
+ wire wb_wr = wb_acc & we_i; // WISHBONE write access
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ begin
+ ctrl <= 64'h0;
+ line <= 0;
+ end
+ else if (wb_wr)
+ case( adr_i[3:2] )
+ 2'b00 :
+ line <= dat_i;
+ 2'b01 :
+ ctrl[31:0] <= dat_i;
+ 2'b10 :
+ ctrl[63:32] <= dat_i;
+ endcase // case( adr_i[3:2] )
+
+ always @(posedge clk_i)
+ case (adr_i[3:2])
+ 2'b00 :
+ dat_o <= lgpio;
+ 2'b01 :
+ dat_o <= ctrl[31:0];
+ 2'b10 :
+ dat_o <= ctrl[63:32];
+ endcase // case(adr_i[3:2])
+
+ always @(posedge clk_i or posedge rst_i)
+ if (rst_i)
+ ack_o <= 1'b0;
+ else
+ ack_o <= wb_acc & !ack_o;
+
+ // latch GPIO input pins
+ always @(posedge clk_i)
+ lgpio <= gpio;
+
+ // assign GPIO outputs
+ integer n;
+ reg [31:0] igpio; // temporary internal signal
+
+ always @(ctrl or line)
+ for(n=0;n<32;n=n+1)
+ igpio[n] <= ctrl[2*n+1] ? (ctrl[2*n] ? debug[n] : internal_sig[n]) :
+ (ctrl[2*n] ? line[n] : 1'bz);
+
+ assign gpio = igpio;
+
+endmodule
+
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v 2007-09-27
18:50:35 UTC (rev 6556)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v 2007-09-27
19:23:06 UTC (rev 6557)
@@ -7,6 +7,7 @@
input set_stb, input [7:0] set_addr, input [31:0] set_data,
input [31:0] master_time,
+ output overrun,
// To Buffer interface
output [31:0] wr_dat_o,
@@ -21,8 +22,7 @@
input [15:0] bb_i,
input [15:0] bb_q,
output run_rx,
- input wr_req
-
+ input wr_req
);
setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr
@@ -71,7 +71,7 @@
// Inband signalling support needs to go in here...
assign write = wr_req & ~full;
- wire overrun = wr_req & full;
+ assign overrun = wr_req & full;
reg [8:0] counter;
always @(posedge clk)
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v 2007-09-27
18:50:35 UTC (rev 6556)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/tx_control.v 2007-09-27
19:23:06 UTC (rev 6557)
@@ -5,7 +5,8 @@
(input clk, input rst,
input set_stb, input [7:0] set_addr, input [31:0] set_data,
- input [31:0] master_time,
+ input [31:0] master_time,
+ output underrun,
// To Buffer interface
input [31:0] rd_dat_i,
@@ -20,7 +21,6 @@
output [15:0] bb_q,
output run_tx,
input rd_ack
-
);
// Buffer interface to internal FIFO
@@ -54,6 +54,6 @@
assign run_tx = ~empty;
assign read = rd_ack & ~empty;
- wire underrun = rd_ack & empty;
+ assign underrun = rd_ack & empty;
endmodule // tx_control
Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-09-27 18:50:35 UTC (rev 6556)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
2007-09-27 19:23:06 UTC (rev 6557)
@@ -126,7 +126,8 @@
wire [31:0] ser_debug;
wire [31:0] status, status_b0, status_b1, status_b2, status_b3,
status_b4, status_b5, status_b6, status_b7;
-
+ wire bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int,
overrun, underrun;
+
//
///////////////////////////////////////////////////////////////////////////////////////////////
// Wishbone Single Master INTERCON
parameter dw = 32; // Data bus width
@@ -196,8 +197,6 @@
wire [aw-1:0] iram_wr_adr, iram_rd_adr;
wire [dw-1:0] iram_wr_dat, iram_rd_dat;
- wire bus_error, spi_int, i2c_int, timer_int, buffer_int, proc_int;
-
assign iram_rd_ack = ram_loader_done ? iram_ack : 1'b0;
assign iram_wr_ack = ram_loader_done ? 1'b0 : iram_ack;
@@ -316,34 +315,14 @@
assign s3_rty = 1'b0;
// GPIOs -- Slave #4
- wire s4_ack_a, s4_ack_b, s4_ack_c, s4_ack_d;
- assign s4_ack = s4_ack_a | s4_ack_b | s4_ack_c | s4_ack_d;
-
- simple_gpio gpio_a(.clk_i(wb_clk),.rst_i(~wb_rst),
-
.cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[0]),.adr_i(s4_adr[2]),.we_i(s4_we),
-
.dat_i(s4_dat_o[7:0]),.dat_o(s4_dat_i[7:0]),.ack_o(s4_ack_a),
- .gpio(/* io_tx[7:0]*/) );
-
- simple_gpio gpio_b(.clk_i(wb_clk),.rst_i(~wb_rst),
-
.cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[1]),.adr_i(s4_adr[2]),.we_i(s4_we),
-
.dat_i(s4_dat_o[15:8]),.dat_o(s4_dat_i[15:8]),.ack_o(s4_ack_b),
- .gpio(/* io_tx[15:8] */) );
-
- simple_gpio gpio_c(.clk_i(wb_clk),.rst_i(~wb_rst),
-
.cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[2]),.adr_i(s4_adr[2]),.we_i(s4_we),
-
.dat_i(s4_dat_o[23:16]),.dat_o(s4_dat_i[23:16]),.ack_o(s4_ack_c),
- .gpio(/* io_rx[7:0] */) );
-
- simple_gpio gpio_d(.clk_i(wb_clk),.rst_i(~wb_rst),
-
.cyc_i(s4_cyc),.stb_i(s4_stb&s4_sel[3]),.adr_i(s4_adr[2]),.we_i(s4_we),
-
.dat_i(s4_dat_o[31:24]),.dat_o(s4_dat_i[31:24]),.ack_o(s4_ack_d),
- .gpio(/* io_rx[15:8]*/) );
-
+ nsgpio nsgpio(.clk_i(wb_clk),.rst_i(wb_rst),
+ .cyc_i(s4_cyc),.stb_i(s4_stb),.adr_i(s4_adr[3:0]),.we_i(s4_we),
+ .dat_i(s4_dat_o),.dat_o(s4_dat_i),.ack_o(s4_ack),
+ .internal_sig(),.debug(),.gpio({io_tx,io_rx}) );
assign s4_err = 1'b0;
assign s4_rty = 1'b0;
- // Buffer Pool Control #5
-
+ // Buffer Pool Status #5
wb_readback_mux buff_pool_status
(.wb_clk_i(wb_clk),
.wb_rst_i(wb_rst),
@@ -435,7 +414,7 @@
simple_pic simple_pic
(.clk_i(wb_clk),.rst_i(wb_rst),.cyc_i(s8_cyc),.stb_i(s8_stb),.adr_i(s8_adr[3:2]),
.we_i(s8_we),.dat_i(s8_dat_o[7:0]),.dat_o(s8_dat_i[7:0]),.ack_o(s8_ack),.int_o(proc_int),
- .irq({3'b000,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}) );
+
.irq({1'b0,overrun,underrun,PHY_INTn,i2c_int,spi_int,timer_int,buffer_int}) );
assign s8_dat_i[31:8] = 0;
// /////////////////////////////////////////////////////////////////////////
@@ -473,7 +452,7 @@
rx_control rx_control
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .master_time(master_time),
+ .master_time(master_time),.overrun(overrun),
.wr_dat_o(wr1_dat), .wr_write_o(wr1_write), .wr_done_o(wr1_done),
.wr_error_o(wr1_error),
.wr_ready_i(wr1_ready), .wr_full_i(wr1_full),
.bb_i(bb_i_rx), .bb_q(bb_q_rx), .run_rx(run_rx), .wr_req(wr_req) );
@@ -487,7 +466,7 @@
tx_control tx_control
(.clk(dsp_clk), .rst(dsp_rst),
.set_stb(set_stb),.set_addr(set_addr),.set_data(set_data),
- .master_time(master_time),
+ .master_time(master_time),.underrun(underrun),
.rd_dat_i(rd1_dat), .rd_sop_i(rd1_sop), .rd_eop_i(rd1_eop),
.rd_read_o(rd1_read), .rd_done_o(rd1_done), .rd_error_o(rd1_error),
.bb_i(bb_i_tx), .bb_q(bb_q_tx), .run_tx(run_tx), .rd_ack(rd_ack) );
@@ -530,9 +509,6 @@
{iram_rd_adr[7:0]},
{serdes_outs}};
- assign io_rx = ser_debug[31:16];
- assign io_tx = ser_debug[15:0];
-
assign debug = debug_wb;
assign debug_clk[0] = wb_clk;
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