[Commit-gnuradio] r6551 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-09-27 01:58:09 -0600 (Thu, 27 Sep 2007)
New Revision: 6551

Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
Log:
fixed and cleaned up logic.  


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-09-27 
07:56:25 UTC (rev 6550)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-09-27 
07:58:09 UTC (rev 6551)
@@ -34,21 +34,31 @@
    reg            xfer_active;
    reg            sop_i, eop_i;
    wire    sop_o, eop_o;
-   
+
+   reg            xfer_state;
+   localparam XFER_IDLE = 1'b0;
+   localparam XFER_GO = 1'b1;
+
    always @(posedge clk)
-     if(rst)
-       xfer_active <= 0;
-     else if(~empty & (eop_o | wr_full_i))
-       xfer_active <= 0;
-     else if(wr_ready_i)
-       xfer_active <= 1;
-   
-   assign  read = (xfer_active | ~sop_o) & ~empty;
-   
-   assign  wr_write_o = xfer_active & ~empty;
-   assign  wr_done_o = eop_o & ~empty & xfer_active;
-   assign  wr_error_o = xfer_active & wr_full_i & ~eop_o & ~empty;   // FIXME 
possible critical path
-   
+     if(rst) xfer_state <= XFER_IDLE;
+     else
+       case(xfer_state)
+        XFER_IDLE :
+          if(wr_ready_i)
+            xfer_state <= XFER_GO;
+        XFER_GO :
+          if((eop_o | wr_full_i) & wr_write_o)
+            xfer_state <= XFER_IDLE;
+        default :
+          xfer_state <= XFER_IDLE;
+       endcase // case(xfer_state)
+
+   assign     wr_write_o = (xfer_state == XFER_GO) & ~empty;
+   assign     wr_done_o = (eop_o & wr_write_o);
+   assign     wr_error_o = 0;   // FIXME add check here for eop if we have 
wr_full_i once we have IBS
+
+   assign     read = wr_write_o;   // FIXME  what if there is junk between 
packets?
+  
    // Internal FIFO, size 9 is 2K, size 10 is 4K
    longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
      (.clk(clk),.rst(rst),
@@ -71,23 +81,6 @@
          eop_i <= 0;
          counter <= 0;
        end
-     else if(write)
-       begin
-         if(sop_i)
-           sop_i <= 0;
-         if(eop_i)
-           begin
-              eop_i <= 0;
-              sop_i <= 1;
-           end
-         if(counter == 498)
-           begin
-              counter <= 0;
-              eop_i <= 1;
-           end
-         else
-           counter <= counter + 1;
-       end
        
 endmodule // rx_control