[Commit-gnuradio] r6522 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-09-24 17:23:52 -0600 (Mon, 24 Sep 2007)
New Revision: 6522

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
Log:
added more slave ports


Modified: gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v      
2007-09-24 23:23:39 UTC (rev 6521)
+++ gnuradio/branches/developers/matt/u2f/control_lib/wb_1master.v      
2007-09-24 23:23:52 UTC (rev 6522)
@@ -42,13 +42,21 @@
       parameter        s0_addr = 4'h0,                 // slave 0 address
       parameter        s1_addr_w = 4 ,                 // slave 1 address 
decode width
       parameter        s1_addr = 4'h1,                 // slave 1 address 
-      parameter        s27_addr_w = 8 ,                // slave 2 to slave 7 
address decode width
+      parameter        s215_addr_w = 8 ,               // slave 2 to slave 7 
address decode width
       parameter        s2_addr = 8'h92,                // slave 2 address
       parameter        s3_addr = 8'h93,                // slave 3 address
       parameter        s4_addr = 8'h94,                // slave 4 address
       parameter        s5_addr = 8'h95,                // slave 5 address
       parameter        s6_addr = 8'h96,                // slave 6 address
       parameter        s7_addr = 8'h97,                // slave 7 address
+      parameter        s8_addr = 8'h98,                // slave 7 address
+      parameter        s9_addr = 8'h99,                // slave 7 address
+      parameter        s10_addr = 8'h9a,               // slave 7 address
+      parameter        s11_addr = 8'h9b,               // slave 7 address
+      parameter        s12_addr = 8'h9c,               // slave 7 address
+      parameter        s13_addr = 8'h9d,               // slave 7 address
+      parameter        s14_addr = 8'h9e,               // slave 7 address
+      parameter        s15_addr = 8'h9f,               // slave 7 address
       
       parameter        dw = 32,                // Data bus Width
       parameter        aw = 32,                // Address bus Width
@@ -156,14 +164,103 @@
        output          s7_stb_o,
        input           s7_ack_i,
        input           s7_err_i,
-       input           s7_rty_i);
+       input           s7_rty_i,
+
+       input [dw-1:0]  s8_dat_i,
+       output [dw-1:0]         s8_dat_o,
+       output [aw-1:0]         s8_adr_o,
+       output [sw-1:0]         s8_sel_o,
+       output          s8_we_o,
+       output          s8_cyc_o,
+       output          s8_stb_o,
+       input           s8_ack_i,
+       input           s8_err_i,
+       input           s8_rty_i,
+       
+       input [dw-1:0]  s9_dat_i,
+       output [dw-1:0]         s9_dat_o,
+       output [aw-1:0]         s9_adr_o,
+       output [sw-1:0]         s9_sel_o,
+       output          s9_we_o,
+       output          s9_cyc_o,
+       output          s9_stb_o,
+       input           s9_ack_i,
+       input           s9_err_i,
+       input           s9_rty_i,
+       
+       input [dw-1:0]  s10_dat_i,
+       output [dw-1:0]         s10_dat_o,
+       output [aw-1:0]         s10_adr_o,
+       output [sw-1:0]         s10_sel_o,
+       output          s10_we_o,
+       output          s10_cyc_o,
+       output          s10_stb_o,
+       input           s10_ack_i,
+       input           s10_err_i,
+       input           s10_rty_i,
+       
+       input [dw-1:0]  s11_dat_i,
+       output [dw-1:0]         s11_dat_o,
+       output [aw-1:0]         s11_adr_o,
+       output [sw-1:0]         s11_sel_o,
+       output          s11_we_o,
+       output          s11_cyc_o,
+       output          s11_stb_o,
+       input           s11_ack_i,
+       input           s11_err_i,
+       input           s11_rty_i,
+       
+       input [dw-1:0]  s12_dat_i,
+       output [dw-1:0]         s12_dat_o,
+       output [aw-1:0]         s12_adr_o,
+       output [sw-1:0]         s12_sel_o,
+       output          s12_we_o,
+       output          s12_cyc_o,
+       output          s12_stb_o,
+       input           s12_ack_i,
+       input           s12_err_i,
+       input           s12_rty_i,
+       
+       input [dw-1:0]  s13_dat_i,
+       output [dw-1:0]         s13_dat_o,
+       output [aw-1:0]         s13_adr_o,
+       output [sw-1:0]         s13_sel_o,
+       output          s13_we_o,
+       output          s13_cyc_o,
+       output          s13_stb_o,
+       input           s13_ack_i,
+       input           s13_err_i,
+       input           s13_rty_i,
+       
+       input [dw-1:0]  s14_dat_i,
+       output [dw-1:0]         s14_dat_o,
+       output [aw-1:0]         s14_adr_o,
+       output [sw-1:0]         s14_sel_o,
+       output          s14_we_o,
+       output          s14_cyc_o,
+       output          s14_stb_o,
+       input           s14_ack_i,
+       input           s14_err_i,
+       input           s14_rty_i,
+       
+       input [dw-1:0]  s15_dat_i,
+       output [dw-1:0]         s15_dat_o,
+       output [aw-1:0]         s15_adr_o,
+       output [sw-1:0]         s15_sel_o,
+       output          s15_we_o,
+       output          s15_cyc_o,
+       output          s15_stb_o,
+       input           s15_ack_i,
+       input           s15_err_i,
+       input           s15_rty_i
+       );
    
    // ////////////////////////////////////////////////////////////////
    //
    // Local wires
    //
    
-   wire [7:0]          ssel_dec;
+   wire [15:0]                 ssel_dec;
    reg [dw-1:0]        i_dat_s;        // internal share bus , slave data to 
master
    
    // Master output Interface
@@ -179,14 +276,25 @@
        32  : i_dat_s <= s5_dat_i;
        64  : i_dat_s <= s6_dat_i;
        128 : i_dat_s <= s7_dat_i;
+       256 : i_dat_s <= s8_dat_i;
+       512 : i_dat_s <= s9_dat_i;
+       1024 : i_dat_s <= s10_dat_i;
+       2048 : i_dat_s <= s11_dat_i;
+       4096 : i_dat_s <= s12_dat_i;
+       8192 : i_dat_s <= s13_dat_i;
+       16384 : i_dat_s <= s14_dat_i;
+       32768 : i_dat_s <= s15_dat_i;
        default : i_dat_s <= s0_dat_i;
      endcase // case(ssel_dec)
    
    assign              {m0_ack_o, m0_err_o, m0_rty_o} 
-     = {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | 
s6_ack_i | s7_ack_i ,
-       s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | 
s6_err_i | s7_err_i ,
-       s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | 
s6_rty_i | s7_rty_i };
-   
+     =  {s0_ack_i | s1_ack_i | s2_ack_i | s3_ack_i | s4_ack_i | s5_ack_i | 
s6_ack_i | s7_ack_i |
+        s8_ack_i | s9_ack_i | s10_ack_i | s11_ack_i | s12_ack_i | s13_ack_i | 
s14_ack_i | s15_ack_i ,
+        s0_err_i | s1_err_i | s2_err_i | s3_err_i | s4_err_i | s5_err_i | 
s6_err_i | s7_err_i |
+        s8_err_i | s9_err_i | s10_err_i | s11_err_i | s12_err_i | s13_err_i | 
s14_err_i | s15_err_i ,
+        s0_rty_i | s1_rty_i | s2_rty_i | s3_rty_i | s4_rty_i | s5_rty_i | 
s6_rty_i | s7_rty_i |
+        s8_rty_i | s9_rty_i | s10_rty_i | s11_rty_i | s12_rty_i | s13_rty_i | 
s14_rty_i | s15_rty_i };
+
    // Slave output interfaces
    assign              s0_adr_o = m0_adr_i;
    assign              s0_sel_o = m0_sel_i;
@@ -244,15 +352,79 @@
    assign              s7_cyc_o = m0_cyc_i;
    assign              s7_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[7];   
    
+   assign              s8_adr_o = m0_adr_i;
+   assign              s8_sel_o = m0_sel_i;
+   assign              s8_dat_o = m0_dat_i;
+   assign              s8_we_o = m0_we_i;
+   assign              s8_cyc_o = m0_cyc_i;
+   assign              s8_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[8];   
+   
+   assign              s9_adr_o = m0_adr_i;
+   assign              s9_sel_o = m0_sel_i;
+   assign              s9_dat_o = m0_dat_i;
+   assign              s9_we_o = m0_we_i;
+   assign              s9_cyc_o = m0_cyc_i;
+   assign              s9_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[9];   
+   
+   assign              s10_adr_o = m0_adr_i;
+   assign              s10_sel_o = m0_sel_i;
+   assign              s10_dat_o = m0_dat_i;
+   assign              s10_we_o = m0_we_i;
+   assign              s10_cyc_o = m0_cyc_i;
+   assign              s10_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[10];   
+   
+   assign              s11_adr_o = m0_adr_i;
+   assign              s11_sel_o = m0_sel_i;
+   assign              s11_dat_o = m0_dat_i;
+   assign              s11_we_o = m0_we_i;
+   assign              s11_cyc_o = m0_cyc_i;
+   assign              s11_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[11];   
+   
+   assign              s12_adr_o = m0_adr_i;
+   assign              s12_sel_o = m0_sel_i;
+   assign              s12_dat_o = m0_dat_i;
+   assign              s12_we_o = m0_we_i;
+   assign              s12_cyc_o = m0_cyc_i;
+   assign              s12_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[12];   
+   
+   assign              s13_adr_o = m0_adr_i;
+   assign              s13_sel_o = m0_sel_i;
+   assign              s13_dat_o = m0_dat_i;
+   assign              s13_we_o = m0_we_i;
+   assign              s13_cyc_o = m0_cyc_i;
+   assign              s13_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[13];   
+   
+   assign              s14_adr_o = m0_adr_i;
+   assign              s14_sel_o = m0_sel_i;
+   assign              s14_dat_o = m0_dat_i;
+   assign              s14_we_o = m0_we_i;
+   assign              s14_cyc_o = m0_cyc_i;
+   assign              s14_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[14];   
+   
+   assign              s15_adr_o = m0_adr_i;
+   assign              s15_sel_o = m0_sel_i;
+   assign              s15_dat_o = m0_dat_i;
+   assign              s15_we_o = m0_we_i;
+   assign              s15_cyc_o = m0_cyc_i;
+   assign              s15_stb_o = m0_cyc_i & m0_stb_i & ssel_dec[15];   
+   
    // Address decode logic
    // WARNING -- must make sure these are mutually exclusive!
    assign              ssel_dec[0] = (m0_adr_i[aw -1 : aw - s0_addr_w ] == 
s0_addr);
    assign              ssel_dec[1] = (m0_adr_i[aw -1 : aw - s1_addr_w ] == 
s1_addr);
-   assign              ssel_dec[2] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s2_addr);
-   assign              ssel_dec[3] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s3_addr);
-   assign              ssel_dec[4] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s4_addr);
-   assign              ssel_dec[5] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s5_addr);
-   assign              ssel_dec[6] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s6_addr);
-   assign              ssel_dec[7] = (m0_adr_i[aw -1 : aw - s27_addr_w ] == 
s7_addr);
+   assign              ssel_dec[2] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s2_addr);
+   assign              ssel_dec[3] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s3_addr);
+   assign              ssel_dec[4] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s4_addr);
+   assign              ssel_dec[5] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s5_addr);
+   assign              ssel_dec[6] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s6_addr);
+   assign              ssel_dec[7] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s7_addr);
+   assign              ssel_dec[8] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s8_addr);
+   assign              ssel_dec[9] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s9_addr);
+   assign              ssel_dec[10] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s10_addr);
+   assign              ssel_dec[11] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s11_addr);
+   assign              ssel_dec[12] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s12_addr);
+   assign              ssel_dec[13] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s13_addr);
+   assign              ssel_dec[14] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s14_addr);
+   assign              ssel_dec[15] = (m0_adr_i[aw -1 : aw - s215_addr_w ] == 
s15_addr);
    
 endmodule // wb_1master