[Commit-gnuradio] r6519 - gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl

[matt]

Author: matt
Date: 2007-09-24 17:20:37 -0600 (Mon, 24 Sep 2007)
New Revision: 6519

Modified:
   gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
Log:
make it compile, properly reset


Modified: 
gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v 
2007-09-24 23:11:46 UTC (rev 6518)
+++ gnuradio/branches/developers/matt/u2f/opencores/simple_pic/rtl/simple_pic.v 
2007-09-24 23:20:37 UTC (rev 6519)
@@ -201,9 +201,9 @@
   always @(posedge clk_i or negedge rst_i)
     if (~rst_i)
       begin
-          pol   <= #1 {{is}{1'b0}};              // clear polarity register
-          edgen <= #1 {{is}{1'b0}};              // clear edge enable register
-          mask  <= #1 {{is}{1'b1}};              // mask all interrupts
+          pol   <= #1 {is{1'b0}};              // clear polarity register
+          edgen <= #1 {is{1'b0}};              // clear edge enable register
+          mask  <= #1 {is{1'b1}};              // mask all interrupts
       end
     else if(wb_wr)                               // wishbone write cycle??
       case (adr_i) // synopsys full_case parallel_case
@@ -217,7 +217,7 @@
     // pending register is a special case
     always @(posedge clk_i or negedge rst_i)
       if (~rst_i)
-          pending <= #1 {{is}{1'b0}};            // clear all pending 
interrupts
+          pending <= #1 {is{1'b0}};            // clear all pending interrupts
       else if ( wb_wr & (&adr_i) )
           pending <= #1 (pending & ~dat_i[is-1:0]) | irq_event;
       else
@@ -228,10 +228,10 @@
     reg [7:0] dat_o;
     always @(posedge clk_i)
       case (adr_i) // synopsys full_case parallel_case
-        2'b00: dat_o <= #1 { {{8-is}{1'b0}}, edgen};
-        2'b01: dat_o <= #1 { {{8-is}{1'b0}}, pol};
-        2'b10: dat_o <= #1 { {{8-is}{1'b0}}, mask};
-        2'b11: dat_o <= #1 { {{8-is}{1'b0}}, pending};
+        2'b00: dat_o <= #1 { {(8-is){1'b0}}, edgen};
+        2'b01: dat_o <= #1 { {(8-is){1'b0}}, pol};
+        2'b10: dat_o <= #1 { {(8-is){1'b0}}, mask};
+        2'b11: dat_o <= #1 { {(8-is){1'b0}}, pending};
       endcase
 
    //
@@ -244,7 +244,10 @@
   // generate CPU interrupt signal
   reg int_o;
   always @(posedge clk_i)
-    int_o <= #1 |(pending & ~mask);
+    if(rst_i)
+      int_o <= #1 0;
+    else
+      int_o <= #1 |(pending & ~mask);
 
 endmodule