[Commit-gnuradio] r6505 - gnuradio/branches/developers/matt/u2f/eth

[matt]

Author: matt
Date: 2007-09-22 17:27:44 -0600 (Sat, 22 Sep 2007)
New Revision: 6505

Modified:
   gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
Log:
greatly simplified, works, but not tested with errors yet


Modified: gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-22 
08:38:10 UTC (rev 6504)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v  2007-09-22 
23:27:44 UTC (rev 6505)
@@ -9,7 +9,7 @@
    input Rx_mac_pa,
    input Rx_mac_sop,
    input Rx_mac_eop,
-   input Rx_mac_error,
+   input Rx_mac_err,
 
    output [31:0] wr_dat_o,
    output wr_write_o,
@@ -23,63 +23,22 @@
    // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2 
bytes, 11 means 3 bytes. 
    // This goes for both Tx and Rx direction. 
 
+   // Outputs -- Rx_mac_rd, wr_write_o, wr_done_o, wr_error_o
 
-   // Might as well use a shortfifo here since they are basically free
-   wire  empty, full, sfifo_write, sfifo_read;
-   wire [34:0] sfifo_in, sfifo_out;
-   
-   shortfifo #(.WIDTH(35)) txmac_sfifo
-     (.clk(clk),.rst(rst),
-      .datain(sfifo_in),.write(sfifo_write),.full(full),
-      .dataout(sfifo_out),.read(sfifo_read),.empty(empty));
-   
-   // MAC side signals
-   //  We are allowed to do one more write after we are told the FIFO is full
-   //  This allows us to register the _wa signal and speed up timing.
-
-   reg                rx_mac_ra_d1;
+   reg          xfer_active;
    always @(posedge clk)
-     if(rst) rx_mac_ra_d1 <= 0;
-     else rx_mac_ra_d1 <= Rx_mac_ra;
-   
-   assign      Rx_mac_rd = rx_mac_ra_d1 & ~full;
-   assign      sfifo_write = Rx_mac_pa;  // We need to write even if we didn't 
ask for the data...
-   assign      sfifo_in = {Rx_mac_error,Rx_mac_sop,Rx_mac_eop,Rx_mac_data};
-   
-   // BUFFER side signals
-   reg                xfer_active, error_active;
-   wire        sop, eop, error;
-   
-   assign      sop = sfifo_out[33];
-   assign      eop = sfifo_out[32];
-   assign      error = sfifo_out[34];
-   
-   always @(posedge clk)
      if(rst)
-       begin
-         xfer_active <= 0;
-         error_active <= 0;
-       end
-     else if(eop)
-       begin
-         xfer_active <= 0;
-         error_active <=0;
-       end
-     else if(error | wr_full_i)
-       begin
-         xfer_active <= 0;
-         error_active <= 1;
-       end
-     else if(wr_ready_i & ~error_active)
+       xfer_active <= 0;
+     else if(wr_ready_i & Rx_mac_ra)
        xfer_active <= 1;
+     else if(Rx_mac_eop | Rx_mac_err)
+       xfer_active <= 0;
 
-   assign sfifo_read = (error_active | xfer_active) & ~empty;
+   assign Rx_mac_rd = xfer_active;
    
-   assign wr_dat_o = sfifo_out[31:0];
-   assign wr_write_o = xfer_active & ~empty;
-   assign wr_done_o = eop & ~empty;    // FIXME double check this
-   assign wr_error_o = error | (wr_full_i & ~eop);  // FIXME potential timing 
problem
-
-   // How do we handle wr_full_i?
+   assign wr_write_o = Rx_mac_pa;
+   assign wr_done_o = Rx_mac_eop;
+   assign wr_error_o = Rx_mac_err;
+   assign wr_dat_o = Rx_mac_data;
    
 endmodule // mac_rxfifo_int