[Commit-gnuradio] r6473 - gnuradio/branches/developers/matt/u2f/sdr_lib

[matt]

Author: matt
Date: 2007-09-18 17:26:38 -0600 (Tue, 18 Sep 2007)
New Revision: 6473

Modified:
   gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
Log:
believed to be working basic streaming rx interface


Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-09-18 
23:26:08 UTC (rev 6472)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/rx_control.v  2007-09-18 
23:26:38 UTC (rev 6473)
@@ -1,4 +1,5 @@
 
+`define DSP_CORE_RX_BASE 160
 
 module rx_control
   #(parameter FIFOSIZE = 10)
@@ -24,23 +25,28 @@
      
      );
 
+   setting_reg #(.my_addr(`DSP_CORE_RX_BASE+3)) sr
+     (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+      .in(set_data),.out(run_rx),.changed());
+
    // Buffer interface to internal FIFO
    wire    write, full, read, empty;
    reg            xfer_active;
-
+   reg            sop_i, eop_i;
+   
    always @(posedge clk)
      if(rst)
        xfer_active <= 0;
-     else if(eop_o | wr_full_i)
+     else if(~empty & (eop_o | wr_full_i))
        xfer_active <= 0;
      else if(wr_ready_i)
        xfer_active <= 1;
    
-   assign  read = xfer_active & ~empty;
+   assign  read = (xfer_active | ~sop_o) & ~empty;
    
-   assign  wr_write_o = read;
-   assign  wr_done_o = eop_o & ~empty;
-   assign  wr_error_o = 0;
+   assign  wr_write_o = xfer_active & ~empty;
+   assign  wr_done_o = eop_o & ~empty & xfer_active;
+   assign  wr_error_o = xfer_active & wr_full_i & ~eop_o & ~empty;   // FIXME 
possible critical path
    
    // Internal FIFO, size 9 is 2K, size 10 is 4K
    longfifo #(.WIDTH(34),.SIZE(FIFOSIZE)) rxfifo
@@ -52,10 +58,35 @@
    // Internal FIFO to DSP interface
    
    //     Inband signalling support needs to go in here...
-   assign  run_rx = ~full;
    assign  write = wr_req & ~full;
 
    wire    overrun = wr_req & full;
-   
+
+   reg [8:0] counter;
+   always @(posedge clk)
+     if(rst)
+       begin
+         sop_i <= 1;
+         eop_i <= 0;
+         counter <= 0;
+       end
+     else if(write)
+       begin
+         if(sop_i)
+           sop_i <= 0;
+         if(eop_i)
+           begin
+              eop_i <= 0;
+              sop_i <= 1;
+           end
+         if(counter == 498)
+           begin
+              counter <= 0;
+              eop_i <= 1;
+           end
+         else
+           counter <= counter + 1;
+       end
+       
 endmodule // rx_control