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[Commit-gnuradio] r6459 - gnuradio/branches/developers/matt/u2f/control_
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From: |
matt |
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Subject: |
[Commit-gnuradio] r6459 - gnuradio/branches/developers/matt/u2f/control_lib |
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Date: |
Mon, 17 Sep 2007 22:10:50 -0600 (MDT) |
Author: matt
Date: 2007-09-17 22:10:50 -0600 (Mon, 17 Sep 2007)
New Revision: 6459
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
Log:
seems to be working, but no flow control yet
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-09-18 04:00:14 UTC (rev 6458)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-09-18 04:10:50 UTC (rev 6459)
@@ -47,11 +47,13 @@
localparam K_ERROR = 8'b000_00000; // 0x00 K00.0
localparam IDLE = 3'd0;
- localparam FIRSTLINE = 3'd1;
- localparam PKT = 3'd2;
- localparam CRC_CHECK = 3'd3;
- localparam ERROR = 3'd4;
- localparam DONE = 3'd5;
+ localparam FIRSTLINE1 = 3'd1;
+ localparam FIRSTLINE2 = 3'd2;
+ localparam PKT1 = 3'd3;
+ localparam PKT2 = 3'd4;
+ localparam CRC_CHECK = 3'd5;
+ localparam ERROR = 3'd6;
+ localparam DONE = 3'd7;
wire [17:0] even_data;
reg [17:0] odd_data;
@@ -59,6 +61,10 @@
reg odd;
reg [31:0] line_i;
+ reg sop_i;
+ reg eop_i;
+ reg error_i;
+
reg [15:0] halfline;
reg data_valid, phase;
reg [8:0] holder;
@@ -86,107 +92,150 @@
odd_data <= {even_data[16],holder[8],even_data[7:0],holder[7:0]};
assign chosen_data = odd ? odd_data : even_data;
-
+
+/*
always @(posedge clk)
if(phase == 1)
line_i = {chosen_data[15:0], halfline};
+ */
+
+ always @(posedge clk)
+ if(rst) sop_i <= 0;
+ else if(state == FIRSTLINE1) sop_i <= 1;
+ else if(write_d) sop_i <= 0;
+ reg write_pre;
always @(posedge clk)
if(rst)
begin
state <= IDLE;
- data_valid <= 0;
- phase <= 0;
odd <= 0;
+ halfline <= 0;
+ line_i <= 0;
+ eop_i <= 0;
+ error_i <= 0;
+ write_pre <= 0;
end
else
case(state)
IDLE :
begin
- data_valid <= 0;
- phase <= 0;
+ error_i <= 0;
+ write_pre <= 0;
if(even_data == {2'b11,K_PKT_START,K_PKT_START})
begin
- state <= FIRSTLINE;
+ state <= FIRSTLINE1;
odd <= 0;
end
else if(odd_data == {2'b11,K_PKT_START,K_PKT_START})
begin
- state <= FIRSTLINE;
+ state <= FIRSTLINE1;
odd <= 1;
end
end
- FIRSTLINE, PKT :
+ FIRSTLINE1 :
+ if(chosen_data[17:16] == 0)
+ begin
+ halfline <= chosen_data[15:0];
+ state <= FIRSTLINE2;
+ end
+ else if(chosen_data == {2'b11,K_COMMA,K_COMMA})
+ ; // Flow Controlled, so wait here and do nothing
+ else
+ state <= ERROR;
+
+ FIRSTLINE2 :
+ if(chosen_data[17:16] == 0)
+ begin
+ line_i <= {chosen_data[15:0],halfline};
+ if(full) // No space to write to! Should have been avoided by
flow control
+ state <= ERROR;
+ else
+ begin
+ state <= PKT1;
+ write_pre <= 1;
+ end
+ end // if (chosen_data[17:16] == 0)
+ else if(chosen_data == {2'b11,K_COMMA,K_COMMA})
+ ; // Flow Controlled, so wait here and do nothing
+ else
+ state <= ERROR;
+
+ PKT1 :
begin
- if(full)
+ write_pre <= 0;
+ if(chosen_data[17:16] == 0)
begin
- data_valid <= 0;
- state <= ERROR;
+ halfline <= chosen_data[15:0];
+ state <= PKT2;
end
+ else if(chosen_data == {2'b11,K_COMMA,K_COMMA})
+ ; // Flow Controlled
else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END})
- if(~phase)
- begin
- state <= CRC_CHECK;
- data_valid <= 0;
- end
+ state <= CRC_CHECK;
+ else
+ state <= ERROR;
+ end // case: PKT1
+
+ PKT2 :
+ if(chosen_data[17:16] == 0)
+ begin
+ line_i <= {1'b0,1'b0,1'b0,chosen_data[15:0],halfline};
+ if(full) // No space to write to!
+ state <= ERROR;
else
begin
- state <= ERROR;
- data_valid <= 0;
+ state <= PKT1;
+ write_pre <= 1;
end
- else if(chosen_data[17:16] == 2'b00)
- begin
- data_valid <= 1;
- phase <= ~phase;
- halfline <= chosen_data[15:0];
- if(phase)
- state <= PKT;
- end
- else
- begin
- data_valid <= 0;
- state <= ERROR;
- end // else: !if(chosen_data[17:16] == 2'b00)
- end // case: FIRSTLINE, PKT
-
+ end // if (chosen_data[17:16] == 0)
+ else if(chosen_data == {2'b11,K_COMMA,K_COMMA})
+ ; // Flow Controlled
+ else
+ state <= ERROR;
+
CRC_CHECK :
- if(chosen_data[15:0] == CRC)
- state <= DONE;
+ if(chosen_data[17:0] == {2'b00,CRC})
+ begin
+ state <= DONE;
+ eop_i <= 1;
+ end
else
state <= ERROR;
ERROR :
- state <= IDLE;
+ begin
+ error_i <= 1;
+ if(~full)
+ state <= IDLE;
+ end
DONE :
- state <= IDLE;
+ begin
+ state <= IDLE;
+ eop_i <= 0;
+ end
+
endcase // case(state)
+
always @(posedge clk)
if(rst)
CRC <= 16'hFFFF;
else if(state == IDLE)
CRC <= 16'hFFFF;
- else if(data_valid)
+ else if(chosen_data[17:16] == 2'b00)
CRC <= nextCRC;
- CRC16_D16 crc_blk(halfline,CRC,nextCRC);
+ CRC16_D16 crc_blk(chosen_data[15:0],CRC,nextCRC);
- reg sop;
+ reg write_d;
always @(posedge clk)
- if(rst)
- sop <= 0;
- else if(state == FIRSTLINE)
- sop <= 1;
- else
- sop <= 0;
-
- assign write = data_valid & ~phase;
- assign sop_i = sop;
- assign eop_i = (state == DONE);
- assign error_i = (state == ERROR);
-
+ if(rst) write_d <= 0;
+ else write_d <= write_pre;
+
// Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
+ wire write = eop_i | (error_i & ~full) | (write_d & (state != CRC_CHECK));
wire [31:0] line_o;
longfifo #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
(.clk(clk),.rst(rst),
@@ -201,14 +250,14 @@
xfer_active <= 0;
else if(~empty & (eop_o | wr_full_i))
xfer_active <= 0;
- else if(wr_ready_i)
+ else if(wr_ready_i & sop_o)
xfer_active <= 1;
assign read = (xfer_active | ~sop_o) & ~empty;
assign wr_write_o = xfer_active & ~empty;
assign wr_done_o = eop_o & ~empty & xfer_active;
- assign wr_error_o = xfer_active & wr_full_i & ~eop_o & ~empty;
+ assign wr_error_o = xfer_active & ((wr_full_i & ~eop_o &
~empty)|error_o);
assign wr_dat_o = line_o;
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-09-18 04:00:14 UTC (rev 6458)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-09-18 04:10:50 UTC (rev 6459)
@@ -38,6 +38,7 @@
wire fdone_tx, ferror_tx;
reg even;
+ reg channel_error = 0;
serdes_tx serdes_tx
(.clk(clk),.rst(rst),
@@ -100,7 +101,7 @@
serdes_model serdes_model
(.ser_tx_clk(ser_tx_clk), .ser_tkmsb(ser_tkmsb), .ser_tklsb(ser_tklsb),
.ser_t(ser_t),
.ser_rx_clk(ser_rx_clk), .ser_rkmsb(ser_rkmsb), .ser_rklsb(ser_rklsb),
.ser_r(ser_r),
- .even(even));
+ .even(even), .error(channel_error) );
initial begin
wb_en_rx <= 0;
@@ -118,16 +119,44 @@
ResetBuffer(0);
ResetBuffer(1);
+ // receive a full buffer
ReceiveSERDES(0,10);
- SendSERDES(10,20);
- SendSERDES(1,511);
+ SendSERDES(0,10);
+ // Receive a partial buffer
+ SendSERDES(11,20);
+ ReceiveSERDES(11,50);
+
+ // Receive too many for buffer
+ SendSERDES(21,100);
+ ReceiveSERDES(21,30);
+
+ // Send 3 packets, then wait to receive them, so they stack up in the rx
fifo
+ SendSERDES(31,40);
+ SendSERDES(41,50);
+ SendSERDES(51,60);
+ repeat (10)
+ @(posedge clk);
+ ReceiveSERDES(31,40);
+ ReceiveSERDES(41,50);
+ repeat (1000)
+ @(posedge clk);
+ ReceiveSERDES(51,60);
+
+ // Overfill the FIFO, should get an error on 3rd packet
+ SendSERDES(1,400);
+ SendSERDES(1,400);
+
+
WaitForTX;
- WaitForRX;
+ //WaitForRX;
- repeat(100)
+
+ repeat(1000)
@(posedge clk);
- ReadRAM;
+ ReceiveSERDES(101,500);
+ ReceiveSERDES(101,500);
+ ReadRAM(80);
$finish;
end // initial begin
@@ -144,8 +173,11 @@
$dumpvars(0,serdes_tb);
end
- initial #1000000 $finish;
+ initial #10000000 $finish;
+ initial #259300 channel_error <= 1;
+ initial #259500 channel_error <= 0;
+
task FillTXRAM;
begin
wb_adr <= 0;
@@ -185,12 +217,13 @@
endtask // FillRAM
task ReadRAM;
+ input [8:0] lastline;
begin
wb_en_rx <= 1;
wb_adr <= 0;
@(posedge clk);
@(posedge clk);
- repeat(511) begin
+ repeat(lastline) begin
$display("ADDR: %h DATA %h", wb_adr, wb_dat_o_rx);
wb_adr <= wb_adr + 1;
@(posedge clk);
@@ -252,14 +285,14 @@
task WaitForTX;
begin
- while (!(fdone_tx | error_tx))
+ while (!(fdone_tx | ferror_tx))
@(posedge clk);
end
endtask // WaitForTX
task WaitForRX;
begin
- while (!(fdone_rx | error_rx))
+ while (!(fdone_rx | ferror_rx))
@(posedge clk);
end
endtask // WaitForRX
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