[Commit-gnuradio] r6456 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-09-17 16:17:51 -0600 (Mon, 17 Sep 2007)
New Revision: 6456

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
Log:
work in progress, needs sop and eop help


Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-09-17 22:17:26 UTC (rev 6455)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-09-17 22:17:51 UTC (rev 6456)
@@ -21,23 +21,24 @@
 //  K30.7 111-11110
 
 module serdes_rx
-  (input clk,
-   input rst,
-
-   // RX HW Interface
-   input ser_rx_clk,
-   input [15:0] ser_r,
-   input ser_rklsb,
-   input ser_rkmsb,
-
-   output [31:0] fifo_data_o,
-   output fifo_write_o,
-   output fifo_done_o,
-   output fifo_error_o,
-   input fifo_ready_i,
-   input fifo_full_i
-   );
-
+  #(parameter FIFOSIZE = 9)
+    (input clk,
+     input rst,
+     
+     // RX HW Interface
+     input ser_rx_clk,
+     input [15:0] ser_r,
+     input ser_rklsb,
+     input ser_rkmsb,
+     
+     output [31:0] wr_dat_o,
+     output wr_write_o,
+     output wr_done_o,
+     output wr_error_o,
+     input wr_ready_i,
+     input wr_full_i
+     );
+   
    localparam K_COMMA = 8'b101_11100;     // 0xBC K28.5
    localparam K_IDLE = 8'b001_11100;      // 0x3C K28.1
    localparam K_PKT_START = 8'b110_11100; // 0xDC K28.6
@@ -46,17 +47,18 @@
    localparam K_ERROR = 8'b000_00000;     // 0x00 K00.0
    
    localparam IDLE = 3'd0;
-   localparam PKT = 3'd1;
-   localparam CRC_CHECK = 3'd2;
-   localparam ERROR = 3'd3;
-   localparam DONE = 3'd4;
+   localparam FIRSTLINE = 3'd1;
+   localparam PKT = 3'd2;
+   localparam CRC_CHECK = 3'd3;
+   localparam ERROR = 3'd4;
+   localparam DONE = 3'd5;
    
    wire [17:0] even_data;
    reg [17:0]  odd_data;
    wire [17:0] chosen_data;
    reg                odd;
    
-   reg [31:0]  line;
+   reg [31:0]  line_i;
    reg [15:0]  halfline;
    reg                data_valid, phase;
    reg [8:0]   holder;
@@ -87,7 +89,7 @@
    
    always @(posedge clk)
      if(phase == 1)
-       line = {chosen_data[15:0], halfline};
+       line_i = {chosen_data[15:0], halfline};
    
    always @(posedge clk)
      if(rst)
@@ -105,45 +107,49 @@
              phase <= 0;
              if(even_data == {2'b11,K_PKT_START,K_PKT_START})
                begin
-                  state <= PKT;
+                  state <= FIRSTLINE;
                   odd <= 0;
                end
              else if(odd_data == {2'b11,K_PKT_START,K_PKT_START})
                begin
-                  state <= PKT;
+                  state <= FIRSTLINE;
                   odd <= 1;
                end
           end
+
+        FIRSTLINE, PKT :
+          begin
+             if(full)
+               begin
+                  data_valid <= 0;
+                  state <= ERROR;
+               end
+             else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END})
+               if(~phase)
+                 begin
+                    state <= CRC_CHECK;
+                    data_valid <= 0;
+                 end
+               else
+                 begin
+                    state <= ERROR;
+                    data_valid <= 0;
+                 end
+             else if(chosen_data[17:16] == 2'b00)
+               begin  
+                  data_valid <= 1;
+                  phase <= ~phase;
+                  halfline <= chosen_data[15:0];
+                  if(phase)
+                    state <= PKT;
+               end
+             else
+               begin
+                  data_valid <= 0;
+                  state <= ERROR;
+               end // else: !if(chosen_data[17:16] == 2'b00)
+          end // case: FIRSTLINE, PKT
         
-        PKT :
-          if(fifo_full_i | ~fifo_ready_i)
-            begin
-               data_valid <= 0;
-               state <= ERROR;
-            end
-          else if(chosen_data == {2'b11,K_PKT_END,K_PKT_END})
-            if(~phase)
-              begin
-                 state <= CRC_CHECK;
-                 data_valid <= 0;
-              end
-            else
-              begin
-                 state <= ERROR;
-                 data_valid <= 0;
-              end
-          else if(chosen_data[17:16] == 2'b00)
-            begin  
-               data_valid <= 1;
-               phase <= ~phase;
-               halfline <= chosen_data[15:0];
-            end
-          else
-            begin
-               data_valid <= 0;
-               state <= ERROR;
-            end // else: !if(chosen_data[17:16] == 2'b00)
-        
         CRC_CHECK :
           if(chosen_data[15:0] == CRC)
             state <= DONE;
@@ -166,9 +172,44 @@
 
    CRC16_D16 crc_blk(halfline,CRC,nextCRC);
 
-   assign      fifo_data_o = line;
-   assign      fifo_write_o = data_valid & ~phase;
-   assign      fifo_error_o = (state == ERROR);
-   assign      fifo_done_o = (state == DONE);
+   reg sop;
+   always @(posedge clk)
+     if(rst)
+       sop <= 0;
+     else if(state == FIRSTLINE)
+       sop <= 1;
+     else
+       sop <= 0;
+   
+   assign      write = data_valid & ~phase;
+   assign      sop_i = sop;
+   assign      eop_i = (state == DONE);
+   assign      error_i = (state == ERROR);
+   
+   // Internal FIFO, size 9 is 2K, size 10 is 4K Bytes
+   wire [31:0] line_o;
+   longfifo #(.WIDTH(35),.SIZE(FIFOSIZE)) serdes_rx_fifo
+     (.clk(clk),.rst(rst),
+      .datain({error_i,sop_i,eop_i,line_i}), .write(write), .full(full),
+      .dataout({error_o,sop_o,eop_o,line_o}), .read(read), .empty(empty) );
+   
+   // Internal FIFO to Buffer interface
+   reg                xfer_active;
+
+   always @(posedge clk)
+     if(rst)
+       xfer_active <= 0;
+     else if(~empty & (eop_o | wr_full_i))
+       xfer_active <= 0;
+     else if(wr_ready_i)
+       xfer_active <= 1;
+
+   assign      read = (xfer_active | ~sop_o) & ~empty;
+
+   assign      wr_write_o = xfer_active & ~empty;
+   assign      wr_done_o = eop_o & ~empty & xfer_active;
+   assign      wr_error_o = xfer_active & wr_full_i & ~eop_o & ~empty;
+
+   assign      wr_dat_o = line_o;
+   
 endmodule // serdes_rx
-