[Commit-gnuradio] r6414 - gnuradio/branches/developers/matt/u2f/top/u2_fpga

[matt]

Author: matt
Date: 2007-09-12 13:08:24 -0600 (Wed, 12 Sep 2007)
New Revision: 6414

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
   gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
Log:
includes ethernet files now


Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga.ise
===================================================================
(Binary files differ)

Modified: gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-09-12 19:08:10 UTC (rev 6413)
+++ gnuradio/branches/developers/matt/u2f/top/u2_fpga/u2_fpga_top.prj   
2007-09-12 19:08:24 UTC (rev 6414)
@@ -1,3 +1,4 @@
+verilog work "../../eth/rtl/verilog/TECH/duram.v"
 verilog work "../../sdr_lib/sign_extend.v"
 verilog work "../../sdr_lib/cordic_stage.v"
 verilog work "../../sdr_lib/cic_int_shifter.v"
@@ -8,6 +9,26 @@
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_decode.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_control.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_aslu.v"
+verilog work "../../eth/rtl/verilog/miim/eth_shiftreg.v"
+verilog work "../../eth/rtl/verilog/miim/eth_outputcontrol.v"
+verilog work "../../eth/rtl/verilog/miim/eth_clockgen.v"
+verilog work "../../eth/rtl/verilog/TECH/eth_clk_switch.v"
+verilog work "../../eth/rtl/verilog/TECH/eth_clk_div2.v"
+verilog work "../../eth/rtl/verilog/Reg_int.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_dpram.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_ctrl.v"
+verilog work "../../eth/rtl/verilog/RMON/RMON_addr_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/flow_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/Ramdon_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_addr_add.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/MAC_tx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_tx/CRC_gen.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_ctrl.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_add_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/MAC_rx_FF.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/CRC_chk.v"
+verilog work "../../eth/rtl/verilog/MAC_rx/Broadcast_filter.v"
 verilog work "../../control_lib/ram_2port.v"
 verilog work "../../sdr_lib/cordic.v"
 verilog work "../../sdr_lib/cic_interp.v"
@@ -16,8 +37,15 @@
 verilog work "../../opencores/spi/rtl/verilog/spi_clgen.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_byte_ctrl.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core.v"
+verilog work "../../eth/rtl/verilog/eth_miim.v"
+verilog work "../../eth/rtl/verilog/RMON.v"
+verilog work "../../eth/rtl/verilog/Phy_int.v"
+verilog work "../../eth/rtl/verilog/MAC_tx.v"
+verilog work "../../eth/rtl/verilog/MAC_rx.v"
+verilog work "../../eth/rtl/verilog/Clk_ctrl.v"
 verilog work "../../control_lib/strobe_gen.v"
 verilog work "../../control_lib/ss_rcvr.v"
+verilog work "../../control_lib/shortfifo.v"
 verilog work "../../control_lib/setting_reg.v"
 verilog work "../../control_lib/mux8.v"
 verilog work "../../control_lib/mux4.v"
@@ -31,6 +59,9 @@
 verilog work "../../opencores/simple_gpio/rtl/simple_gpio.v"
 verilog work "../../opencores/i2c/rtl/verilog/i2c_master_top.v"
 verilog work "../../opencores/aemb/rtl/verilog/aeMB_core_BE.v"
+verilog work "../../eth/rtl/verilog/MAC_top.v"
+verilog work "../../eth/mac_txfifo_int.v"
+verilog work "../../eth/mac_rxfifo_int.v"
 verilog work "../../control_lib/wb_readback_mux.v"
 verilog work "../../control_lib/wb_1master.v"
 verilog work "../../control_lib/system_control.v"