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[Commit-gnuradio] r6411 - in gnuradio/branches/developers/matt/u2f/eth:
|
From: |
matt |
|
Subject: |
[Commit-gnuradio] r6411 - in gnuradio/branches/developers/matt/u2f/eth: . bench/verilog rtl/verilog rtl/verilog/MAC_rx |
|
Date: |
Tue, 11 Sep 2007 21:25:36 -0600 (MDT) |
Author: matt
Date: 2007-09-11 21:25:35 -0600 (Tue, 11 Sep 2007)
New Revision: 6411
Added:
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/mdio.scr
Modified:
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/Phy_sim.v
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/icomp.bat
gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
Log:
code drop from Claus, 2007-09-11
Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/Phy_sim.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/Phy_sim.v
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/Phy_sim.v
2007-09-12 03:25:35 UTC (rev 6411)
@@ -106,7 +106,7 @@
assign Rx_dv = Tx_en;
assign Rxd = Txd;
- assign Rx_er = 0;
+ assign Rx_er = Tx_er;
assign Crs = Tx_en;
assign Col = 0;
Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/error.scr
2007-09-12 03:25:35 UTC (rev 6411)
@@ -21,8 +21,8 @@
// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
21 00 C8 00 01
-// Inject a single bit error in the packet!!!
-23
+// Inject a single bit error in the packet (data bit 0)
+23 00 01
// Wait (indefinitely) for missing Rx packets
22 00 00
@@ -36,8 +36,8 @@
// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
21 00 C8 00 01
-// Inject a single bit error in the packet!!!
-23
+// Inject a single bit error in the packet (data bit 7)
+23 00 80
// Wait (indefinitely) for missing Rx packets
22 00 00
@@ -48,6 +48,38 @@
// Wait (indefinitely) for missing Rx packets
22 00 00
+// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
+21 00 C8 00 01
+
+// Inject a single bit error in the packet (RxEn)
+23 01 00
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+// Transmit a 200-byte frame 1 time - and expect it to be received again!
+20 00 C8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+// Transmit a 200-byte frame 1 time - but don't expect it to be received again!
+21 00 C8 00 01
+
+// Inject a single bit error in the packet (RxEr)
+23 02 00
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+// Transmit a 200-byte frame 1 time - and expect it to be received again!
+20 00 C8 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+//---------------------------------------------------------------------------
+
// Set CPU_rd_addr to address RxCRCErrCounter
01 00 1C 00 05
@@ -72,5 +104,32 @@
// Negate CPU_rd_apply
01 00 1D 00 00
+//---------------------------------------------------------------------------
+
+// Set CPU_rd_addr to address RxTooShortTooLongCounter
+01 00 1C 00 07
+
+// Assert CPU_rd_apply
+01 00 1D 00 01
+
+// Kill a little time while waiting for CPU_rd_grant to assert...
+02 00 1E
+02 00 1E
+02 00 1E
+02 00 1E
+
+// Confirm that CPU_rd_grant is asserted
+03 00 1E 00 01 ff ff
+
+// Read & check low part of RxTooShortTooLongCounter (0x0002)
+03 00 1F 00 02 ff ff
+
+// Read & check high part of RxTooShortTooLongCounter (0x0000)
+03 00 20 00 00 ff ff
+
+// Negate CPU_rd_apply
+01 00 1D 00 00
+
+
// Halt
FF
Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/icomp.bat
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/icomp.bat
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/icomp.bat
2007-09-12 03:25:35 UTC (rev 6411)
@@ -1 +1 @@
-iverilog -I ../../rtl/verilog -c files.lst
+iverilog -I ..\..\rtl\verilog -c files.lst
Added: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/jumbo_err.scr
2007-09-12 03:25:35 UTC (rev 6411)
@@ -0,0 +1,34 @@
+// This test performs transmission & reception of several Jumbo-frame of
~2Kbytes
+// In one of the frames an error is injected to allow analysis of how the
+// MAC Rx interface reacts to errors in long packets
+
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
+// Set speed to 1000 Mbps
+01 00 22 00 04
+
+// Setup Tx and Rx MAC addresses and type field to "IP"
+// Set Tx Data at offset 0, length 14 to 123456789ABC CBA987654321 0800
+10 00 00 00 0E 12 34 56 78 9A BC CB A9 87 65 43 21 08 00
+
+// Transmit a 2049-byte frame 2 times - and expect them to be received again!
+20 08 01 00 02
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+// Transmit a 2049-byte frame 1 time - but don't expect it to be received
again!
+20 08 01 00 01
+
+// Delay 256 NOPs to time the error injection to be late in the packet
+0F 01 00
+
+// Inject a single bit error in the packet (data bit 0)
+23 00 01
+
+// Wait (indefinitely) for missing Rx packets
+22 00 00
+
+// Halt
+FF
Added: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/mdio.scr
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/mdio.scr
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/mdio.scr
2007-09-12 03:25:35 UTC (rev 6411)
@@ -0,0 +1,52 @@
+// Read from register 24 to confirm that Rx CRC check is enabled
+03 00 18 00 01 ff ff
+
+// Set speed to 1000 Mbps
+01 00 22 00 04
+
+// Set MDIO clock (MDC) divider to 4 to speed up test
+01 00 23 00 04
+03 00 23 00 04 ff ff
+
+// Check default (reset) values in new (added) MDIO registers
+//03 00 23 00 64 ff ff
+03 00 24 00 00 ff ff
+03 00 25 00 00 ff ff
+03 00 26 00 00 ff ff
+03 00 27 00 00 ff ff
+03 00 28 00 00 ff ff
+
+// Set RGAD=0x00 (all zeroes), FIAD=0x1f (all ones), check it
+// - these values allows easy recognition in the waveform
+01 00 25 00 1f
+03 00 25 00 1f ff ff
+
+// Now start the read operation by writing a 1 to the MIICOMMAND[1] - RSTAT
+01 00 24 00 02
+03 00 24 00 02 ff ff
+
+// Delay for 768 NOP
+0F 03 00
+
+// Check that the read operation has completed
+03 00 28 00 00 ff ff
+
+// Set RGAD=0x1f (all ones), FIAD=0x00 (all zeroes), check it
+// - these values allows easy recognition in the waveform
+01 00 25 1f 00
+03 00 25 1f 00 ff ff
+// Set MIITX_DATA = 0xAAAA, check it
+01 00 26 AA AA
+03 00 26 AA AA ff ff
+// Check MIISTATUS - must still be zero
+03 00 28 00 00 ff ff
+
+// Now start the write operation by writing a 1 to the MIICOMMAND[2] -
WCTRLDATA
+01 00 24 00 04
+03 00 24 00 04 ff ff
+
+// Delay for 768 NOP
+0F 03 00
+
+// Check that the write operation has completed
+03 00 28 00 00 ff ff
Modified: gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/bench/verilog/tb_top.v
2007-09-12 03:25:35 UTC (rev 6411)
@@ -178,18 +178,20 @@
.Mdc ( Mdc )
);
- reg InjectError;
+ reg [15:0] InjectError;
reg InjectErrorDone;
- reg [7:0] TxError;
- wire [7:0] TxdModified;
+ reg [15:0] TxError;
+ wire Tx_er_Modified;
+ wire Tx_en_Modified;
+ wire [7:0] Txd_Modified;
Phy_sim U_Phy_sim(
.Gtx_clk( Gtx_clk ),
.Rx_clk ( Rx_clk ),
.Tx_clk ( Tx_clk ),
- .Tx_er ( Tx_er ),
- .Tx_en ( Tx_en ),
- .Txd ( TxdModified ),
+ .Tx_er ( Tx_er_Modified ),
+ .Tx_en ( Tx_en_Modified ),
+ .Txd ( Txd_Modified ),
.Rx_er ( Rx_er ),
.Rx_dv ( Rx_dv ),
.Rxd ( Rxd ),
@@ -212,20 +214,22 @@
// Asserted after the Destination MAC address in the packet
wire TxInPayload = Tx_en & (TxTrackPreAmble > (7+6));
- assign TxdModified = Txd ^ ( TxError & {8{TxInPayload}} );
+ assign Tx_er_Modified = Tx_er ^ ( TxError[9] & TxInPayload );
+ assign Tx_en_Modified = Tx_en ^ ( TxError[8] & TxInPayload );
+ assign Txd_Modified = Txd ^ ( TxError[7:0] & {8{TxInPayload}} );
always @( posedge Reset or posedge Tx_clk )
if ( Reset )
begin
InjectError <= 0;
InjectErrorDone <= 0;
- TxError <= 8'b0;
+ TxError <= 'b0;
end
else
if ( InjectError )
begin
+ TxError <= InjectError;
InjectError <= 0;
- TxError <= 8'h01;
InjectErrorDone <= TxInPayload;
end
else if ( TxInPayload || InjectErrorDone )
@@ -235,6 +239,32 @@
end
//-------------------------------------------------------------------------
+ // Track pause on Tx interface
+
+ reg TxEnSeenOnce;
+ integer TxTrackPause;
+
+ always @( posedge Reset or posedge Tx_clk )
+ if ( Reset )
+ begin
+ TxEnSeenOnce <= 0;
+ TxTrackPause <= 0;
+ end
+ else
+ if ( Tx_en )
+ begin
+ if ( TxEnSeenOnce && (TxTrackPause >= 64) ) // 512 bits
+ $display( "IDLE period on Tx interface ended after %0d Tx clocks
(%0d bits, tick ~ %0d)",
+ TxTrackPause,
+ (Speed == 4) ? TxTrackPause*8 : TxTrackPause*4,
+ (Speed == 4) ? TxTrackPause*8/512 : TxTrackPause*4/512 );
+ TxEnSeenOnce <= 1;
+ TxTrackPause <= 0;
+ end
+ else
+ TxTrackPause <= TxTrackPause + 1;
+
+ //-------------------------------------------------------------------------
// Host access routines (register read & write)
//-------------------------------------------------------------------------
@@ -684,6 +714,17 @@
ScriptReadRegAndMatch( Addr, Data, Mask );
end
+ 8'h0f: // Delay
+ begin
+ Count = Get16bit(i);
+ $display( "Delay %0d", Count );
+ while ( Count > 0 )
+ begin
+ #10;
+ Count = Count - 1;
+ end
+ end
+
8'h10: // Setup Tx Data
begin
Addr = Get16bit(i);
@@ -756,8 +797,9 @@
8'h23: // Inject bit error in Tx packet
begin
- $display( "Injecting a single bit-error in Tx packet..." );
- InjectError = 1;
+ InjectError = Get16bit(i); // Get bit error pattern
+ $display( "Injecting a single bit-error in Tx packet:
TxEr=%0d, TxEn=%0d, TxD=0x%02h (0x%03h)",
+ InjectError[9], InjectError[8], InjectError[7:0],
InjectError );
end
8'h24: // Store internally generated PAUSE frame in Rx expect queue
@@ -871,6 +913,18 @@
//-------------------------------------------------------------------------
+ initial
+ begin
+ if ( $test$plusargs( "vcd" ) )
+ begin
+ $display( "Turning VCD data dump on" );
+ $dumpfile();
+ $dumpvars( 0 ); // Dump all signals in entire design
+ end
+ end
+
+ //-------------------------------------------------------------------------
+
reg [1023:0] ScriptFile;
initial
@@ -905,7 +959,4 @@
ExecuteScript;
end
- initial $dumpfile("tb_top.vcd");
- initial $dumpvars(0,tb_top);
-
endmodule
Modified: gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v 2007-09-11
20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_rxfifo_int.v 2007-09-12
03:25:35 UTC (rev 6411)
@@ -17,8 +17,30 @@
input wr_ready_i,
input wr_full_i);
- assign wr_dat_o = Rx_mac_data;
- assign wr_done_o = Rx_mac_eop;
+ // From Claus --
+ // The _BE fields are only valid when _eop is asserted.
+ // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2
bytes, 11 means 3 bytes.
+ // This goes for both Tx and Rx direction.
+
+ shortfifo #(.WIDTH(32)) rxmac_sfifo
+ (.clk(clk),.rst(rst),
+ .datain(Rx_mac_data),.write(Rx_mac_rd),.full(full),
+ .dataout(wr_dat_o),.read(wr_write_o),.empty(empty));
+
+ reg in_packet;
+ always @(posedge clk)
+ if(rst)
+ in_packet <= 0;
+ else if(Rx_mac_sop)
+ in_packet <= 1;
+ else if(Rx_mac_eop)
+ in_packet <= 0;
+ else if(wr_error_o)
+ in_packet <= 0;
+
+ wire write_into_sfifo = 0;
+ wire read_from_macfifo = 0;
+
endmodule // mac_rxfifo_int
Modified: gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v 2007-09-11
20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/mac_txfifo_int.v 2007-09-12
03:25:35 UTC (rev 6411)
@@ -1,25 +1,53 @@
module mac_txfifo_int
(input clk, input rst,
-
+
input Tx_mac_wa,
output Tx_mac_wr,
output [31:0] Tx_mac_data,
output [1:0] Tx_mac_BE,
output Tx_mac_sop,
output Tx_mac_eop,
-
+
input [31:0] rd_dat_i,
output rd_read_o,
output rd_done_o,
output rd_error_o,
input rd_ready_i,
input rd_empty_i);
+
+ // We are allowed to do one more write after we are told the FIFO is full
+ // This allows us to register the _wa signal and speed up timing.
+
+ reg tx_mac_wa_d1;
+ always @(posedge clk)
+ tx_mac_wa_d1 <= Tx_mac_wa;
+
+ //assign Tx_mac_data = rd_dat_i;
+ //assign Tx_mac_eop = rd_empty_i;
+
+ // From Claus --
+ // The _BE fields are only valid when _eop is asserted.
+ // 00 means all 4 bytes are valid, 01 means 1 byte (bit 31:24), 10 means 2
bytes, 11 means 3 bytes.
+ // This goes for both Tx and Rx direction.
- assign Tx_mac_data = rd_dat_i;
- assign Tx_mac_eop = rd_empty_i;
- assign Tx_mac_BE = 0;
+ assign Tx_mac_BE = 0; // Since we only deal with packets that are
multiples of 32 bits long
+
+ // Might as well use a shortfifo here since they are basically free
+ wire empty, full;
+ assign Tx_mac_wr = ~empty & tx_mac_wa_d1;
+ assign rd_read_o = ~full & rd_ready_i;
+ shortfifo #(.WIDTH(32)) txmac_sfifo
+ (.clk(clk),.rst(rst),
+ .datain(rd_dat_i),.write(rd_read_o),.full(full),
+ .dataout(Tx_mac_data),.read(Tx_mac_wr),.empty(empty));
+
+ // need to control sop and eop
+
+ assign rd_error_o = 0; // No possible error situations?
+ assign rd_done_o = 0; // Always send everything we're given?
endmodule // mac_txfifo_int
+
Modified:
gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/MAC_rx/MAC_rx_FF.v
2007-09-12 03:25:35 UTC (rev 6411)
@@ -109,16 +109,17 @@
//******************************************************************************
//internal signals
//******************************************************************************
-parameter State_byte3 =4'd0;
-parameter State_byte2 =4'd1;
-parameter State_byte1 =4'd2;
-parameter State_byte0 =4'd3;
-parameter State_be0 =4'd4;
-parameter State_be3 =4'd5;
-parameter State_be2 =4'd6;
-parameter State_be1 =4'd7;
-parameter State_err_end =4'd8;
-parameter State_idle =4'd9;
+parameter State_byte3 =4'h0;
+parameter State_byte2 =4'h1;
+parameter State_byte1 =4'h2;
+parameter State_byte0 =4'h3;
+parameter State_be0 =4'h4;
+parameter State_be3 =4'h5;
+parameter State_be2 =4'h6;
+parameter State_be1 =4'h7;
+parameter State_err =4'h8;
+parameter State_err_end =4'h9;
+parameter State_idle =4'ha;
parameter SYS_read =3'd0;
parameter SYS_pause =3'd1;
@@ -222,7 +223,7 @@
if (Fifo_data_en)
Next_state =State_byte2;
else if (Fifo_data_err)
- Next_state =State_err_end;
+ Next_state =State_err;
else if (Fifo_data_end)
Next_state =State_be1;
else
@@ -231,7 +232,7 @@
if (Fifo_data_en)
Next_state =State_byte1;
else if (Fifo_data_err)
- Next_state =State_err_end;
+ Next_state =State_err;
else if (Fifo_data_end)
Next_state =State_be2;
else
@@ -240,7 +241,7 @@
if (Fifo_data_en)
Next_state =State_byte0;
else if (Fifo_data_err)
- Next_state =State_err_end;
+ Next_state =State_err;
else if (Fifo_data_end)
Next_state =State_be3;
else
@@ -249,7 +250,7 @@
if (Fifo_data_en)
Next_state =State_byte3;
else if (Fifo_data_err)
- Next_state =State_err_end;
+ Next_state =State_err;
else if (Fifo_data_end)
Next_state =State_be0;
else
@@ -262,6 +263,8 @@
Next_state =State_idle;
State_be0:
Next_state =State_idle;
+ State_err:
+ Next_state =State_err_end;
State_err_end:
Next_state =State_idle;
default:
@@ -406,14 +409,20 @@
Din_tmp ={4'b1010,Fifo_data_byte3,Fifo_data_byte2,16'h0};
State_be3:
Din_tmp
={4'b1011,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,8'h0};
+ State_err:
+ begin
+ $display( "%0t: Current_state=State_err, writing...", $time );
+ Din_tmp ={4'b1101,32'h0};
+ end
default:
Din_tmp
={4'b0000,Fifo_data_byte3,Fifo_data_byte2,Fifo_data_byte1,Fifo_data_dl1};
endcase
always @ (*)
- if (Current_state==State_be0||Current_state==State_be1||
- Current_state==State_be2||Current_state==State_be3||
- (Current_state==State_byte0&&Fifo_data_en))
+ if ( Current_state==State_be0 || Current_state==State_be1 ||
+ Current_state==State_be2 || Current_state==State_be3 ||
+ Current_state==State_err ||
+ ( Current_state==State_byte0 && Fifo_data_en ) )
Wr_en_tmp =1;
else
Wr_en_tmp =0;
@@ -667,9 +676,10 @@
else
Dout_dl1 <=Dout;
-assign Rx_mac_data =Dout_dl1[31:0];
-assign Rx_mac_BE =Dout_dl1[33:32];
-assign Rx_mac_eop =Dout_dl1[35];
+assign Rx_mac_data = Dout_dl1[31:0];
+assign Rx_mac_BE = Dout_dl1[33:32];
+assign Rx_mac_eop = Dout_dl1[35];
+wire Rx_mac_err = Dout_dl1[34]; // CFH: TBD
//aligned to Addr_rd
always @ (posedge Clk_SYS or posedge Reset)
Modified: gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
2007-09-11 20:21:39 UTC (rev 6410)
+++ gnuradio/branches/developers/matt/u2f/eth/rtl/verilog/Reg_int.v
2007-09-12 03:25:35 UTC (rev 6411)
@@ -114,6 +114,14 @@
wire [15:0] Line_loop_en_int;
wire [15:0] Speed_int;
+ // New registers for controlling the MII interface
+ wire [15:0] MIIMODER;
+ reg [15:0] MIICOMMAND;
+ wire [15:0] MIIADDRESS;
+ wire [15:0] MIITX_DATA;
+ reg [15:0] MIIRX_DATA;
+ wire [15:0] MIISTATUS;
+
assign Tx_Hwmark = Tx_Hwmark_int;
assign Tx_Lwmark = Tx_Lwmark_int;
assign pause_frame_send_en = pause_frame_send_en_int;
@@ -150,6 +158,23 @@
assign Line_loop_en = Line_loop_en_int;
assign Speed = Speed_int;
+ // New registers for controlling the MII interface
+
+ // MIIMODER
+ assign NoPre = MIIMODER[8];
+ assign Divider = MIIMODER[7:0];
+ // MIICOMMAND
+ assign WCtrlData = MIICOMMAND[2];
+ assign RStat = MIICOMMAND[1];
+ assign ScanStat = MIICOMMAND[0];
+ // MIIADDRESS
+ assign Rgad = MIIADDRESS[12:8];
+ assign Fiad = MIIADDRESS[4:0];
+ // MIITX_DATA
+ assign CtrlData = MIITX_DATA[15:0];
+ // MIISTATUS
+ assign MIISTATUS[15:0] = { 13'b0, Nvalid, Busy, LinkFail };
+
wire Wr;
RegCPUData U_0_000( Tx_Hwmark_int , 7'd000, 16'h0009, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
@@ -188,12 +213,44 @@
RegCPUData U_0_033( Line_loop_en_int , 7'd033, 16'h0000, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
RegCPUData U_0_034( Speed_int , 7'd034, 16'h0004, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
+ // New registers for controlling the MDIO interface
+ RegCPUData U_0_035( MIIMODER , 7'd035, 16'h0064, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
+ // Reg #36 is MIICOMMAND - implemented separately below
+ RegCPUData U_0_037( MIIADDRESS , 7'd037, 16'h0000, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
+ RegCPUData U_0_038( MIITX_DATA , 7'd038, 16'h0000, RST_I,
CLK_I, Wr, ADR_I, DAT_I );
+
// Asserted in first clock of 2-cycle access, negated otherwise
wire Access = ~ACK_O & STB_I & CYC_I;
// Asserted in first clock of 2-cycle write access, negated otherwise
assign Wr = Access & WE_I;
+ // MIICOMMAND register - needs special treatment because of auto-resetting
bits
+ always @ ( posedge RST_I or posedge CLK_I )
+ if ( RST_I )
+ MIICOMMAND <= 0;
+ else
+ begin
+ if ( Wr & ( ADR_I == 7'd036 ) )
+ // Write access
+ MIICOMMAND <= DAT_I;
+ else
+ begin
+ if ( WCtrlDataStart )
+ MIICOMMAND[2] <= 0;
+ if ( RStatStart )
+ MIICOMMAND[1] <= 0;
+ end
+ end
+
+ // MIIRX_DATA register
+ always @ ( posedge RST_I or posedge CLK_I )
+ if ( RST_I )
+ MIIRX_DATA <= 0;
+ else
+ if ( UpdateMIIRX_DATAReg )
+ MIIRX_DATA <= Prsd;
+
// ACK_O is asserted in second clock of 2-cycle access, negated otherwise
always @ ( posedge RST_I or posedge CLK_I )
if ( RST_I )
@@ -244,6 +301,14 @@
7'd32: DAT_O <= CPU_rd_dout[31:16];
7'd33: DAT_O <= Line_loop_en;
7'd34: DAT_O <= Speed;
+
+ // New registers for controlling MII interface
+ 7'd35: DAT_O <= MIIMODER;
+ 7'd36: DAT_O <= MIICOMMAND;
+ 7'd37: DAT_O <= MIIADDRESS;
+ 7'd38: DAT_O <= MIITX_DATA;
+ 7'd39: DAT_O <= MIIRX_DATA;
+ 7'd40: DAT_O <= MIISTATUS;
endcase
end
@@ -261,11 +326,11 @@
input [15:0] WrData
);
-always @( posedge Reset or posedge Clk )
- if ( Reset )
- RegOut <= RegInit;
- else
- if ( Wr && ( Addr == RegAddr ) )
- RegOut <= WrData;
+ always @( posedge Reset or posedge Clk )
+ if ( Reset )
+ RegOut <= RegInit;
+ else
+ if ( Wr && ( Addr == RegAddr ) )
+ RegOut <= WrData;
endmodule
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- [Commit-gnuradio] r6411 - in gnuradio/branches/developers/matt/u2f/eth: . bench/verilog rtl/verilog rtl/verilog/MAC_rx,
matt <=