[Commit-gnuradio] r6409 - in gnuradio/branches/developers/zhuochen/inband/usrp/fpga: inband_lib toplevel/usrp_inband_usb

[zhuochen]

Author: zhuochen
Date: 2007-09-11 14:06:29 -0600 (Tue, 11 Sep 2007)
New Revision: 6409

Modified:
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
   
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
Log:
rssi deadline timer implemented


Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-09-11 19:51:39 UTC (rev 6408)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/chan_fifo_reader.v
        2007-09-11 20:06:29 UTC (rev 6409)
@@ -1,7 +1,7 @@
 module chan_fifo_reader 
   ( reset, tx_clock, tx_strobe, adc_time, samples_format,
     fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
-    underrun, tx_empty, debug, rssi, threshhold) ;
+    underrun, tx_empty, debug, rssi, threshhold, rssi_wait) ;
 
     input   wire                     reset ;
     input   wire                     tx_clock ;
@@ -18,6 +18,7 @@
     output  reg                      tx_empty ; //cause 0 to be the output
     input      wire                      [31:0] rssi;
     input      wire                      [31:0] threshhold;
+       input   wire                      [31:0] rssi_wait;
 
        output wire [14:0] debug;
        assign debug = {reader_state, trash, skip, timestamp[4:0], 
adc_time[4:0]};
@@ -53,6 +54,7 @@
     reg                              burst;
        reg                                                              trash;
        reg                                                              
rssi_flag;
+       reg                                               [31:0] time_wait;
    
     always @(posedge tx_clock)
     begin
@@ -68,6 +70,7 @@
             tx_i <= 0;
                        trash <= 0;
                        rssi_flag <= 0;
+                       time_wait <= 0;
          end
        else 
                   begin
@@ -81,6 +84,7 @@
                                 * is already available to this fifo_reader 
when pkt_waiting is on
                                 */
                    skip <=0;
+                                  time_wait <= 0;
                    if (pkt_waiting == 1)
                      begin
                         reader_state <= HEADER;
@@ -139,9 +143,18 @@
                begin
                    if (tx_strobe == 1)
                        tx_empty <= 1 ;
-                          
-                   // Let's send it
-                   if ((timestamp <= adc_time + `JITTER 
+                    
+                   time_wait <= time_wait + 32'd1;
+                                  // Outdated
+                   if ((timestamp < adc_time) ||
+                                                       (time_wait >= rssi_wait 
&& rssi_wait != 0 && rssi_flag))
+                     begin
+                                               trash <= 1;
+                        reader_state <= IDLE;
+                        skip <= 1;
+                     end  
+                   // Let's send it                                    
+                   else if ((timestamp <= adc_time + `JITTER 
                              && timestamp > adc_time)
                              || timestamp == 32'hFFFFFFFF)
                                        begin
@@ -153,16 +166,11 @@
                                                else
                                                    reader_state <= WAIT;
                                        end
+                                  else
+                                               reader_state <= WAIT;
                    // Wait a little bit more
-                   else if (timestamp > adc_time + `JITTER)
-                       reader_state <= WAIT; 
-                   // Outdated
-                   else if (timestamp < adc_time)
-                     begin
-                                               trash <= 1;
-                        reader_state <= IDLE;
-                        skip <= 1;
-                     end
+                   //else if (timestamp > adc_time + `JITTER)
+                   //    reader_state <= WAIT;
                end
                  
                // Wait for the transmit chain to be ready

Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v 
    2007-09-11 19:51:39 UTC (rev 6408)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/register_io.v 
    2007-09-11 20:06:29 UTC (rev 6409)
@@ -2,12 +2,14 @@
        (input clk, input reset, input wire [1:0] enable, input wire [6:0] 
addr, 
         input wire [31:0] datain, output reg [31:0] dataout, output wire 
[15:0] debugbus,
         input wire [31:0] rssi_0, input wire [31:0] rssi_1,
-        input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0] 
threshhold);
+        input wire [31:0] rssi_2, input wire [31:0] rssi_3, 
+        output wire [31:0] threshhold, output wire [31:0] rssi_wait);
         
        reg strobe;
        wire [31:0] out[7:0];
        assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
        assign threshhold = out[1];
+       assign rssi_wait = out[2];
        
        always @(*)
         if (reset | ~enable[1])

Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
        2007-09-11 19:51:39 UTC (rev 6408)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/inband_lib/tx_buffer_inband.v
        2007-09-11 20:06:29 UTC (rev 6409)
@@ -5,7 +5,7 @@
     clear_status, tx_empty, debugbus, 
        rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
        reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2, 
-    rssi_3, threshhold, tx_overrun, tx_underrun
+    rssi_3, rssi_wait, threshhold, tx_underrun
    );
        
     parameter NUM_CHAN  =      2 ;
@@ -32,7 +32,8 @@
     input      wire              [31:0]rssi_2;
     input      wire              [31:0]rssi_3;
     input      wire              [31:0]threshhold;
-
+       input   wire              [31:0]rssi_wait;
+       
     output  wire                have_space ;
     output  wire                tx_empty ;
     output  wire         [15:0] tx_i_0 ;
@@ -53,7 +54,6 @@
     output  wire         [31:0] reg_data_in;
     output  wire         [6:0]  reg_addr;
     output  wire         [1:0]  reg_io_enable;
-       output  wire             [NUM_CHAN-1:0] tx_overrun;
        output  wire             [NUM_CHAN-1:0] tx_underrun;
 
     /* To generate channel readers */
@@ -148,7 +148,6 @@
        
     generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
     begin : generate_channel_readers
-               assign tx_overrun[i] = ~chan_have_space[i];
                assign tx_underrun[i] = chan_underrun[i];
         channel_ram tx_data_packet_fifo 
             (      .reset               (reset),
@@ -178,7 +177,8 @@
                    .pkt_waiting         (chan_pkt_waiting[i]),
                    .tx_empty            (chan_txempty[i]),
                    .rssi                               (rssi[i]),
-                   .threshhold                 (threshhold)
+                   .threshhold                 (threshhold),
+                                  .rssi_wait                   (rssi_wait)
             );     
         
     end

Modified: 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
--- 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
   2007-09-11 19:51:39 UTC (rev 6408)
+++ 
gnuradio/branches/developers/zhuochen/inband/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
   2007-09-11 20:06:29 UTC (rev 6409)
@@ -135,11 +135,12 @@
 wire [31:0] reg_data_in;
 wire [1:0] reg_io_enable;
 wire [31:0] rssi_threshhold;
+wire [31:0] rssi_wait;
 
 register_io register_control
 
(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
  .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
- .rssi_3(rssi_3), .threshhold(rssi_threshhold));
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
 wire [1:0] tx_overrun;
 wire [1:0] tx_underrun;
 
@@ -147,8 +148,7 @@
        tx_buffer_inband tx_buffer
      ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
        .usbdata(usbdata),.WR(WR),.have_space(have_space),
-       .tx_underrun(tx_underrun), .tx_overrun(tx_overrun),
-       .channels({tx_numchan,1'b0}),
+       .tx_underrun(tx_underrun),.channels({tx_numchan,1'b0}),
        .tx_i_0(ch0tx),.tx_q_0(ch1tx),
        .tx_i_1(ch2tx),.tx_q_1(ch3tx),
        .tx_i_2(),.tx_q_2(),
@@ -166,7 +166,7 @@
           .reg_io_enable(reg_io_enable),
           .debugbus(),
           .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), 
-       .rssi_3(rssi_3), .threshhold(rssi_threshhold));
+       .rssi_3(rssi_3), .threshhold(rssi_threshhold), .rssi_wait(rssi_wait));
 `else
    tx_buffer tx_buffer
      ( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),