[Commit-gnuradio] r6363 - gnuradio/branches/developers/matt/u2f/top/u2_basic

[matt]

Author: matt
Date: 2007-09-08 00:23:55 -0600 (Sat, 08 Sep 2007)
New Revision: 6363

Modified:
   gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
Log:
added in the MAC


Modified: gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-08 06:21:24 UTC (rev 6362)
+++ gnuradio/branches/developers/matt/u2f/top/u2_basic/u2_basic.v       
2007-09-08 06:23:55 UTC (rev 6363)
@@ -26,10 +26,10 @@
    input GMII_CRS,
 
    //   GMII-TX
-   input [7:0] GMII_TXD,
-   input GMII_TX_EN,
-   input GMII_TX_ER,
-   input GMII_GTX_CLK,
+   output [7:0] GMII_TXD,
+   output GMII_TX_EN,
+   output GMII_TX_ER,
+   output GMII_GTX_CLK,
    input GMII_TX_CLK,  // 100mbps clk
 
    //   GMII-RX
@@ -39,8 +39,8 @@
    input GMII_RX_ER,
 
    //   GMII-Management
-   input MDIO,
-   input MDC,
+   inout MDIO,
+   output MDC,
    input PHY_INTn,   // open drain
    input PHY_RESETn,
    input PHY_CLK,   // possibly use on-board osc
@@ -349,10 +349,7 @@
    assign       s5_err = 1'b0;
    assign       s5_rty = 1'b0;
 
-   // Unused slave, #6
-   assign       s6_ack = s6_stb;
-   assign       s6_err = 1'b0;
-   assign       s6_rty = 1'b0;
+   // Slave, #6 Ethernet MAC, see below
    
    // Settings Bus -- Slave #7
    settings_bus settings_bus
@@ -382,6 +379,46 @@
                                      .in(set_data),.out(misc_outs),.changed());
 
    // /////////////////////////////////////////////////////////////////////////
+   // Ethernet MAC
+   
+   wire         Tx_mac_wa, Tx_mac_wr, Tx_mac_sop, Tx_mac_eop;
+   wire         Rx_mac_ra, Rx_mac_rd, Rx_mac_sop, Rx_mac_eop, Rx_mac_pa;
+   wire [31:0]          Tx_mac_data, Rx_mac_data;
+   wire [1:0]   Tx_mac_BE, Rx_mac_BE;
+   
+   MAC_top MAC_top
+     (.Clk_125M(),.Clk_user(dsp_clk),.Speed(),
+      
.RST_I(wb_rst),.CLK_I(wb_clk),.STB_I(s6_stb),.CYC_I(s6_cyc),.ADR_I(s6_adr[8:2]),
+      
.WE_I(s6_we),.DAT_I(s6_dat_o[15:0]),.DAT_O(s6_dat_i[15:0]),.ACK_O(s6_ack),
+      .Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+      
.Rx_mac_BE(Rx_mac_BE),.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),
+      .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+      .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+      
.Gtx_clk(GMII_GTX_CLK),.Tx_clk(GMII_TX_CLK),.Tx_er(GMII_TX_ER),.Tx_en(GMII_TX_EN),.Txd(GMII_TXD),
+      
.Rx_clk(GMII_RX_CLK),.Rx_er(GMII_RX_ER),.Rx_dv(GMII_RX_DV),.Rxd(GMII_RXD),
+      .Crs(GMII_CRS),.Col(GMII_COL),
+      .Mdio(MDIO),.Mdc(MDC) );
+
+   assign       s6_dat_i[31:16] = 0;
+   assign       s6_err = 1'b0;
+   assign       s6_rty = 1'b0;
+
+   mac_rxfifo_int mac_rxfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .Rx_mac_ra(Rx_mac_ra),.Rx_mac_rd(Rx_mac_rd),.Rx_mac_data(Rx_mac_data),
+      
.Rx_mac_BE(Rx_mac_BE),.Rx_mac_pa(Rx_mac_pa),.Rx_mac_sop(Rx_mac_sop),.Rx_mac_eop(Rx_mac_eop),
+      .wr_dat_o(wr2_dat),.wr_write_o(wr2_write),.wr_done_o(wr2_done),
+      .wr_error_o(wr2_error),.wr_ready_i(wr2_ready),.wr_full_i(wr2_full) );
+
+   mac_txfifo_int mac_txfifo_int
+     (.clk(dsp_clk),.rst(dsp_rst),
+      .Tx_mac_wa(Tx_mac_wa),.Tx_mac_wr(Tx_mac_wr),.Tx_mac_data(Tx_mac_data),
+      .Tx_mac_BE(Tx_mac_BE),.Tx_mac_sop(Tx_mac_sop),.Tx_mac_eop(Tx_mac_eop),
+      .rd_dat_i(rd2_dat),.rd_read_o(rd2_read),.rd_done_o(rd2_done),
+      .rd_error_o(rd2_error),.rd_ready_i(rd2_ready),.rd_empty_i(rd2_empty) );
+
+
+   // /////////////////////////////////////////////////////////////////////////
    // DSP
    reg [13:0]   adc_a_reg1, adc_b_reg1, adc_a_reg2, adc_b_reg2;
    reg                  adc_ovf_a_reg1, adc_ovf_a_reg2, adc_ovf_b_reg1, 
adc_ovf_b_reg2;