[Top][All Lists]
[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Commit-gnuradio] r6258 - in gnuradio/branches/features/inband-usb/usrp:
|
From: |
gnychis |
|
Subject: |
[Commit-gnuradio] r6258 - in gnuradio/branches/features/inband-usb/usrp: fpga/inband_lib fpga/megacells fpga/sdr_lib fpga/toplevel/usrp_inband_usb host/lib/inband |
|
Date: |
Sat, 1 Sep 2007 13:05:09 -0600 (MDT) |
Author: gnychis
Date: 2007-09-01 13:05:09 -0600 (Sat, 01 Sep 2007)
New Revision: 6258
Added:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_packer.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_2k_1clk.v
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/serial_io.v
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
gnuradio/branches/features/inband-usb/usrp/host/lib/inband/gen_test_packets.py
Log:
Merging FPGA code from a hybrid of Thibaud's final changes with Leo's changes
which is -r5752:6250 from zhuochen/burst
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/chan_fifo_reader.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -1,24 +1,26 @@
module chan_fifo_reader
( reset, tx_clock, tx_strobe, adc_time, samples_format,
fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
- underrun, tx_empty ) ;
-
- parameter MAX_PAYLOAD = 504 ;
-
+ underrun, tx_empty, debug, rssi, threshhold) ;
+
input wire reset ;
input wire tx_clock ;
- input wire tx_strobe ;
- input wire [31:0] adc_time ;
- input wire [3:0] samples_format ;
- input wire [31:0] fifodata ;
- input wire pkt_waiting ;
- output reg rdreq ;
- output reg skip ;
- output reg [15:0] tx_q ;
- output reg [15:0] tx_i ;
- output reg underrun ;
- output reg tx_empty ;
-
+ input wire tx_strobe ; //signal to output tx_i and
tx_q
+ input wire [31:0] adc_time ; //current time
+ input wire [3:0] samples_format ;// not useful at this
point
+ input wire [31:0] fifodata ; //the data input
+ input wire pkt_waiting ; //signal the next packet is
ready
+ output reg rdreq ; //actually an ack to the current
fifodata
+ output reg skip ; //finish reading current packet
+ output reg [15:0] tx_q ; //top 16 bit output of fifodata
+ output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
+ output reg underrun ;
+ output reg tx_empty ; //cause 0 to be the output
+ input wire [31:0] rssi;
+ input wire [31:0] threshhold;
+
+ output wire [14:0] debug;
+ assign debug = {reader_state, trash, skip, timestamp[4:0],
adc_time[4:0]};
// Should not be needed if adc clock rate < tx clock rate
// Used only to debug
`define JITTER 5
@@ -28,34 +30,35 @@
`define QI16 4'b0
// States
- `define IDLE 4'd0
- `define READ 4'd1
- `define HEADER 4'd2
- `define TIMESTAMP 4'd3
- `define WAIT 4'd4
- `define WAITSTROBE 4'd5
- `define SEND 4'd6
- `define DISCARD 4'd7
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter TIMESTAMP = 3'd2;
+ parameter WAIT = 3'd3;
+ parameter WAITSTROBE = 3'd4;
+ parameter SEND = 3'd5;
// Header format
- `define PAYLOAD 8:0
+ `define PAYLOAD 8:2
`define ENDOFBURST 27
- `define STARTDOFBURST 28
+ `define STARTOFBURST 28
+ `define RSSI_FLAG 15
/* State registers */
- reg [3:0] reader_state;
+ reg [2:0] reader_state;
- reg [8:0] payload_len;
- reg [8:0] read_len;
+ reg [6:0] payload_len;
+ reg [6:0] read_len;
reg [31:0] timestamp;
reg burst;
+ reg trash;
+ reg
rssi_flag;
always @(posedge tx_clock)
begin
if (reset)
begin
- reader_state <= `IDLE;
+ reader_state <= IDLE;
rdreq <= 0;
skip <= 0;
underrun <= 0;
@@ -63,15 +66,24 @@
tx_empty <= 1;
tx_q <= 0;
tx_i <= 0;
+ trash <= 0;
+ rssi_flag <= 0;
end
else
begin
case (reader_state)
- `IDLE:
+ IDLE:
begin
+ /*
+ * reset all the variables and wait for a
tx_strobe
+ * it is assumed that the ram connected to this
fifo_reader
+ * is a short hand fifo meaning that the header
to the next packet
+ * is already available to this fifo_reader
when pkt_waiting is on
+ */
+ skip <=0;
if (pkt_waiting == 1)
begin
- reader_state <= `READ;
+ reader_state <= HEADER;
rdreq <= 1;
underrun <= 0;
end
@@ -82,90 +94,100 @@
tx_empty <= 1 ;
end
- /* Just wait for the fifodata to show up */
- `READ:
- begin
- reader_state <= `HEADER;
-
- if (tx_strobe)
- tx_empty <= 1 ;
- end
-
/* Process header */
- `HEADER:
+ HEADER:
begin
- reader_state <= `TIMESTAMP;
if (tx_strobe == 1)
tx_empty <= 1 ;
+ rssi_flag <= fifodata[`RSSI_FLAG]&fifodata[`STARTOFBURST];
//Check Start/End burst flag
- if (fifodata[`STARTDOFBURST] == 1
+ if (fifodata[`STARTOFBURST] == 1
&& fifodata[`ENDOFBURST] == 1)
burst <= 0;
- else if (fifodata[`STARTDOFBURST] == 1)
+ else if (fifodata[`STARTOFBURST] == 1)
burst <= 1;
else if (fifodata[`ENDOFBURST] == 1)
burst <= 0;
-
- payload_len <= fifodata[`PAYLOAD] ;
- read_len <= 0;
-
- rdreq <= 0;
+
+ if (trash == 1 &&
fifodata[`STARTOFBURST] == 0)
+ begin
+ skip <= 1;
+ reader_state <= IDLE;
+ rdreq <= 0;
+ end
+ else
+ begin
+ payload_len <= fifodata[`PAYLOAD] ;
+ read_len <= 0;
+ rdreq <= 1;
+ reader_state <= TIMESTAMP;
+ end
end
- `TIMESTAMP:
+ TIMESTAMP:
begin
timestamp <= fifodata;
- reader_state <= `WAIT;
+ reader_state <= WAIT;
if (tx_strobe == 1)
tx_empty <= 1 ;
+ rdreq <= 0;
end
// Decide if we wait, send or discard samples
- `WAIT:
+ WAIT:
begin
if (tx_strobe == 1)
tx_empty <= 1 ;
// Let's send it
- if ((timestamp < adc_time + `JITTER
+ if ((timestamp <= adc_time + `JITTER
&& timestamp > adc_time)
|| timestamp == 32'hFFFFFFFF)
- reader_state <= `WAITSTROBE;
+ begin
+ if (rssi <= threshhold ||
rssi_flag == 0)
+ begin
+ trash <= 0;
+ reader_state <= WAITSTROBE;
+ end
+ else
+ reader_state <= WAIT;
+ end
// Wait a little bit more
else if (timestamp > adc_time + `JITTER)
- reader_state <= `WAIT;
+ reader_state <= WAIT;
// Outdated
else if (timestamp < adc_time)
begin
- reader_state <= `DISCARD;
+ trash <= 1;
+ reader_state <= IDLE;
skip <= 1;
end
end
// Wait for the transmit chain to be ready
- `WAITSTROBE:
+ WAITSTROBE:
begin
// If end of payload...
if (read_len == payload_len)
begin
- reader_state <= `DISCARD;
- skip <= (payload_len < MAX_PAYLOAD);
+ reader_state <= IDLE;
+ skip <= 1;
if (tx_strobe == 1)
tx_empty <= 1 ;
end
else if (tx_strobe == 1)
begin
- reader_state <= `SEND;
+ reader_state <= SEND;
rdreq <= 1;
end
end
// Send the samples to the tx_chain
- `SEND:
+ SEND:
begin
- reader_state <= `WAITSTROBE;
- read_len <= read_len + 9'd4;
+ reader_state <= WAITSTROBE;
+ read_len <= read_len + 7'd1;
tx_empty <= 0;
rdreq <= 0;
@@ -184,19 +206,11 @@
end
endcase
end
-
- `DISCARD:
- begin
- skip <= 0;
- reader_state <= `IDLE;
- if (tx_strobe == 1)
- tx_empty <= 1 ;
- end
default:
begin
- $display ("Error unknown state");
- reader_state <= `IDLE;
+ //error handling
+ reader_state <= IDLE;
end
endcase
end
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
(from rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/channel_demux.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_demux.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,78 @@
+module channel_demux
+ #(parameter NUM_CHAN = 2, parameter CHAN_WIDTH = 2) ( //usb Side
+ input [31:0]usbdata_final,
+ input WR_final,
+
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [CHAN_WIDTH:0] WR_channel,
+ output reg [31:0] ram_data,
+ output reg [CHAN_WIDTH:0] WR_done_channel );
+/* Parse header and forward to ram */
+ reg [2:0]reader_state;
+ reg [4:0]channel ;
+ reg [6:0]read_length ;
+
+ // States
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter WAIT = 3'd2;
+ parameter FORWARD = 3'd3;
+
+ `define CHANNEL 20:16
+ `define PKT_SIZE 127
+ wire [4:0] true_channel;
+ assign true_channel = (usbdata_final[`CHANNEL] == 5'h1f) ?
+ NUM_CHAN :
(usbdata_final[`CHANNEL]);
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ begin
+ reader_state <= IDLE;
+ WR_channel <= 0;
+ WR_done_channel <= 0;
+ end
+ else
+ case (reader_state)
+ IDLE: begin
+ if (WR_final)
+ reader_state <= HEADER;
+ end
+
+ // Store channel and forware header
+ HEADER: begin
+ channel <= true_channel;
+ WR_channel[true_channel] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= 7'd0 ;
+
+ reader_state <= WAIT;
+ end
+
+ WAIT: begin
+ WR_channel[channel] <= 0;
+
+ if (read_length == `PKT_SIZE)
+ reader_state <= IDLE;
+ else if (WR_final)
+ reader_state <= FORWARD;
+ end
+
+ FORWARD: begin
+ WR_channel[channel] <= 1;
+ ram_data <= usbdata_final;
+ read_length <= read_length + 7'd1;
+
+ reader_state <= WAIT;
+ end
+
+ default:
+ begin
+ //error handling
+ reader_state <= IDLE;
+ end
+ endcase
+ end
+endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/channel_ram.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -31,6 +31,8 @@
wire wr_done_int;
wire rd_done_int;
+ wire [6:0] rd_addr_final;
+ wire [1:0] which_ram_rd_final;
// USB side
always @(posedge txclk)
@@ -61,21 +63,24 @@
else if (wr_done_int)
which_ram_wr <= which_ram_wr + 2'd1;
- assign have_space = (nb_packets < 3);
+ assign have_space = (nb_packets < 3'd3);
// Reader side
- always @(posedge txclk) dataout0 <= ram0[rd_addr];
- always @(posedge txclk) dataout1 <= ram1[rd_addr];
- always @(posedge txclk) dataout2 <= ram2[rd_addr];
- always @(posedge txclk) dataout3 <= ram3[rd_addr];
-
- assign dataout = (which_ram_rd[1]) ?
- (which_ram_rd[0] ? dataout3 :
dataout2) :
- (which_ram_rd[0] ? dataout1 :
dataout0);
+ // short hand fifo
+ // rd_addr_final is what rd_addr is going to be next clock cycle
+ // which_ram_rd_final is what which_ram_rd is going to be next clock
cycle
+ always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
+ always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
+ always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
+ always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
+
+ assign dataout = (which_ram_rd_final[1]) ?
+ (which_ram_rd_final[0] ?
dataout3 : dataout2) :
+ (which_ram_rd_final[0] ?
dataout1 : dataout0);
- reg next_packet;
- assign rd_done_int = ((RD && (rd_addr == 7'd127)) || RD_done);
-
+ //RD_done is the only way to signal the end of one packet
+ assign rd_done_int = RD_done;
+
always @(posedge txclk)
if (reset)
rd_addr <= 0;
@@ -83,21 +88,20 @@
rd_addr <= 0;
else if (RD) rd_addr <= rd_addr + 7'd1;
+ assign rd_addr_final = (reset|RD_done) ? (6'd0) :
+ ((RD)?(rd_addr+7'd1):rd_addr);
always @(posedge txclk)
if (reset)
- begin
which_ram_rd <= 0;
- next_packet <= 0;
- end
- else if (next_packet)
- begin
+ else if (rd_done_int)
which_ram_rd <= which_ram_rd + 2'd1;
- next_packet <= 0;
- end
- else if (rd_done_int)
- next_packet <= 1;
-
- assign packet_waiting = (nb_packets > 0);
+
+ assign which_ram_rd_final = (reset) ? (2'd0):
+ ((rd_done_int) ? (which_ram_rd + 2'd1) :
which_ram_rd);
+
+ //packet_waiting is set to zero if rd_done_int is high
+ //because there is no guarantee that nb_packets will be pos.
+ assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
always @(posedge txclk)
if (reset)
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
(from rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/cmd_reader.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/cmd_reader.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,292 @@
+module cmd_reader(
+ //System
+ input reset,
+ input txclk,
+ input [31:0] adc_time,
+ //FX2 Side
+ output reg skip,
+ output reg rdreq,
+ input [31:0] fifodata,
+ input pkt_waiting,
+ //Rx side
+ input rx_WR_enabled,
+ output reg [15:0] rx_databus,
+ output reg rx_WR,
+ output reg rx_WR_done,
+ //register io
+ input wire [31:0] reg_data_out,
+ output reg [31:0] reg_data_in,
+ output reg [6:0] reg_addr,
+ output reg [1:0] reg_io_enable,
+ output wire [14:0] debug
+ );
+
+ // States
+ parameter IDLE = 4'd0;
+ parameter HEADER = 4'd1;
+ parameter TIMESTAMP = 4'd2;
+ parameter WAIT = 4'd3;
+ parameter TEST = 4'd4;
+ parameter SEND = 4'd5;
+ parameter PING = 4'd6;
+ parameter WRITE_REG = 4'd7;
+ parameter WRITE_REG_MASKED = 4'd8;
+ parameter READ_REG = 4'd9;
+ parameter DELAY = 4'd14;
+
+ `define OP_PING_FIXED 8'd0
+ `define OP_PING_FIXED_REPLY 8'd1
+ `define OP_WRITE_REG 8'd2
+ `define OP_WRITE_REG_MASKED 8'd3
+ `define OP_READ_REG 8'd4
+ `define OP_READ_REG_REPLY 8'd5
+ `define OP_DELAY 8'd12
+
+ reg [6:0] payload;
+ reg [6:0] payload_read;
+ reg [3:0] state;
+ reg [15:0] high;
+ reg [15:0] low;
+ reg pending;
+ reg [31:0] value0;
+ reg [31:0] value1;
+ reg [31:0] value2;
+ reg [1:0] lines_in;
+ reg [1:0] lines_out;
+ reg [1:0] lines_out_total;
+
+ `define JITTER 5
+ `define OP_CODE 31:24
+ `define PAYLOAD 8:2
+
+ wire [7:0] ops;
+ assign ops = value0[`OP_CODE];
+ assign debug = {state[3:0], lines_out[1:0], pending, rx_WR,
rx_WR_enabled, value0[2:0], ops[2:0]};
+
+ always @(posedge txclk)
+ if (reset)
+ begin
+ pending <= 0;
+ state <= IDLE;
+ skip <= 0;
+ rdreq <= 0;
+ rx_WR <= 0;
+ reg_io_enable <= 0;
+ reg_data_in <= 0;
+ reg_addr <= 0;
+ end
+ else case (state)
+ IDLE : begin
+ payload_read <= 0;
+ skip <= 0;
+ lines_in <= 0;
+ if (pkt_waiting)
+ begin
+ state <= HEADER;
+ rdreq <= 1;
+ end
+ end
+
+ HEADER : begin
+ payload <= fifodata[`PAYLOAD];
+ state <= TIMESTAMP;
+ end
+
+ TIMESTAMP : begin
+ value0 <= fifodata;
+ state <= WAIT;
+ rdreq <= 0;
+ end
+
+ WAIT : begin
+ // Let's send it
+ if ((value0 <= adc_time + `JITTER
+ && value0 > adc_time)
+ || value0 == 32'hFFFFFFFF)
+ state <= TEST;
+ // Wait a little bit more
+ else if (value0 > adc_time + `JITTER)
+ state <= WAIT;
+ // Outdated
+ else if (value0 < adc_time)
+ begin
+ state <= IDLE;
+ skip <= 1;
+ end
+ end
+
+ TEST : begin
+ reg_io_enable <= 0;
+ rx_WR <= 0;
+ rx_WR_done <= 1;
+ if (payload_read == payload)
+ begin
+ skip <= 1;
+ state <= IDLE;
+ rdreq <= 0;
+ end
+ else
+ begin
+ value0 <= fifodata;
+ lines_in <= 2'd1;
+ rdreq <= 1;
+ payload_read <= payload_read +
7'd1;
+ lines_out <= 0;
+ case (fifodata[`OP_CODE])
+ `OP_PING_FIXED: begin
+ state <= PING;
+ end
+ `OP_WRITE_REG: begin
+ state <=
WRITE_REG;
+ pending <= 1;
+ end
+ `OP_WRITE_REG_MASKED:
begin
+ state <=
WRITE_REG_MASKED;
+ pending <= 1;
+ end
+ `OP_READ_REG: begin
+ state <=
READ_REG;
+ end
+ `OP_DELAY: begin
+ state <= DELAY;
+ end
+ default: begin
+ //error, skip this
packet
+ skip <= 1;
+ state <= IDLE;
+ end
+ endcase
+ end
+ end
+
+ SEND: begin
+ rdreq <= 0;
+ rx_WR_done <= 0;
+ if (pending)
+ begin
+ rx_WR <= 1;
+ rx_databus <= high;
+ pending <= 0;
+ if (lines_out ==
lines_out_total)
+ state <= TEST;
+ else case (ops)
+ `OP_READ_REG: begin
+ state <=
READ_REG;
+ end
+ default: begin
+ state <= TEST;
+ end
+ endcase
+ end
+ else
+ begin
+ if (rx_WR_enabled)
+ begin
+ rx_WR <= 1;
+ rx_databus <= low;
+ pending <= 1;
+ lines_out <= lines_out
+ 2'd1;
+ end
+ else
+ rx_WR <= 0;
+ end
+ end
+
+ PING: begin
+ rx_WR <= 0;
+ rdreq <= 0;
+ rx_WR_done <= 0;
+ lines_out_total <= 2'd1;
+ pending <= 0;
+ state <= SEND;
+ high <= {`OP_PING_FIXED_REPLY, 8'd2};
+ low <= value0[15:0];
+ end
+
+ READ_REG: begin
+ rx_WR <= 0;
+ rx_WR_done <= 0;
+ rdreq <= 0;
+ lines_out_total <= 2'd2;
+ pending <= 0;
+ state <= SEND;
+ if (lines_out == 0)
+ begin
+ high <= {`OP_READ_REG_REPLY,
8'd6};
+ low <= value0[15:0];
+ reg_io_enable <= 2'd3;
+ reg_addr <= value0[6:0];
+ end
+ else
+ begin
+ high <= reg_data_out[31:16];
+ low <= reg_data_out[15:0];
+ end
+ end
+
+ WRITE_REG: begin
+ rx_WR <= 0;
+ if (pending)
+ pending <= 0;
+ else
+ begin
+ if (lines_in == 2'd1)
+ begin
+ payload_read <=
payload_read + 7'd1;
+ lines_in <= lines_in +
2'd1;
+ value1 <= fifodata;
+ rdreq <= 0;
+ end
+ else
+ begin
+ reg_io_enable <= 2'd2;
+ reg_data_in <= value1;
+ reg_addr <= value0[6:0];
+ state <= TEST;
+ end
+ end
+ end
+
+ WRITE_REG_MASKED: begin
+ rx_WR <= 0;
+ if (pending)
+ pending <= 0;
+ else
+ begin
+ if (lines_in == 2'd1)
+ begin
+ rdreq <= 1;
+ payload_read <=
payload_read + 7'd1;
+ lines_in <= lines_in +
2'd1;
+ value1 <= fifodata;
+ end
+ else if (lines_in == 2'd2)
+ begin
+ rdreq <= 0;
+ payload_read <=
payload_read + 7'd1;
+ lines_in <= lines_in +
2'd1;
+ value2 <= fifodata;
+ end
+ else
+ begin
+ reg_io_enable <= 2'd2;
+ reg_data_in <= (value1
& value2);
+ reg_addr <= value0[6:0];
+ state <= TEST;
+ end
+ end
+ end
+
+ DELAY : begin
+ rdreq <= 0;
+ value1 <= value1 + 32'd1;
+ if (value0[15:0] == value1[15:0])
+ state <= TEST;
+ end
+
+ default : begin
+ //error state handling
+ state <= IDLE;
+ end
+ endcase
+endmodule
\ No newline at end of file
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
(from rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/packet_builder.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/packet_builder.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,132 @@
+module packet_builder #(parameter NUM_CHAN = 1)(
+ // System
+ input rxclk,
+ input reset,
+ input [31:0] adctime,
+ input [3:0] channels,
+ // ADC side
+ input [15:0]chan_fifodata,
+ input [NUM_CHAN:0]chan_empty,
+ input [9:0]chan_usedw,
+ output reg [3:0]rd_select,
+ output reg chan_rdreq,
+ // FX2 side
+ output reg WR,
+ output reg [15:0]fifodata,
+ input have_space,
+ input wire [31:0]rssi_0, input wire [31:0]rssi_1, input wire
[31:0]rssi_2,
+ input wire [31:0]rssi_3, output wire [7:0] debugbus);
+
+
+ // States
+ `define IDLE 3'd0
+ `define HEADER1 3'd1
+ `define HEADER2 3'd2
+ `define TIMESTAMP 3'd3
+ `define FORWARD 3'd4
+
+ `define MAXPAYLOAD 504
+
+ `define PAYLOAD_LEN 8:0
+ `define TAG 12:9
+ `define MBZ 15:13
+
+ `define CHAN 4:0
+ `define RSSI 10:5
+ `define BURST 12:11
+ `define DROPPED 13
+ `define UNDERRUN 14
+ `define OVERRUN 15
+
+ reg [2:0] state;
+ reg [8:0] read_length;
+ reg [8:0] payload_len;
+ reg tstamp_complete;
+ reg [3:0] check_next;
+ wire [8:0] chan_used;
+ wire [31:0] true_rssi;
+
+ assign debugbus = {state, chan_empty[0], chan_empty[1], check_next[0],
+ have_space, rd_select[0]};
+ assign chan_used = chan_usedw[8:0];
+ assign true_rssi = (rd_select[1]) ? ((rd_select[0]) ? rssi_3:rssi_2) :
+ ((rd_select[0]) ?
rssi_1:rssi_0);
+ always @(posedge rxclk)
+ begin
+ if (reset)
+ begin
+ WR <= 0;
+ rd_select <= 0;
+ chan_rdreq <= 0;
+ tstamp_complete <= 0;
+ check_next <= 0;
+ state <= `IDLE;
+ end
+ else case (state)
+ `IDLE: begin
+ if (have_space)
+ begin
+ if(~chan_empty[check_next])
+ begin
+ state <= #1 `HEADER1;
+ rd_select <= #1 check_next;
+ end
+ check_next <= #1 (check_next ==
channels ? 4'd0 : check_next + 4'd1);
+ end
+ end
+
+ `HEADER1: begin
+ fifodata[`PAYLOAD_LEN] <= #1 (chan_used > 9'd252
+ ? 9'd252 : chan_used << 1);
+ payload_len <= #1 (chan_used > 9'd252
+ ? 9'd252 : chan_used << 1);
+ fifodata[`TAG] <= #1 0;
+ fifodata[`MBZ] <= #1 0;
+ WR <= #1 1;
+
+ state <= #1 `HEADER2;
+ read_length <= #1 0;
+ end
+
+ `HEADER2: begin
+ fifodata[`CHAN] <= #1 (check_next == 4'd0 ? 5'h1f : {1'd0,
check_next - 4'd1});
+ fifodata[`RSSI] <= #1 true_rssi[5:0];
+ fifodata[`BURST] <= #1 0;
+ fifodata[`DROPPED] <= #1 0;
+ fifodata[`UNDERRUN] <= #1 0;
+ fifodata[`OVERRUN] <= #1 0;
+
+ state <= #1 `TIMESTAMP;
+ end
+
+ `TIMESTAMP: begin
+ fifodata <= #1 (tstamp_complete ? adctime[31:16] :
adctime[15:0]);
+ tstamp_complete <= #1 ~tstamp_complete;
+
+ if (~tstamp_complete)
+ chan_rdreq <= #1 1;
+
+ state <= #1 (tstamp_complete ? `FORWARD : `TIMESTAMP);
+ end
+
+ `FORWARD: begin
+ read_length <= #1 read_length + 9'd2;
+ fifodata <= #1 (read_length >= payload_len ? 16'hDEAD :
chan_fifodata);
+
+ if (read_length >= `MAXPAYLOAD)
+ begin
+ WR <= #1 0;
+ state <= #1 `IDLE;
+ end
+ else if (read_length == payload_len - 4)
+ chan_rdreq <= #1 0;
+ end
+
+ default: begin
+ //handling error state
+ state <= `IDLE;
+ end
+ endcase
+ end
+endmodule
+
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v (from
rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/register_io.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/register_io.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,60 @@
+module register_io
+ (input clk, input reset, input wire [1:0] enable, input wire [6:0]
addr,
+ input wire [31:0] datain, output reg [31:0] dataout, output wire
[15:0] debugbus,
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3, output wire [31:0]
threshhold);
+
+ reg strobe;
+ wire [31:0] out[7:0];
+ assign debugbus = {clk, enable, addr[2:0], datain[4:0], dataout[4:0]};
+ assign threshhold = out[1];
+
+ always @(*)
+ if (reset | ~enable[1])
+ begin
+ strobe <= 0;
+ dataout <= 0;
+ end
+ else
+ begin
+ if (enable[0])
+ begin
+ //read
+ if (addr == 7'd9)
+ dataout <= rssi_0;
+ else if (addr == 7'd10)
+ dataout <= rssi_1;
+ else if (addr == 7'd11)
+ dataout <= rssi_2;
+ else if (addr == 7'd12)
+ dataout <= rssi_3;
+ else
+ dataout <= out[addr[2:0]];
+ strobe <= 0;
+ end
+ else
+ begin
+ //write
+ dataout <= dataout;
+ strobe <= 1;
+ end
+ end
+
+ //register declarations
+ setting_reg #(0) setting_reg0(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[0]));
+ setting_reg #(1) setting_reg1(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[1]));
+ setting_reg #(2) setting_reg2(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[2]));
+ setting_reg #(3) setting_reg3(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[3]));
+ setting_reg #(4) setting_reg4(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[4]));
+ setting_reg #(5) setting_reg5(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[5]));
+ setting_reg #(6) setting_reg6(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[6]));
+ setting_reg #(7) setting_reg7(.clock(clk),.reset(reset),
+ .strobe(strobe),.addr(addr),.in(datain),.out(out[7]));
+endmodule
\ No newline at end of file
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
(from rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/rx_buffer_inband.v)
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
(rev 0)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/rx_buffer_inband.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,176 @@
+//`include "../../firmware/include/fpga_regs_common.v"
+//`include "../../firmware/include/fpga_regs_standard.v"
+
+module rx_buffer_inband
+ ( input usbclk,
+ input bus_reset,
+ input reset, // DSP side reset (used here), do not reset registers
+ input reset_regs, //Only reset registers
+ output [15:0] usbdata,
+ input RD,
+ output wire have_pkt_rdy,
+ output reg rx_overrun,
+ input wire [3:0] channels,
+ input wire [15:0] ch_0,
+ input wire [15:0] ch_1,
+ input wire [15:0] ch_2,
+ input wire [15:0] ch_3,
+ input wire [15:0] ch_4,
+ input wire [15:0] ch_5,
+ input wire [15:0] ch_6,
+ input wire [15:0] ch_7,
+ input rxclk,
+ input rxstrobe,
+ input clear_status,
+ input [6:0] serial_addr,
+ input [31:0] serial_data,
+ input serial_strobe,
+ output wire [15:0] debugbus,
+
+ //Connection with tx_inband
+ input rx_WR,
+ input [15:0] rx_databus,
+ input rx_WR_done,
+ output reg rx_WR_enabled,
+ //signal strength
+ input wire [31:0] rssi_0, input wire [31:0] rssi_1,
+ input wire [31:0] rssi_2, input wire [31:0] rssi_3
+ );
+
+ parameter NUM_CHAN = 1;
+ genvar i ;
+
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ // Time counter
+ reg [31:0] adctime;
+ always @(posedge rxclk)
+ if (reset)
+ adctime <= 0;
+ else if (rxstrobe)
+ adctime <= adctime + 1;
+
+ // USB side fifo
+ wire [11:0] rdusedw;
+ wire [11:0] wrusedw;
+ wire [15:0] fifodata;
+ wire WR;
+ wire have_space;
+
+ fifo_4k rx_usb_fifo (
+ .aclr ( reset ),
+ .data ( fifodata ),
+ .rdclk ( ~usbclk ),
+ .rdreq ( RD & ~read_count[8] ),
+ .wrclk ( rxclk ),
+ .wrreq ( WR ),
+ .q ( usbdata ),
+ .rdempty ( ),
+ .rdusedw ( rdusedw ),
+ .wrfull ( ),
+ .wrusedw ( wrusedw ) );
+
+ assign have_pkt_rdy = (rdusedw >= 12'd256);
+ assign have_space = (wrusedw < 12'd760);
+
+ // Rx side fifos
+ wire chan_rdreq;
+ wire [15:0] chan_fifodata;
+ wire [9:0] chan_usedw;
+ wire [NUM_CHAN:0] chan_empty;
+ wire [3:0] rd_select;
+ wire [NUM_CHAN:0] rx_full;
+
+ packet_builder #(NUM_CHAN) rx_pkt_builer (
+ .rxclk ( rxclk ),
+ .reset ( reset ),
+ .adctime ( adctime ),
+ .channels ( 4'd1 ),
+ .chan_rdreq ( chan_rdreq ),
+ .chan_fifodata ( chan_fifodata ),
+ .chan_empty ( chan_empty ),
+ .rd_select ( rd_select ),
+ .chan_usedw ( chan_usedw ),
+ .WR ( WR ),
+ .fifodata ( fifodata ),
+ .have_space ( have_space ),
+ .rssi_0(rssi_0), .rssi_1(rssi_1),
+ .rssi_2(rssi_2),.rssi_3(rssi_3), .debugbus(debug));
+
+ // Detect overrun
+ always @(posedge rxclk)
+ if(reset)
+ rx_overrun <= 1'b0;
+ else if(rx_full[0])
+ rx_overrun <= 1'b1;
+ else if(clear_status)
+ rx_overrun <= 1'b0;
+
+ reg [6:0] test;
+ always @(posedge rxclk)
+ if (reset)
+ test <= 0;
+ else
+ test <= test + 7'd1;
+
+ // TODO write this genericly
+ wire [15:0]ch[NUM_CHAN:0];
+ assign ch[0] = ch_0;
+
+ wire cmd_empty;
+ always @(posedge rxclk)
+ if(reset)
+ rx_WR_enabled <= 1;
+ else if(cmd_empty)
+ rx_WR_enabled <= 1;
+ else if(rx_WR_done)
+ rx_WR_enabled <= 0;
+
+ wire [15:0] dataout [0:NUM_CHAN];
+ wire [9:0] usedw [0:NUM_CHAN];
+
+ generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
+ begin : generate_channel_fifos
+ wire rdreq;
+
+ assign rdreq = (rd_select == i) & chan_rdreq;
+ assign chan_empty[i] = usedw[i] < 10'd126;
+
+ fifo_2k_1clk rx_chan_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( ch[i] ),
+ .rdreq ( rdreq ),
+ .wrreq ( ~rx_full[i] & rxstrobe),
+ .empty ( ),
+ .full ( rx_full[i] ),
+ .q ( dataout[i]),
+ .usedw ( usedw[i] )
+ );
+ end
+ endgenerate
+ wire [7:0] debug;
+ fifo_2k_1clk rx_cmd_fifo (
+ .aclr ( reset ),
+ .clock ( rxclk ),
+ .data ( rx_databus ),
+ .rdreq ( (rd_select == NUM_CHAN) & chan_rdreq ),
+ .wrreq ( rx_WR & rx_WR_enabled),
+ .empty ( cmd_empty),
+ .full ( rx_full[NUM_CHAN] ),
+ .q ( dataout[NUM_CHAN]),
+ .usedw ( usedw[NUM_CHAN] )
+ );
+ assign chan_empty[NUM_CHAN] = cmd_empty | rx_WR_enabled;
+ assign chan_fifodata = dataout[rd_select];
+ assign chan_usedw = usedw[rd_select];
+ assign debugbus = {wrusedw, have_space, RD, read_count[8], rxclk};
+endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_buffer_inband.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -2,10 +2,18 @@
( usbclk, bus_reset, reset, usbdata, WR, have_space,
tx_underrun, channels, tx_i_0, tx_q_0, tx_i_1, tx_q_1,
tx_i_2, tx_q_2, tx_i_3, tx_q_3, txclk, txstrobe,
- clear_status, tx_empty, debugbus
+ clear_status, tx_empty, debugbus,
+ rx_databus, rx_WR, rx_WR_done, rx_WR_enabled, reg_io_enable,
+ reg_data_in, reg_data_out, reg_addr, rssi_0, rssi_1, rssi_2,
+ rssi_3, threshhold
);
-
- parameter NUM_CHAN = 2 ;
+
+ //CHAN_WIDTH is the width of the channel
+ //NUM_CHAN is the number of data channel (index from 0 to NUM_CHAN-1)
+ //index NUM_CHAN is reserved for command
+
+ parameter CHAN_WIDTH = 2 ;
+ parameter NUM_CHAN = 2 ;
/* Debug paramters */
parameter STROBE_RATE_0 = 8'd1 ;
parameter STROBE_RATE_1 = 8'd2 ;
@@ -17,10 +25,19 @@
input wire WR ;
input wire txclk ;
input wire txstrobe ;
+ input wire rx_WR_enabled;
/* Not used yet */
input wire [3:0] channels ;
input wire clear_status ;
-
+ /*register io*/
+ input wire [31:0]reg_data_out;
+ // rssi
+ input wire [31:0]rssi_0;
+ input wire [31:0]rssi_1;
+ input wire [31:0]rssi_2;
+ input wire [31:0]rssi_3;
+ input wire [31:0]threshhold;
+
output wire have_space ;
output wire tx_underrun ;
output wire tx_empty ;
@@ -34,42 +51,62 @@
output wire [15:0] tx_q_2 ;
output wire [15:0] tx_i_3 ;
output wire [15:0] tx_q_3 ;
-
+ output wire [15:0] rx_databus ;
+ output wire rx_WR;
+ output wire rx_WR_done;
+ /* reg_io */
+ output wire [31:0] reg_data_in;
+ output wire [6:0] reg_addr;
+ output wire [1:0] reg_io_enable;
+
/* To generate channel readers */
genvar i ;
/* These will eventually be external register */
- reg [31:0] time_counter ;
- wire [7:0] txstrobe_rate [NUM_CHAN-1:0] ;
+ reg [31:0] adc_time ;
+ wire [7:0] txstrobe_rate [CHAN_WIDTH-1:0] ;
+ wire [31:0] rssi [3:0];
+ assign rssi[0] = rssi_0;
+ assign rssi[1] = rssi_1;
+ assign rssi[2] = rssi_2;
+ assign rssi[3] = rssi_3;
+ always @(posedge txclk)
+ if (reset)
+ adc_time <= 0;
+ else if (txstrobe)
+ adc_time <= adc_time + 1;
+
+
/* Connections between tx_usb_fifo_reader and
cnannel/command processing blocks */
wire [31:0] tx_data_bus ;
- wire [NUM_CHAN:0] chan_WR ;
- wire [NUM_CHAN:0] chan_done ;
+ wire [CHAN_WIDTH:0] chan_WR ;
+ wire [CHAN_WIDTH:0] chan_done ;
/* Connections between data block and the
FX2/TX chains */
- wire [NUM_CHAN:0] chan_underrun ;
- wire [NUM_CHAN:0] chan_txempty ;
+ wire [CHAN_WIDTH:0] chan_underrun ;
+ wire [CHAN_WIDTH:0] chan_txempty ;
/* Conections between tx_data_packet_fifo and
its reader + strobe generator */
- wire [31:0] chan_fifodata [NUM_CHAN:0] ;
- wire chan_pkt_waiting [NUM_CHAN:0] ;
- wire chan_rdreq [NUM_CHAN:0] ;
- wire chan_skip [NUM_CHAN:0] ;
- wire [NUM_CHAN:0] chan_have_space ;
- wire chan_txstrobe [NUM_CHAN-1:0] ;
+ wire [31:0] chan_fifodata [CHAN_WIDTH:0] ;
+ wire chan_pkt_waiting [CHAN_WIDTH:0] ;
+ wire chan_rdreq [CHAN_WIDTH:0] ;
+ wire chan_skip [CHAN_WIDTH:0] ;
+ wire [CHAN_WIDTH:0] chan_have_space ;
+ wire chan_txstrobe [CHAN_WIDTH-1:0] ;
+
+ wire [14:0] debug;
/* Outputs to transmit chains */
- wire [15:0] tx_i [NUM_CHAN-1:0] ;
- wire [15:0] tx_q [NUM_CHAN-1:0] ;
+ wire [15:0] tx_i [CHAN_WIDTH-1:0] ;
+ wire [15:0] tx_q [CHAN_WIDTH-1:0] ;
+ /* TODO: Figure out how to write this genericly */
assign have_space = chan_have_space[0] & chan_have_space[1];
-
- /* TODO: Figure out how to write this genericly */
assign tx_empty = chan_txempty[0] & chan_txempty[1] ;
assign tx_underrun = chan_underrun[0] | chan_underrun[1] ;
assign tx_i_0 = chan_txempty[0] ? 16'b0 : tx_i[0] ;
@@ -85,24 +122,38 @@
assign tx_q_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
assign tx_i_3 = 16'b0 ;
- assign debugbus = {7'b0, have_space, tx_empty, WR, chan_have_space[0],
+ /*assign debugbus = {7'b0, have_space, tx_empty, WR,
chan_have_space[0],
chan_have_space[1], bus_reset, reset, chan_txempty[0],
chan_txempty[1]} ;
-
- usb_fifo_writer tx_usb_packet_writer
- (
- .bus_reset (bus_reset),
- .usbclk (usbclk),
- .WR_fx2 (WR),
- .usbdata (usbdata),
- .reset (reset),
- .txclk (txclk),
- .WR_channel (chan_WR),
- .WR_done_channel (chan_done),
- .ram_data (tx_data_bus)
- );
+ */
+ assign debugbus = {debug, txclk};
-
+ wire [31:0] usbdata_final;
+ wire WR_final;
+
+ tx_packer tx_usb_packer
+ (
+ .bus_reset (bus_reset),
+ .usbclk (usbclk),
+ .WR_fx2 (WR),
+ .usbdata (usbdata),
+ .reset (reset),
+ .txclk (txclk),
+ .usbdata_final (usbdata_final),
+ .WR_final (WR_final)
+ );
+
+ channel_demux channel_demuxer
+ (
+ .usbdata_final (usbdata_final),
+ .WR_final (WR_final),
+ .reset (reset),
+ .txclk (txclk),
+ .WR_channel (chan_WR),
+ .WR_done_channel (chan_done),
+ .ram_data (tx_data_bus)
+ );
+
generate for (i = 0 ; i < NUM_CHAN; i = i + 1)
begin : generate_channel_readers
channel_ram tx_data_packet_fifo
@@ -131,20 +182,58 @@
( .reset (reset),
.tx_clock (txclk),
.tx_strobe (txstrobe),
- .adc_time (32'd0),
+ .adc_time (adc_time),
.samples_format (4'b0),
.tx_q (tx_q[i]),
.tx_i (tx_i[i]),
.underrun (chan_underrun[i]),
- .skip (chan_skip[i]),
+ .skip (chan_skip[i]),
.rdreq (chan_rdreq[i]),
.fifodata (chan_fifodata[i]),
.pkt_waiting (chan_pkt_waiting[i]),
- .tx_empty (chan_txempty[i])
+ .tx_empty (chan_txempty[i]),
+ .rssi (rssi[i]),
+ .threshhold (threshhold)
);
end
endgenerate
+
+
+ channel_ram tx_cmd_packet_fifo
+ ( .reset (reset),
+ .txclk (txclk),
+ .datain (tx_data_bus),
+ .WR (chan_WR[NUM_CHAN]),
+ .WR_done (chan_done[NUM_CHAN]),
+ .have_space (chan_have_space[NUM_CHAN]),
+ .dataout (chan_fifodata[NUM_CHAN]),
+ .packet_waiting (chan_pkt_waiting[NUM_CHAN]),
+ .RD (chan_rdreq[NUM_CHAN]),
+ .RD_done (chan_skip[NUM_CHAN])
+ );
+
+
+ cmd_reader tx_cmd_reader
+ ( .reset (reset),
+ .txclk (txclk),
+ .adc_time
(adc_time),
+ .skip
(chan_skip[NUM_CHAN]),
+ .rdreq
(chan_rdreq[NUM_CHAN]),
+ .fifodata
(chan_fifodata[NUM_CHAN]),
+ .pkt_waiting
(chan_pkt_waiting[NUM_CHAN]),
+ .rx_databus
(rx_databus),
+ .rx_WR (rx_WR),
+ .rx_WR_done
(rx_WR_done),
+ .rx_WR_enabled (rx_WR_enabled),
+ .reg_data_in (reg_data_in),
+ .reg_data_out (reg_data_out),
+ .reg_addr
(reg_addr),
+ .reg_io_enable (reg_io_enable),
+ .debug (debug)
+ );
+
+
endmodule // tx_buffer
Copied: gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_packer.v
(from rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/inband_lib/tx_packer.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_packer.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/tx_packer.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,119 @@
+module tx_packer
+ ( //FX2 Side
+ input bus_reset,
+ input usbclk,
+ input WR_fx2,
+ input [15:0]usbdata,
+
+ // TX Side
+ input reset,
+ input txclk,
+ output reg [31:0] usbdata_final,
+ output reg WR_final);
+
+ reg [8:0] write_count;
+
+ /* Fix FX2 bug */
+ always @(posedge usbclk)
+ begin
+ if(bus_reset) // Use bus reset because this is on usbclk
+ write_count <= #1 0;
+ else if(WR_fx2 & ~write_count[8])
+ write_count <= #1 write_count + 9'd1;
+ else
+ write_count <= #1 WR_fx2 ? write_count : 9'b0;
+ end
+
+ reg WR_fx2_fixed;
+ reg [15:0]usbdata_fixed;
+
+ always @(posedge usbclk)
+ begin
+ WR_fx2_fixed <= WR_fx2 & ~write_count[8];
+ usbdata_fixed <= usbdata;
+ end
+
+ /* Used to convert 16 bits bus_data to the 32 bits wide fifo */
+ reg word_complete ;
+ reg [15:0] usbdata_delayed ;
+ reg writing ;
+ wire [31:0] usbdata_packed ;
+ wire WR_packed ;
+
+ always @(posedge usbclk)
+ begin
+ if (bus_reset)
+ begin
+ word_complete <= 0 ;
+ writing <= 0 ;
+ end
+ else if (WR_fx2_fixed)
+ begin
+ writing <= 1 ;
+ if (word_complete)
+ word_complete <= 0 ;
+ else
+ begin
+ usbdata_delayed <= usbdata_fixed ;
+ word_complete <= 1 ;
+ end
+ end
+ else
+ writing <= 0 ;
+ end
+
+ assign usbdata_packed = {usbdata_fixed, usbdata_delayed} ;
+ assign WR_packed = word_complete & writing ;
+
+ /* Make sure data are sync with usbclk */
+ reg [31:0]usbdata_usbclk;
+ reg WR_usbclk;
+
+ always @(posedge usbclk)
+ begin
+ if (WR_packed)
+ usbdata_usbclk <= usbdata_packed;
+ WR_usbclk <= WR_packed;
+ end
+
+ /* Cross clock boundaries */
+ reg [31:0] usbdata_tx ;
+ reg WR_tx;
+ reg WR_1;
+ reg WR_2;
+
+ always @(posedge txclk) usbdata_tx <= usbdata_usbclk;
+
+ always @(posedge txclk)
+ if (reset)
+ WR_1 <= 0;
+ else
+ WR_1 <= WR_usbclk;
+
+ always @(posedge txclk)
+ if (reset)
+ WR_2 <= 0;
+ else
+ WR_2 <= WR_1;
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ WR_tx <= 0;
+ else
+ WR_tx <= WR_1 & ~WR_2;
+ end
+
+ always @(posedge txclk)
+ begin
+ if (reset)
+ WR_final <= 0;
+ else
+ begin
+ WR_final <= WR_tx;
+ if (WR_tx)
+ usbdata_final <= usbdata_tx;
+ end
+ end
+
+endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_reader.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -1,127 +1,24 @@
-module usb_fifo_reader (tx_clock, fifodata, pkt_waiting, reset,
- rdreq, done_chan, WR_chan, tx_data_bus, have_space_chan);
+module usb_fifo_reader (
+ input usbclk,
+ input bus_reset,
+ input RD,
+ output rdreq,
+ );
- /* Module parameters */
- parameter NUM_CHAN = 2 ;
- parameter WIDTH = 32 ;
- parameter PKT_SIZE = 512 ;
+ // FX2 Bug Fix
+ reg [8:0] read_count;
+ always @(negedge usbclk)
+ if(bus_reset)
+ read_count <= #1 9'd0;
+ else if(RD & ~read_count[8])
+ read_count <= #1 read_count + 9'd1;
+ else
+ read_count <= #1 RD ? read_count : 9'b0;
+
+ assign rdreq = RD & ~read_count[8];
- input wire tx_clock ;
- input wire reset ;
- input wire [WIDTH-1:0] fifodata ;
- input wire pkt_waiting ;
- input wire [NUM_CHAN:0] have_space_chan ;
- output reg rdreq ;
- output reg [NUM_CHAN:0] done_chan ;
- output reg [NUM_CHAN:0] WR_chan ;
- output reg [WIDTH-1:0] tx_data_bus ;
-
-
-
- /* States definition */
- `define IDLE 3'd0
- `define WAIT 3'd1
- `define READ_HEADER 3'd2
- `define FORWARD_DATA 3'd3
- `define SKIP_REST 3'd4
-
- /* Channel Ids */
- `define TXCHAN0 5'h0
- `define TXCHAN1 5'h1
- `define TXCMD 5'h1F
-
- /* Local registers */
- reg [2:0] reader_state ;
- reg [4:0] channel ;
- reg [9:0] pkt_length ;
- reg [9:0] read_length ;
- /* State Machine */
- always @(posedge tx_clock)
- begin
- if (reset)
- begin
- reader_state <= `IDLE ;
- rdreq <= 0 ;
- WR_chan <= {(NUM_CHAN+1){1'b0}} ;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
- end
- else
- begin
-
- case(reader_state)
- `IDLE:
- begin
- reader_state <= pkt_waiting ? `WAIT : `IDLE
;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
- rdreq <= pkt_waiting ;
- end
-
- /* Wait for the fifo's data to show up */
- `WAIT:
- begin
- reader_state <= `READ_HEADER ;
- rdreq <= 0 ;
- end
-
- `READ_HEADER:
- begin
- /* Read header fields */
- channel <= (fifodata[20:16]) ;
- pkt_length <= fifodata[8:0] + 10'd8 ;
- read_length <= 10'd0 ;
-
- if (have_space_chan[channel])
- begin
- reader_state <= `FORWARD_DATA ;
- rdreq <= 1;
- end
- end
-
- `FORWARD_DATA:
- begin
- read_length <= read_length + 10'd4 ;
-
- // If end of payload...
- if (read_length == pkt_length)
- begin
- reader_state <= rdreq ? `SKIP_REST : `IDLE ;
-
- /* Data pushing done */
- WR_chan <= {(NUM_CHAN+1){1'b0}} ;
-
- /* Notify next block */
- done_chan[channel] <= 1 ;
-
- end
- else
- WR_chan[channel] <= 1 ;
-
- if (read_length == PKT_SIZE - 8)
- rdreq <= 0;
-
- /* Forward data */
- tx_data_bus <= fifodata ;
- end
-
- `SKIP_REST:
- begin
- read_length <= read_length + 10'd4;
- done_chan <= {(NUM_CHAN+1){1'b0}} ;
-
- if (read_length == PKT_SIZE - 4)
- reader_state <= `IDLE ;
- else if (read_length == PKT_SIZE - 8)
- rdreq <= 0 ;
- end
-
- default:
- begin
- reader_state <= `IDLE;
- end
- endcase
- end
- end
+
endmodule
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/inband_lib/usb_fifo_writer.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -3,7 +3,7 @@
#(parameter BUS_WIDTH = 16,
parameter NUM_CHAN = 2,
parameter FIFO_WIDTH = 32)
- (//FX2 Side
+ ( //FX2 Side
input bus_reset,
input usbclk,
input WR_fx2,
@@ -152,8 +152,10 @@
// Store channel and forware header
HEADER: begin
- channel <= (usbdata_final[`CHANNEL]) ;
- WR_channel[usbdata_final[`CHANNEL]] <= 1;
+ channel <= (usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN :
usbdata_final[`CHANNEL]) ;
+ WR_channel[(usbdata_final[`CHANNEL] == 5'h1f ? NUM_CHAN :
usbdata_final[`CHANNEL])] <= 1;
+ //channel <= usbdata_final[`CHANNEL] ;
+ //WR_channel[usbdata_final[`CHANNEL]] <= 1;
ram_data <= usbdata_final;
read_length <= 10'd4 ;
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.bsf
2007-09-01 19:05:09 UTC (rev 6258)
@@ -26,8 +26,8 @@
(port
(pt 0 32)
(input)
- (text "data[31..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
- (text "data[31..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 0 0 60 14)(font "Arial" (font_size
8)))
+ (text "data[15..0]" (rect 20 26 71 39)(font "Arial" (font_size
8)))
(line (pt 0 32)(pt 16 32)(line_width 3))
)
(port
@@ -75,15 +75,15 @@
(port
(pt 160 72)
(output)
- (text "wrusedw[7..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
- (text "wrusedw[7..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
+ (text "wrusedw[8..0]" (rect 0 0 84 14)(font "Arial" (font_size
8)))
+ (text "wrusedw[8..0]" (rect 69 66 132 79)(font "Arial"
(font_size 8)))
(line (pt 160 72)(pt 144 72)(line_width 3))
)
(port
(pt 160 96)
(output)
- (text "q[31..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
- (text "q[31..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
+ (text "q[15..0]" (rect 0 0 42 14)(font "Arial" (font_size 8)))
+ (text "q[15..0]" (rect 105 90 141 103)(font "Arial" (font_size
8)))
(line (pt 160 96)(pt 144 96)(line_width 3))
)
(port
@@ -96,12 +96,13 @@
(port
(pt 160 136)
(output)
- (text "rdusedw[7..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
- (text "rdusedw[7..0]" (rect 73 130 135 143)(font "Arial"
(font_size 8)))
+ (text "rdusedw[8..0]" (rect 0 0 80 14)(font "Arial" (font_size
8)))
+ (text "rdusedw[8..0]" (rect 73 130 135 143)(font "Arial"
(font_size 8)))
(line (pt 160 136)(pt 144 136)(line_width 3))
)
(drawing
- (text "32 bits x 256 words" (rect 63 156 144 168)(font "Arial"
))
+ (text "(ack)" (rect 51 99 72 111)(font "Arial" ))
+ (text "16 bits x 512 words" (rect 63 156 144 168)(font "Arial"
))
(line (pt 16 16)(pt 144 16)(line_width 1))
(line (pt 144 16)(pt 144 168)(line_width 1))
(line (pt 144 168)(pt 16 168)(line_width 1))
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.cmp
2007-09-01 19:05:09 UTC (rev 6258)
@@ -17,15 +17,15 @@
PORT
(
aclr : IN STD_LOGIC := '0';
- data : IN STD_LOGIC_VECTOR (31 DOWNTO 0);
+ data : IN STD_LOGIC_VECTOR (15 DOWNTO 0);
rdclk : IN STD_LOGIC ;
rdreq : IN STD_LOGIC ;
wrclk : IN STD_LOGIC ;
wrreq : IN STD_LOGIC ;
- q : OUT STD_LOGIC_VECTOR (31 DOWNTO 0);
+ q : OUT STD_LOGIC_VECTOR (15 DOWNTO 0);
rdempty : OUT STD_LOGIC ;
- rdusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0);
+ rdusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0);
wrfull : OUT STD_LOGIC ;
- wrusedw : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)
+ wrusedw : OUT STD_LOGIC_VECTOR (8 DOWNTO 0)
);
end component;
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.inc
2007-09-01 19:05:09 UTC (rev 6258)
@@ -16,7 +16,7 @@
FUNCTION fifo_1k
(
aclr,
- data[31..0],
+ data[15..0],
rdclk,
rdreq,
wrclk,
@@ -24,9 +24,9 @@
)
RETURNS (
- q[31..0],
+ q[15..0],
rdempty,
- rdusedw[7..0],
+ rdusedw[8..0],
wrfull,
- wrusedw[7..0]
+ wrusedw[8..0]
);
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -47,27 +47,27 @@
wrusedw);
input aclr;
- input [31:0] data;
+ input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [31:0] q;
+ output [15:0] q;
output rdempty;
- output [7:0] rdusedw;
+ output [8:0] rdusedw;
output wrfull;
- output [7:0] wrusedw;
+ output [8:0] wrusedw;
wire sub_wire0;
- wire [7:0] sub_wire1;
+ wire [8:0] sub_wire1;
wire sub_wire2;
- wire [31:0] sub_wire3;
- wire [7:0] sub_wire4;
+ wire [15:0] sub_wire3;
+ wire [8:0] sub_wire4;
wire rdempty = sub_wire0;
- wire [7:0] wrusedw = sub_wire1[7:0];
+ wire [8:0] wrusedw = sub_wire1[8:0];
wire wrfull = sub_wire2;
- wire [31:0] q = sub_wire3[31:0];
- wire [7:0] rdusedw = sub_wire4[7:0];
+ wire [15:0] q = sub_wire3[15:0];
+ wire [8:0] rdusedw = sub_wire4[8:0];
dcfifo dcfifo_component (
.wrclk (wrclk),
@@ -92,11 +92,11 @@
dcfifo_component.clocks_are_synchronized = "FALSE",
dcfifo_component.intended_device_family = "Cyclone",
dcfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
- dcfifo_component.lpm_numwords = 256,
- dcfifo_component.lpm_showahead = "OFF",
+ dcfifo_component.lpm_numwords = 512,
+ dcfifo_component.lpm_showahead = "ON",
dcfifo_component.lpm_type = "dcfifo",
- dcfifo_component.lpm_width = 32,
- dcfifo_component.lpm_widthu = 8,
+ dcfifo_component.lpm_width = 16,
+ dcfifo_component.lpm_widthu = 9,
dcfifo_component.overflow_checking = "ON",
dcfifo_component.underflow_checking = "ON",
dcfifo_component.use_eab = "ON";
@@ -113,19 +113,19 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
@@ -139,35 +139,35 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_1k_bb.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -42,16 +42,16 @@
wrusedw);
input aclr;
- input [31:0] data;
+ input [15:0] data;
input rdclk;
input rdreq;
input wrclk;
input wrreq;
- output [31:0] q;
+ output [15:0] q;
output rdempty;
- output [7:0] rdusedw;
+ output [8:0] rdusedw;
output wrfull;
- output [7:0] wrusedw;
+ output [8:0] wrusedw;
endmodule
@@ -64,19 +64,19 @@
// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
// Retrieval info: PRIVATE: Clock NUMERIC "4"
-// Retrieval info: PRIVATE: Depth NUMERIC "256"
+// Retrieval info: PRIVATE: Depth NUMERIC "512"
// Retrieval info: PRIVATE: Empty NUMERIC "1"
// Retrieval info: PRIVATE: Full NUMERIC "1"
// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
-// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: Optimize NUMERIC "2"
// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
// Retrieval info: PRIVATE: UsedW NUMERIC "1"
-// Retrieval info: PRIVATE: Width NUMERIC "32"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
// Retrieval info: PRIVATE: dc_aclr NUMERIC "1"
// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
// Retrieval info: PRIVATE: rsFull NUMERIC "0"
@@ -90,35 +90,35 @@
// Retrieval info: CONSTANT: CLOCKS_ARE_SYNCHRONIZED STRING "FALSE"
// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
-// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "256"
-// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "512"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
// Retrieval info: CONSTANT: LPM_TYPE STRING "dcfifo"
-// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "32"
-// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "8"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "9"
// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
// Retrieval info: CONSTANT: USE_EAB STRING "ON"
// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT GND aclr
-// Retrieval info: USED_PORT: data 0 0 32 0 INPUT NODEFVAL data[31..0]
-// Retrieval info: USED_PORT: q 0 0 32 0 OUTPUT NODEFVAL q[31..0]
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
// Retrieval info: USED_PORT: rdclk 0 0 0 0 INPUT NODEFVAL rdclk
// Retrieval info: USED_PORT: rdempty 0 0 0 0 OUTPUT NODEFVAL rdempty
// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
-// Retrieval info: USED_PORT: rdusedw 0 0 8 0 OUTPUT NODEFVAL rdusedw[7..0]
+// Retrieval info: USED_PORT: rdusedw 0 0 9 0 OUTPUT NODEFVAL rdusedw[8..0]
// Retrieval info: USED_PORT: wrclk 0 0 0 0 INPUT NODEFVAL wrclk
// Retrieval info: USED_PORT: wrfull 0 0 0 0 OUTPUT NODEFVAL wrfull
// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
-// Retrieval info: USED_PORT: wrusedw 0 0 8 0 OUTPUT NODEFVAL wrusedw[7..0]
-// Retrieval info: CONNECT: @data 0 0 32 0 data 0 0 32 0
-// Retrieval info: CONNECT: q 0 0 32 0 @q 0 0 32 0
+// Retrieval info: USED_PORT: wrusedw 0 0 9 0 OUTPUT NODEFVAL wrusedw[8..0]
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
// Retrieval info: CONNECT: @rdclk 0 0 0 0 rdclk 0 0 0 0
// Retrieval info: CONNECT: @wrclk 0 0 0 0 wrclk 0 0 0 0
// Retrieval info: CONNECT: rdempty 0 0 0 0 @rdempty 0 0 0 0
-// Retrieval info: CONNECT: rdusedw 0 0 8 0 @rdusedw 0 0 8 0
+// Retrieval info: CONNECT: rdusedw 0 0 9 0 @rdusedw 0 0 9 0
// Retrieval info: CONNECT: wrfull 0 0 0 0 @wrfull 0 0 0 0
-// Retrieval info: CONNECT: wrusedw 0 0 8 0 @wrusedw 0 0 8 0
+// Retrieval info: CONNECT: wrusedw 0 0 9 0 @wrusedw 0 0 9 0
// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_1k.v TRUE
Copied:
gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_2k_1clk.v (from
rev 6250,
gnuradio/branches/developers/zhuochen/burst/usrp/fpga/megacells/fifo_2k_1clk.v)
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_2k_1clk.v
(rev 0)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/megacells/fifo_2k_1clk.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -0,0 +1,167 @@
+// megafunction wizard: %LPM_FIFO+%
+// GENERATION: STANDARD
+// VERSION: WM1.0
+// MODULE: scfifo
+
+// ============================================================
+// File Name: fifo_2k_1clk.v
+// Megafunction Name(s):
+// scfifo
+// ============================================================
+// ************************************************************
+// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
+//
+// 5.1 Build 213 01/19/2006 SP 1 SJ Web Edition
+// ************************************************************
+
+
+//Copyright (C) 1991-2006 Altera Corporation
+//Your use of Altera Corporation's design tools, logic functions
+//and other software and tools, and its AMPP partner logic
+//functions, and any output files any of the foregoing
+//(including device programming or simulation files), and any
+//associated documentation or information are expressly subject
+//to the terms and conditions of the Altera Program License
+//Subscription Agreement, Altera MegaCore Function License
+//Agreement, or other applicable license agreement, including,
+//without limitation, that your use is for the sole purpose of
+//programming logic devices manufactured by Altera and sold by
+//Altera or its authorized distributors. Please refer to the
+//applicable agreement for further details.
+
+
+// synopsys translate_off
+`timescale 1 ps / 1 ps
+// synopsys translate_on
+module fifo_2k_1clk (
+ aclr,
+ clock,
+ data,
+ rdreq,
+ wrreq,
+ empty,
+ full,
+ q,
+ usedw);
+
+ input aclr;
+ input clock;
+ input [15:0] data;
+ input rdreq;
+ input wrreq;
+ output empty;
+ output full;
+ output [15:0] q;
+ output [9:0] usedw;
+
+ wire [9:0] sub_wire0;
+ wire sub_wire1;
+ wire [15:0] sub_wire2;
+ wire sub_wire3;
+ wire [9:0] usedw = sub_wire0[9:0];
+ wire empty = sub_wire1;
+ wire [15:0] q = sub_wire2[15:0];
+ wire full = sub_wire3;
+
+ scfifo scfifo_component (
+ .rdreq (rdreq),
+ .aclr (aclr),
+ .clock (clock),
+ .wrreq (wrreq),
+ .data (data),
+ .usedw (sub_wire0),
+ .empty (sub_wire1),
+ .q (sub_wire2),
+ .full (sub_wire3)
+ // synopsys translate_off
+ ,
+ .almost_empty (),
+ .sclr (),
+ .almost_full ()
+ // synopsys translate_on
+ );
+ defparam
+ scfifo_component.add_ram_output_register = "OFF",
+ scfifo_component.intended_device_family = "Cyclone",
+ scfifo_component.lpm_hint = "RAM_BLOCK_TYPE=M4K",
+ scfifo_component.lpm_numwords = 1024,
+ scfifo_component.lpm_showahead = "OFF",
+ scfifo_component.lpm_type = "scfifo",
+ scfifo_component.lpm_width = 16,
+ scfifo_component.lpm_widthu = 10,
+ scfifo_component.overflow_checking = "ON",
+ scfifo_component.underflow_checking = "ON",
+ scfifo_component.use_eab = "ON";
+
+
+endmodule
+
+// ============================================================
+// CNX file retrieval info
+// ============================================================
+// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
+// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
+// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
+// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
+// Retrieval info: PRIVATE: Clock NUMERIC "0"
+// Retrieval info: PRIVATE: Depth NUMERIC "1024"
+// Retrieval info: PRIVATE: Empty NUMERIC "1"
+// Retrieval info: PRIVATE: Full NUMERIC "1"
+// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
+// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "1"
+// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
+// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: Optimize NUMERIC "2"
+// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
+// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
+// Retrieval info: PRIVATE: UsedW NUMERIC "1"
+// Retrieval info: PRIVATE: Width NUMERIC "16"
+// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
+// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
+// Retrieval info: PRIVATE: rsFull NUMERIC "0"
+// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
+// Retrieval info: PRIVATE: sc_aclr NUMERIC "1"
+// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
+// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
+// Retrieval info: PRIVATE: wsFull NUMERIC "1"
+// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
+// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
+// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone"
+// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M4K"
+// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
+// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "OFF"
+// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
+// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "16"
+// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
+// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
+// Retrieval info: CONSTANT: USE_EAB STRING "ON"
+// Retrieval info: USED_PORT: aclr 0 0 0 0 INPUT NODEFVAL aclr
+// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL clock
+// Retrieval info: USED_PORT: data 0 0 16 0 INPUT NODEFVAL data[15..0]
+// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL empty
+// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL full
+// Retrieval info: USED_PORT: q 0 0 16 0 OUTPUT NODEFVAL q[15..0]
+// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL rdreq
+// Retrieval info: USED_PORT: usedw 0 0 10 0 OUTPUT NODEFVAL usedw[9..0]
+// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL wrreq
+// Retrieval info: CONNECT: @data 0 0 16 0 data 0 0 16 0
+// Retrieval info: CONNECT: q 0 0 16 0 @q 0 0 16 0
+// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
+// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
+// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
+// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
+// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
+// Retrieval info: CONNECT: usedw 0 0 10 0 @usedw 0 0 10 0
+// Retrieval info: CONNECT: @aclr 0 0 0 0 aclr 0 0 0 0
+// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.inc TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.cmp TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk.bsf TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_inst.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_bb.v TRUE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_waveforms.html FALSE
+// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_2k_1clk_wave*.jpg FALSE
Modified: gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/serial_io.v
===================================================================
--- gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/serial_io.v
2007-09-01 18:42:44 UTC (rev 6257)
+++ gnuradio/branches/features/inband-usb/usrp/fpga/sdr_lib/serial_io.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -40,9 +40,12 @@
input wire [31:0] readback_4,
input wire [31:0] readback_5,
input wire [31:0] readback_6,
- input wire [31:0] readback_7
+ input wire [31:0] readback_7,
+ output wire [15:0] debug
);
+ assign debug = {enable, ser_ctr, is_read, write_done, serial_data_in,
serial_data_out,
+ serial_strobe, serial_clock,
master_clk};
reg is_read;
reg [7:0] ser_ctr;
reg write_done;
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.qsf
2007-09-01 19:05:09 UTC (rev 6258)
@@ -372,9 +372,14 @@
set_instance_assignment -name PARTITION_HIERARCHY no_file_for_top_partition
-to | -section_id Top
set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
set_global_assignment -name FITTER_AUTO_EFFORT_DESIRED_SLACK_MARGIN "100 ps"
+set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_demux.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_packer.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/cmd_reader.v
+set_global_assignment -name VERILOG_FILE ../../megacells/fifo_2k_1clk.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/packet_builder.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/rx_buffer_inband.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/atr_delay.v
set_global_assignment -name VERILOG_FILE ../../megacells/fifo_1k.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/usb_fifo_writer.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/tx_buffer_inband.v
set_global_assignment -name VERILOG_FILE ../../inband_lib/chan_fifo_reader.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/cic_dec_shifter.v
@@ -413,4 +418,5 @@
set_global_assignment -name VERILOG_FILE ../../sdr_lib/serial_io.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/strobe_gen.v
set_global_assignment -name VERILOG_FILE ../../sdr_lib/sign_extend.v
-set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
\ No newline at end of file
+set_global_assignment -name VERILOG_FILE ../../inband_lib/channel_ram.v
+set_global_assignment -name VERILOG_FILE ../../inband_lib/register_io.v
\ No newline at end of file
Modified:
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/fpga/toplevel/usrp_inband_usb/usrp_inband_usb.v
2007-09-01 19:05:09 UTC (rev 6258)
@@ -19,7 +19,8 @@
// along with this program; if not, write to the Free Software
// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
//
-`define IN_BAND
+`define TX_IN_BAND
+`define RX_IN_BAND
`include "config.vh"
`include "../../../firmware/include/fpga_regs_common.v"
@@ -115,6 +116,12 @@
reg [15:0] debug_counter;
reg [15:0] loopback_i_0,loopback_q_0;
+
+ //Connection RX inband <-> TX inband
+ wire rx_WR;
+ wire [15:0] rx_databus;
+ wire rx_WR_done;
+ wire rx_WR_enabled;
////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
// Transmit Side
`ifdef TX_ON
@@ -123,7 +130,17 @@
assign bb_tx_i1 = ch2tx;
assign bb_tx_q1 = ch3tx;
-`ifdef IN_BAND
+wire [6:0] reg_addr;
+wire [31:0] reg_data_out;
+wire [31:0] reg_data_in;
+wire [1:0] reg_io_enable;
+wire [31:0] rssi_threshhold;
+register_io register_control
+(.clk(clk64),.reset(1'b0),.enable(reg_io_enable),.addr(reg_addr),.datain(reg_data_in),
+ .dataout(reg_data_out),.rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold));
+
+`ifdef TX_IN_BAND
tx_buffer_inband tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
.usbdata(usbdata),.WR(WR),.have_space(have_space),.tx_underrun(tx_underrun),
@@ -135,7 +152,17 @@
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
.tx_empty(tx_empty),
- .debugbus(tx_debugbus) );
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus),
+ .rx_WR_done(rx_WR_done),
+ .rx_WR_enabled(rx_WR_enabled),
+ .reg_addr(reg_addr),
+ .reg_data_out(reg_data_out),
+ .reg_data_in(reg_data_in),
+ .reg_io_enable(reg_io_enable),
+ .debugbus(tx_debugbus),
+ .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2),
+ .rssi_3(rssi_3), .threshhold(rssi_threshhold));
`else
tx_buffer tx_buffer
( .usbclk(usbclk),.bus_reset(tx_bus_reset),.reset(tx_dsp_reset),
@@ -147,8 +174,7 @@
.tx_i_3(),.tx_q_3(),
.txclk(clk64),.txstrobe(strobe_interp),
.clear_status(clear_status),
- .tx_empty(tx_empty),
- .debugbus(tx_debugbus) );
+ .tx_empty(tx_empty));
`endif
`ifdef TX_EN_0
@@ -226,7 +252,6 @@
wire [15:0]
ddc0_in_i,ddc0_in_q,ddc1_in_i,ddc1_in_q,ddc2_in_i,ddc2_in_q,ddc3_in_i,ddc3_in_q;
wire [31:0] rssi_0,rssi_1,rssi_2,rssi_3;
-
adc_interface
adc_interface(.clock(clk64),.reset(rx_dsp_reset),.enable(1'b1),
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
.rx_a_a(rx_a_a),.rx_b_a(rx_b_a),.rx_a_b(rx_a_b),.rx_b_b(rx_b_b),
@@ -234,8 +259,27 @@
.ddc0_in_i(ddc0_in_i),.ddc0_in_q(ddc0_in_q),
.ddc1_in_i(ddc1_in_i),.ddc1_in_q(ddc1_in_q),
.ddc2_in_i(ddc2_in_i),.ddc2_in_q(ddc2_in_q),
-
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan) );
-
+
.ddc3_in_i(ddc3_in_i),.ddc3_in_q(ddc3_in_q),.rx_numchan(rx_numchan));
+ `ifdef RX_IN_BAND
+ rx_buffer_inband rx_buffer
+ ( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
+ .reset_regs(rx_dsp_reset),
+
.usbdata(usbdata_out),.RD(RD),.have_pkt_rdy(have_pkt_rdy),.rx_overrun(rx_overrun),
+ .channels(rx_numchan),
+ .ch_0(ch0rx),.ch_1(ch1rx),
+ .ch_2(ch2rx),.ch_3(ch3rx),
+ .ch_4(ch4rx),.ch_5(ch5rx),
+ .ch_6(ch6rx),.ch_7(ch7rx),
+ .rxclk(clk64),.rxstrobe(hb_strobe),
+ .clear_status(clear_status),
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
+ .rx_WR(rx_WR),
+ .rx_databus(rx_databus),
+ .rx_WR_done(rx_WR_done),
+ .rx_WR_enabled(rx_WR_enabled),
+ .debugbus(rx_debugbus),
+ .rssi_0(rssi_0), .rssi_1(rssi_1), .rssi_2(rssi_2), .rssi_3(rssi_3));
+ `else
rx_buffer rx_buffer
( .usbclk(usbclk),.bus_reset(rx_bus_reset),.reset(rx_dsp_reset),
.reset_regs(rx_dsp_reset),
@@ -247,8 +291,9 @@
.ch_6(ch6rx),.ch_7(ch7rx),
.rxclk(clk64),.rxstrobe(hb_strobe),
.clear_status(clear_status),
-
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe),
- .debugbus(rx_debugbus) );
+
.serial_addr(serial_addr),.serial_data(serial_data),.serial_strobe(serial_strobe)/*,
+ .debugbus(rx_debugbus)*/);
+ `endif
`ifdef RX_EN_0
rx_chain #(`FR_RX_FREQ_0,`FR_RX_PHASE_0) rx_chain_0
@@ -305,7 +350,6 @@
assign capabilities[3] = `RX_CAP_HB;
assign capabilities[2:0] = `RX_CAP_NCHAN;
-
serial_io serial_io
( .master_clk(clk64),.serial_clock(SCLK),.serial_data_in(SDI),
.enable(SEN_FPGA),.reset(1'b0),.serial_data_out(SDO),
Modified:
gnuradio/branches/features/inband-usb/usrp/host/lib/inband/gen_test_packets.py
===================================================================
---
gnuradio/branches/features/inband-usb/usrp/host/lib/inband/gen_test_packets.py
2007-09-01 18:42:44 UTC (rev 6257)
+++
gnuradio/branches/features/inband-usb/usrp/host/lib/inband/gen_test_packets.py
2007-09-01 19:05:09 UTC (rev 6258)
@@ -70,7 +70,7 @@
lengths = gen_shuffled_lengths()
npkts = len(lengths) # number of packets we'll generator on
each stream
pkt_gen_0 = packet_sequence_generator(0, lengths)
- pkt_gen_1 = packet_sequence_generator(1, gen_shuffled_lengths())
+ pkt_gen_1 = packet_sequence_generator(0x1f, gen_shuffled_lengths())
pkt_gen = (pkt_gen_0, pkt_gen_1)
which_gen = (npkts * [0]) + (npkts * [1])
| [Prev in Thread] |
Current Thread |
[Next in Thread] |
- [Commit-gnuradio] r6258 - in gnuradio/branches/features/inband-usb/usrp: fpga/inband_lib fpga/megacells fpga/sdr_lib fpga/toplevel/usrp_inband_usb host/lib/inband,
gnychis <=