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[Commit-gnuradio] r6103 - in gnuradio/branches/developers/zhuochen/simul
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From: |
gnychis |
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Subject: |
[Commit-gnuradio] r6103 - in gnuradio/branches/developers/zhuochen/simulations: . burst_test |
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Date: |
Thu, 2 Aug 2007 14:56:13 -0600 (MDT) |
Author: gnychis
Date: 2007-08-02 14:56:13 -0600 (Thu, 02 Aug 2007)
New Revision: 6103
Added:
gnuradio/branches/developers/zhuochen/simulations/burst_test/
gnuradio/branches/developers/zhuochen/simulations/burst_test/chan_fifo_reader.v
gnuradio/branches/developers/zhuochen/simulations/burst_test/channel_ram.v
gnuradio/branches/developers/zhuochen/simulations/burst_test/strobe_gen.v
gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v
Log:
Adding the files for the burst test
Added:
gnuradio/branches/developers/zhuochen/simulations/burst_test/chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/simulations/burst_test/chan_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/zhuochen/simulations/burst_test/chan_fifo_reader.v
2007-08-02 20:56:13 UTC (rev 6103)
@@ -0,0 +1,195 @@
+module chan_fifo_reader
+ ( reset, tx_clock, tx_strobe, adc_time, samples_format,
+ fifodata, pkt_waiting, rdreq, skip, tx_q, tx_i,
+ underrun, tx_empty ) ;
+
+ input wire reset ;
+ input wire tx_clock ;
+ input wire tx_strobe ; //signal to output tx_i and
tx_q
+ input wire [31:0] adc_time ; //current time
+ input wire [3:0] samples_format ;// not useful at this
point
+ input wire [31:0] fifodata ; //the data input
+ input wire pkt_waiting ; //signal the next packet is
ready
+ output reg rdreq ; //actually an ack to the current
fifodata
+ output reg skip ; //finish reading current packet
+ output reg [15:0] tx_q ; //top 16 bit output of fifodata
+ output reg [15:0] tx_i ; //bottom 16 bit output of fifodata
+ output reg underrun ;
+ output reg tx_empty ; //cause 0 to be the output
+
+ // Should not be needed if adc clock rate < tx clock rate
+ // Used only to debug
+ `define JITTER 5
+
+ //Samples format
+ // 16 bits interleaved complex samples
+ `define QI16 4'b0
+
+ // States
+ parameter IDLE = 3'd0;
+ parameter HEADER = 3'd1;
+ parameter TIMESTAMP = 3'd2;
+ parameter WAIT = 3'd3;
+ parameter WAITSTROBE = 3'd4;
+ parameter SEND = 3'd5;
+
+ // Header format
+ `define PAYLOAD 8:2
+ `define ENDOFBURST 27
+ `define STARTOFBURST 28
+
+
+ /* State registers */
+ reg [2:0] reader_state;
+ reg [6:0] payload_len;
+ reg [6:0] read_len;
+ reg [31:0] timestamp;
+ reg burst; //pkt is a continuation
of prev pkts
+ reg trash; //prev pkt has been
trashed
+
+ always @(posedge tx_clock)
+ begin
+ if (reset)
+ begin
+ reader_state <= IDLE;
+ rdreq <= 0;
+ skip <= 0;
+ underrun <= 0;
+ burst <= 0;
+ tx_empty <= 1;
+ tx_q <= 0;
+ tx_i <= 0;
+ trash <= 0;
+ end
+ else
+ begin
+ case (reader_state)
+ IDLE:
+ begin
+ /*
+ * reset all the variables and wait for a tx_strobe
+ * it is assumed that the ram connected to this fifo_reader
+ * is a short hand fifo meaning that the header to the next
packet
+ * is already available to this fifo_reader when pkt_waiting is
on
+ */
+ skip <=0;
+ tx_empty <= 1;
+ if (pkt_waiting == 1)
+ begin
+ reader_state <= HEADER;
+ rdreq <= 1;
+ underrun <= 0;
+ end
+ else if (burst == 1)
+ underrun <= 1;
+ end
+ /* Process header */
+ HEADER:
+ begin
+ //Check Start/End burst flag
+ case ({fifodata[`STARTOFBURST], fifodata[`ENDOFBURST]})
+ 2'd0: burst <= burst;
+ 2'd1: burst <= 0;
+ 2'd2: burst <= 1;
+ default: burst <= 0;
+ endcase
+ //Check trash
+ if (trash == 1 && fifodata[`STARTOFBURST] == 0)
+ begin
+ trash <= 1;
+ skip <= 1;
+ reader_state <= IDLE;
+ rdreq <= 0;
+ end
+ else
+ begin
+ trash <= 0;
+ payload_len <= fifodata[`PAYLOAD];
+ read_len <= 0;
+ reader_state <= TIMESTAMP;
+ rdreq <= 1;
+ end
+ end
+
+ TIMESTAMP:
+ begin
+ timestamp <= fifodata;
+ reader_state <= WAIT;
+ rdreq <= 0;
+ end
+
+ // Decide if we wait, send or discard samples
+ WAIT:
+ begin
+ // Let's send it
+ if ((timestamp < (adc_time + `JITTER) && (timestamp > adc_time))
+ || timestamp == 32'hFFFFFFFF)
+ begin
+ reader_state <= WAITSTROBE;
+ trash <= 0;
+ end
+ // Wait a little bit more
+ else if (timestamp > adc_time + `JITTER)
+ begin
+ reader_state <= WAIT;
+ trash <= 0;
+ end
+ // Outdate
+ else
+ begin
+ trash <= 1;
+ reader_state <= IDLE;
+ skip <= 1;
+ end
+ end
+
+ // Wait for the transmit chain to be ready
+ WAITSTROBE:
+ begin
+ // If end of payload...
+ if (read_len == payload_len)
+ begin
+ reader_state <= IDLE;
+ skip <= 1;
+ tx_empty <= 1;
+ end
+ else if (tx_strobe == 1)
+ begin
+ reader_state <= SEND;
+ rdreq <= 1;
+ end
+ end
+
+ // Send the samples to the tx_chain
+ SEND:
+ begin
+ reader_state <= WAITSTROBE;
+ read_len <= read_len + 7'd1;
+ tx_empty <= 0;
+ rdreq <= 0;
+
+ case(samples_format)
+ `QI16:
+ begin
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
+ end
+
+ default:
+ begin
+ tx_i <= fifodata[15:0];
+ tx_q <= fifodata[31:16];
+ end
+ endcase
+ end
+
+ default:
+ begin
+ //error handling
+ reader_state <= IDLE;
+ end
+ endcase
+ end
+end
+
+endmodule
Added:
gnuradio/branches/developers/zhuochen/simulations/burst_test/channel_ram.v
===================================================================
--- gnuradio/branches/developers/zhuochen/simulations/burst_test/channel_ram.v
(rev 0)
+++ gnuradio/branches/developers/zhuochen/simulations/burst_test/channel_ram.v
2007-08-02 20:56:13 UTC (rev 6103)
@@ -0,0 +1,114 @@
+module channel_ram
+ ( // System
+ input txclk,
+ input reset,
+
+ // USB side
+ input [31:0] datain,
+ input WR,
+ input WR_done,
+ output have_space,
+
+ // Reader side
+ output [31:0] dataout,
+ input RD,
+ input RD_done,
+ output packet_waiting);
+
+ reg [6:0] wr_addr, rd_addr;
+ reg [1:0] which_ram_wr, which_ram_rd;
+ reg [2:0] nb_packets;
+
+ reg [31:0] ram0 [0:127];
+ reg [31:0] ram1 [0:127];
+ reg [31:0] ram2 [0:127];
+ reg [31:0] ram3 [0:127];
+
+ reg [31:0] dataout0;
+ reg [31:0] dataout1;
+ reg [31:0] dataout2;
+ reg [31:0] dataout3;
+
+ wire wr_done_int;
+ wire rd_done_int;
+ wire [6:0] rd_addr_final;
+ wire [1:0] which_ram_rd_final;
+
+ // USB side
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd0)) ram0[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd1)) ram1[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd2)) ram2[wr_addr] <= datain;
+
+ always @(posedge txclk)
+ if(WR & (which_ram_wr == 2'd3)) ram3[wr_addr] <= datain;
+
+ assign wr_done_int = ((WR && (wr_addr == 7'd127)) || WR_done);
+
+ always @(posedge txclk)
+ if(reset)
+ wr_addr <= 0;
+ else if (WR_done)
+ wr_addr <= 0;
+ else if (WR)
+ wr_addr <= wr_addr + 7'd1;
+
+ always @(posedge txclk)
+ if(reset)
+ which_ram_wr <= 0;
+ else if (wr_done_int)
+ which_ram_wr <= which_ram_wr + 2'd1;
+
+ assign have_space = (nb_packets < 3'd3);
+
+ // Reader side
+ // short hand fifo
+ // rd_addr_final is what rd_addr is going to be next clock cycle
+ // which_ram_rd_final is what which_ram_rd is going to be next clock
cycle
+ always @(posedge txclk) dataout0 <= ram0[rd_addr_final];
+ always @(posedge txclk) dataout1 <= ram1[rd_addr_final];
+ always @(posedge txclk) dataout2 <= ram2[rd_addr_final];
+ always @(posedge txclk) dataout3 <= ram3[rd_addr_final];
+
+ assign dataout = (which_ram_rd_final[1]) ?
+ (which_ram_rd_final[0] ?
dataout3 : dataout2) :
+ (which_ram_rd_final[0] ?
dataout1 : dataout0);
+
+ //RD_done is the only way to signal the end of one packet
+ assign rd_done_int = RD_done;
+
+ always @(posedge txclk)
+ if (reset)
+ rd_addr <= 0;
+ else if (RD_done)
+ rd_addr <= 0;
+ else if (RD) rd_addr <= rd_addr + 7'd1;
+
+ assign rd_addr_final = (reset|rd_done_int) ? (7'd0) :
+ ((RD)?(rd_addr+7'd1):rd_addr);
+ always @(posedge txclk)
+ if (reset)
+ which_ram_rd <= 0;
+ else if (rd_done_int)
+ which_ram_rd <= which_ram_rd + 2'd1;
+
+ assign which_ram_rd_final = (reset) ? (2'd0):
+ ((rd_done_int) ? (which_ram_rd + 2'd1) :
which_ram_rd);
+
+ //packet_waiting is set to zero if rd_done_int is high
+ //because there is no guarantee that nb_packets will be pos.
+ assign packet_waiting = (nb_packets != 0) & (~rd_done_int);
+ //assign packet_waiting = (nb_packets > 1) & ((nb_packets ==
1)&(~rd_done_int));
+ always @(posedge txclk)
+ if (reset)
+ nb_packets <= 0;
+ else if (wr_done_int & ~rd_done_int)
+ nb_packets <= nb_packets + 3'd1;
+ else if (rd_done_int & ~wr_done_int)
+ nb_packets <= nb_packets - 3'd1;
+
+endmodule
\ No newline at end of file
Added: gnuradio/branches/developers/zhuochen/simulations/burst_test/strobe_gen.v
===================================================================
--- gnuradio/branches/developers/zhuochen/simulations/burst_test/strobe_gen.v
(rev 0)
+++ gnuradio/branches/developers/zhuochen/simulations/burst_test/strobe_gen.v
2007-08-02 20:56:13 UTC (rev 6103)
@@ -0,0 +1,46 @@
+// -*- verilog -*-
+//
+// USRP - Universal Software Radio Peripheral
+//
+// Copyright (C) 2003 Matt Ettus
+//
+// This program is free software; you can redistribute it and/or modify
+// it under the terms of the GNU General Public License as published by
+// the Free Software Foundation; either version 2 of the License, or
+// (at your option) any later version.
+//
+// This program is distributed in the hope that it will be useful,
+// but WITHOUT ANY WARRANTY; without even the implied warranty of
+// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+// GNU General Public License for more details.
+//
+// You should have received a copy of the GNU General Public License
+// along with this program; if not, write to the Free Software
+// Foundation, Inc., 51 Franklin Street, Boston, MA 02110-1301 USA
+//
+
+
+
+module strobe_gen
+ ( input clock,
+ input reset,
+ input enable,
+ input [7:0] rate, // Rate should be 1 LESS THAN your desired divide ratio
+ input strobe_in,
+ output wire strobe );
+
+// parameter width = 8;
+
+ reg [7:0] counter;
+ assign strobe = ~|counter && enable && strobe_in;
+
+ always @(posedge clock)
+ if(reset | ~enable)
+ counter <= #1 8'd0;
+ else if(strobe_in)
+ if(counter == 0)
+ counter <= #1 rate;
+ else
+ counter <= #1 counter - 8'd1;
+
+endmodule // strobe_gen
Added:
gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v
===================================================================
---
gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v
(rev 0)
+++
gnuradio/branches/developers/zhuochen/simulations/burst_test/test_chan_fifo_reader.v
2007-08-02 20:56:13 UTC (rev 6103)
@@ -0,0 +1,136 @@
+module chan_fifo_readers_test();
+
+// Inputs
+reg reset;
+reg txclock;
+reg [31:0] datain;
+reg [31:0] ttime;
+reg WR;
+reg adcclock;
+reg debug;
+reg WR_done;
+wire [15:0] tx_q;
+wire [15:0] tx_i;
+wire underrun;
+
+reg [15:0] i ;
+
+// fifo inputs
+wire skip;
+wire rdreq;
+
+// fifo ouputs
+wire [31:0] fifodata;
+wire pkt_waiting;
+wire tx_strobe;
+wire tx_empty;
+
+chan_fifo_reader chan0 (
+ .reset(reset),
+ .tx_clock(txclock),
+ .adc_time(ttime),
+ .skip(skip),
+ .rdreq(rdreq),
+ .pkt_waiting(pkt_waiting),
+ .fifodata(fifodata),
+ //.debug(debug),
+ .tx_q(tx_q),
+ .tx_i(tx_i),
+ .underrun(underrun),
+ .samples_format(4'd0),
+ .tx_empty(tx_empty),
+ .tx_strobe(tx_strobe) );
+
+
+// Channel fifo
+ channel_ram tx_data_fifo
+ ( .reset(reset),
+ .txclk(txclock),
+ .datain(datain),
+ .WR(WR),
+ .have_space(),
+ .dataout(fifodata),
+ .packet_waiting(pkt_waiting),
+ .RD(rdreq),
+ .WR_done(WR_done),
+ .RD_done(skip)
+ );
+
+ strobe_gen strobe_generator(
+ .reset(reset),
+ .enable(1'b1),
+ .clock(txclock),
+ .strobe_in(1'b1),
+ .strobe(tx_strobe),
+ .rate(8'd3) );
+
+initial begin
+ // Setup the initial conditions
+ reset = 1;
+ adcclock = 0;
+ txclock = 0;
+ datain = 0;
+ WR = 0;
+ i = 0 ;
+ ttime = 0;
+ debug = 0;
+ WR_done = 0;
+
+ // Deassert the reset
+ #40 reset = 1'b0 ;
+
+ // Wait a few clocks
+ repeat (5) begin
+ @(posedge txclock)
+ reset = 1'b0 ;
+ end
+
+ send_packet(9'd128, 2'd2, 32'h0);
+ send_packet(9'd128, 2'd0, 32'hFFFFFFFF);
+ send_packet(9'd128, 2'd1, 32'hFFFFFFFF);
+ send_packet(9'd128, 2'd3, 32'hFFFFFFFF);
+
+
+ end
+
+always@(posedge adcclock) begin
+ ttime <= ttime + 1;
+end
+
+always
+ #5 txclock = ~txclock ;
+
+always
+ #6 adcclock = ~adcclock ;
+
+task send_packet;
+ input [8:0]length;
+ input [1:0] flag;
+ input [31:0] timestamp;
+ begin
+ repeat (length) begin
+ @(posedge txclock)
+ WR = 1;
+ if (i == 0) datain = {3'd0, flag, 18'd0, (4*length - 8)};
+ else if (i == 1) datain = timestamp;
+ else datain = i;//{16'hFFFF - i,i};
+ i = i + 1;
+ end
+
+ if (length < 128)
+ begin
+ @(posedge txclock)
+ WR_done = 1;
+ WR = 0;
+ @(posedge txclock)
+ WR_done = 0;
+ end
+ else
+ @(posedge txclock)
+ WR = 0;
+
+ i = 0;
+ end
+ endtask
+
+endmodule
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