[Commit-gnuradio] r5841 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-25 22:51:25 -0600 (Mon, 25 Jun 2007)
New Revision: 5841

Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
   gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
   gnuradio/branches/developers/matt/u2f/control_lib/ss_rcvr.v
Log:
 basically working serdes roundtrip, still need to debug odd-mode


Modified: gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-06-26 02:53:59 UTC (rev 5840)
+++ gnuradio/branches/developers/matt/u2f/control_lib/fifo_int.v        
2007-06-26 04:51:25 UTC (rev 5841)
@@ -54,7 +54,7 @@
    localparam WRITING = 3'd3;
    localparam ERROR = 3'd4;
 
-   reg [3:0]  state;
+   reg [2:0]  state;
    
    always @(posedge clk)
      if(rst)

Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-06-26 02:53:59 UTC (rev 5840)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v       
2007-06-26 04:51:25 UTC (rev 5841)
@@ -51,9 +51,10 @@
    localparam CRC_EVEN = 3'd3;
    localparam CRC_ODD = 3'd4;
    localparam ERROR = 3'd5;
+   localparam DONE = 3'd6;
    
-   reg [17:0] rxd_d1;
-   reg [31:0] line_serclk, line_serclk_d1, line_sysclk;
+   wire [17:0] rxd;
+   reg [31:0]  line;
    reg [15:0] halfline;
    reg               data_valid, phase;
    reg [7:0]  holder;
@@ -61,18 +62,18 @@
    wire       crc_pass;
 
    reg [2:0]  state;
+
+
+   ss_rcvr #(.WIDTH(18)) ss_rcvr
+     (.rxclk(ser_rx_clk),.sysclk(clk),.rst(rst),
+      .data_in({ser_rkmsb,ser_rklsb,ser_r}),.data_out(rxd),
+      .clock_present());
    
-   always @(posedge ser_rx_clk or posedge rst)
-     if(rst)
-       rxd_d1 <= 0;
-     else
-       rxd_d1 <= {ser_rkmsb,ser_rklsb,ser_r};
-
-   always @(posedge ser_rx_clk)
+   always @(posedge clk)
      if(phase == 1)
-       line_serclk = {rxd_d1[15:0], halfline};
+       line = {rxd[15:0], halfline};
               
-   always @(posedge ser_rx_clk or posedge rst)
+   always @(posedge clk)
      if(rst)
        begin
          state <= IDLE;
@@ -85,24 +86,24 @@
           begin
              data_valid <= 0;
              phase <= 0;
-             if(rxd_d1 == {2'b11,K_PKT_START,K_PKT_START})
+             if(rxd == {2'b11,K_PKT_START,K_PKT_START})
                state <= EVEN;
-             else if((rxd_d1[17:16]==2'b01) && (rxd_d1[7:0]==K_PKT_START))
+             else if((rxd[17:16]==2'b01) && (rxd[7:0]==K_PKT_START))
                begin
                   state <= ODD;
-                  holder <= rxd_d1[15:8];
+                  holder <= rxd[15:8];
                end
           end
         EVEN : 
-          case(rxd_d1[17:16])
+          case(rxd[17:16])
             2'b00 :
                begin  
                   data_valid <= 1;
                   phase <= ~phase;
-                  halfline <= rxd_d1[15:0];
+                  halfline <= rxd[15:0];
                end
             2'b11 :
-              if((rxd_d1[15:0] == {K_PKT_END,K_PKT_END}) & ~phase)
+              if((rxd[15:0] == {K_PKT_END,K_PKT_END}) & ~phase)
                 begin
                    state <= CRC_EVEN;
                    data_valid <= 0;
@@ -117,15 +118,15 @@
                  data_valid <= 0;
                  state <= ERROR;
               end
-          endcase // case(rxd_d1[17:16])
+          endcase // case(rxd[17:16])
         ODD :
-          if(~rxd_d1[16])
+          if(~rxd[16])
             begin
                data_valid <= 1;
                phase <= ~phase;
-               holder <= rxd_d1[15:8];
-               halfline <= {rxd_d1[7:0],holder};
-               if(rxd_d1[17:16]==2'b10)
+               holder <= rxd[15:8];
+               halfline <= {rxd[7:0],holder};
+               if(rxd[17:16]==2'b10)
                  state <= CRC_ODD;
                else
                  state <= ERROR;
@@ -133,7 +134,7 @@
           else
             state <= ERROR;
         CRC_EVEN :
-          if(rxd_d1[15:0] == CRC)
+          if(rxd[15:0] == CRC)
             state <= DONE;
           else
             state <= ERROR;
@@ -148,7 +149,7 @@
    reg [15:0] CRC;
    wire [15:0] nextCRC;
    
-   always @(posedge ser_rx_clk or posedge rst)
+   always @(posedge clk)
      if(rst)
        CRC <= 16'hFFFF;
      else if(state == IDLE)
@@ -159,8 +160,9 @@
    CRC16_D16 crc_blk(halfline,CRC,nextCRC);
    assign      crc_pass = ~|nextCRC;
 
+   assign      fifo_data_o = line;
+   assign      fifo_write_o = data_valid & ~phase;
    assign      fifo_error_o = (state == ERROR);
    assign      fifo_done_o = (state == DONE);
-   
 endmodule // serdes_rx
 

Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v       
2007-06-26 02:53:59 UTC (rev 5840)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v       
2007-06-26 04:51:25 UTC (rev 5841)
@@ -122,12 +122,14 @@
       $display("Done entering Data into RAM\n");
       repeat(10)
        @(posedge clk);
-      write_go_rx = 1;
+      write_go_rx <= 1;
+      $display("Send write_go");
       @(posedge clk);
-      write_go_rx = 0;
+      write_go_rx <= 0;
       repeat(30)
        @(posedge clk);
       read_go_tx = 1;
+      $display("Send read_go");
       @(posedge clk);
       read_go_tx = 0;
       
@@ -150,7 +152,7 @@
    
    always @(posedge clk)
      if(write_rx)
-       $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO EMPTY 
%d",data_rx, ready_rx, empty_rx);
+       $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO FULL %d",data_rx, 
ready_rx, full_rx);
    
    always @(posedge clk)
      if(read_tx)
@@ -161,6 +163,6 @@
       $dumpvars(0,serdes_tb);
    end
 
-   initial #10000000 $finish;
+   initial #1000000 $finish;
    
 endmodule // serdes_tb

Modified: gnuradio/branches/developers/matt/u2f/control_lib/ss_rcvr.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/ss_rcvr.v 2007-06-26 
02:53:59 UTC (rev 5840)
+++ gnuradio/branches/developers/matt/u2f/control_lib/ss_rcvr.v 2007-06-26 
04:51:25 UTC (rev 5841)
@@ -19,8 +19,8 @@
      input sysclk,
      input rst,
      
-     input [15:0] data_in,
-     output [15:0] data_out,
+     input [WIDTH-1:0] data_in,
+     output [WIDTH-1:0] data_out,
      output reg clock_present);
    
    wire [3:0] rd_addr, wr_addr;
@@ -56,7 +56,7 @@
    
    assign         wr_ctr_sys = 
{wr_addr_sys_d2[3],^wr_addr_sys_d2[3:2],^wr_addr_sys_d2[3:1],^wr_addr_sys_d2[3:0]};
    
-   assign         diff = wr_counter_sys - rd_counter;
+   assign         diff = wr_ctr_sys - rd_counter;
    assign         abs_diff = diff[3] ? (~diff+1) : diff;
    
    reg [3:0]      rd_counter;