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[Commit-gnuradio] r5836 - gnuradio/branches/developers/matt/u2f/control_
From: |
matt |
Subject: |
[Commit-gnuradio] r5836 - gnuradio/branches/developers/matt/u2f/control_lib |
Date: |
Mon, 25 Jun 2007 17:44:17 -0600 (MDT) |
Author: matt
Date: 2007-06-25 17:44:17 -0600 (Mon, 25 Jun 2007)
New Revision: 5836
Added:
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
Modified:
gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
Log:
testbench indicates that tx side is working.
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-06-25 22:47:44 UTC (rev 5835)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_rx.v
2007-06-25 23:44:17 UTC (rev 5836)
@@ -31,9 +31,11 @@
input ser_rkmsb,
output [31:0] fifo_data_o,
- output fifo_wr_o,
+ output fifo_write_o,
+ output fifo_done_o,
+ output fifo_error_o,
input fifo_ready_i,
- input fifo_done_i
+ input fifo_full_i
);
localparam COMMA = 8'b101_11100; // K28.5
@@ -43,34 +45,110 @@
localparam LOS = 8'b111_11111; // K31.7
localparam ERROR = 8'b000_00000; // K0.0
- assign ser_tx_clk = clk;
-
localparam IDLE = 3'd0;
localparam START = 3'd1;
- localparam RUN = 3'd2;
- localparam RESTART = 3'd3;
- localparam ON_ERROR = 3'd4;
+ localparam EVEN = 3'd2;
+ localparam ODD = 3'd3;
+ localparam CRC_EVEN = 3'd4;
+ localparam CRC_ODD = 3'd5;
+
+ reg [17:0] rxd_d1;
+ reg [31:0] line_serclk, line_serclk_d1, line_sysclk;
+ reg [15:0] halfline;
+ reg data_valid, phase;
+ reg [7:0] holder;
- reg [2:0] state, next_state;
+ wire crc_pass;
- reg [7:0] counter;
+ reg [2:0] state;
+
+ always @(posedge ser_rx_clk or posedge rst)
+ if(rst)
+ rxd_d1 <= 0;
+ else
+ rxd_d1 <= {ser_rkmsb,ser_rklsb,ser_r};
+
+ always @(posedge ser_rx_clk or posedge rst)
+ if(rst)
+ begin
+ state <= IDLE;
+ data_valid <= 0;
+ phase <= 0;
+ end
+ else
+ case(state)
+ IDLE :
+ begin
+ data_valid <= 0;
+ phase <= 0;
+ if(rxd_d1 == {2'b11,PKT_START,PKT_START})
+ state <= EVEN;
+ else if((rxd_d1[17:16]==2'b01) && (rxd_d1[7:0]==PKT_START))
+ begin
+ state <= ODD;
+ holder <= rxd_d1[15:8];
+ end
+ end
+ EVEN :
+ case(rxd_d1[17:16])
+ 2'b00 :
+ begin
+ data_valid <= 1;
+ phase <= ~phase;
+ halfline <= rxd_d1[15:0];
+ end
+ 2'b11 :
+ if((rxd_d1[15:0] == {PKT_END,PKT_END}) & phase)
+ begin
+ state <= CRC_EVEN;
+ data_valid <= 0;
+ end
+ else
+ begin
+ data_valid <= 0;
+ state <= ERROR;
+ end
+ default :
+ begin
+ data_valid <= 0;
+ state <= ERROR;
+ end
+ endcase // case(rxd_d1[17:16])
+ ODD :
+ if(~rxd_d1[16])
+ begin
+ data_valid <= 1;
+ phase <= ~phase;
+ holder <= rxd_d1[15:8];
+ halfline <= {rxd_d1[7:0],holder};
+ if(rxd_d1[17:16]==2'b10)
+ state <= CRC_ODD;
+ else
+ state <= ERROR;
+ end
+ else
+ state <= ERROR;
+ CRC_EVEN :
+ state <= IDLE;
+ CRC_ODD :
+ state <= IDLE;
+ ERROR :
+ state <= IDLE;
+ endcase // case(state)
- reg rcv_comma, rcv_comma_ret, rcv_error, rcv_error_ret;
-
- always @(posedge ser_rx_clk)
- rcv_comma <= (ser_rkmsb & (ser_r[15:8] == COMMA)) ||
- (ser_rklsb & (ser_r[7:0] == COMMA));
-
- always @(posedge clk)
- rcv_comma_ret <= rcv_comma;
+ reg [15:0] CRC;
+ wire [15:0] nextCRC;
- always @(posedge ser_rx_clk)
- rcv_error <= (ser_rkmsb & ser_rklsb & ((ser_r[7:0] == LOS)||(ser_r[7:0]
== ERROR)));
+ always @(posedge ser_rx_clk or posedge rst)
+ if(rst)
+ CRC <= 16'hFFFF;
+ else if(state == IDLE)
+ CRC <= 16'hFFFF;
+ else if(data_valid)
+ CRC <= nextCRC;
- always @(posedge clk)
- rcv_error_ret <= rcv_error;
-
- assign din = {counter,rcv_comma,state[2:0],ser_rkmsb,ser_rklsb,ser_r[15:0]};
+ CRC16_D16 crc_blk(halfline,CRC,nextCRC);
+ assign crc_pass = ~|nextCRC;
endmodule // serdes_rx
Added: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tb.v
2007-06-25 23:44:17 UTC (rev 5836)
@@ -0,0 +1,166 @@
+
+
+module serdes_tb();
+
+ reg clk, rst;
+ wire ser_rx_clk, ser_tx_clk;
+ wire ser_rklsb, ser_rkmsb, ser_tklsb, ser_tkmsb;
+ wire [15:0] ser_r, ser_t;
+
+ initial clk = 0;
+ initial rst = 1;
+ initial #1000 rst = 0;
+ always #100 clk = ~clk;
+
+ // Wishbone
+ reg [31:0] wb_dat_i;
+ wire [31:0] wb_dat_o_rx, wb_dat_o_tx;
+ reg wb_we, wb_en_rx, wb_en_tx;
+ reg [8:0] wb_adr;
+
+ // TX Side
+ wire en_tx, we_tx;
+ wire [8:0] addr_tx;
+ wire [31:0] f2r_tx, r2f_tx;
+ wire [31:0] data_tx;
+ wire read_tx, done_tx, error_tx, ready_tx, empty_tx;
+
+ reg [8:0] fl_tx, ll_tx;
+ reg read_go_tx, write_go_tx, clear_tx;
+ wire fdone_tx, ferror_tx;
+
+ serdes_tx serdes_tx
+ (.clk(clk),.rst(rst),
+
.ser_tx_clk(ser_tx_clk),.ser_t(ser_t),.ser_tklsb(ser_tklsb),.ser_tkmsb(ser_tkmsb),
+ .fifo_data_i(data_tx),.fifo_read_o(read_tx),.fifo_done_o(done_tx),
+ .fifo_error_o(error_tx),.fifo_ready_i(ready_tx),.fifo_empty_i(empty_tx)
+ );
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(9))
+
ram_tx(.clka(clk),.ena(wb_en_tx),.wea(wb_we),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_tx),
+
.clkb(clk),.enb(en_tx),.web(we_tx),.addrb(addr_tx),.dib(f2r_tx),.dob(r2f_tx));
+
+ fifo_int fifo_int_tx
+ (.clk(clk),.rst(rst),
+
.firstline(fl_tx),.lastline(ll_tx),.step(1),.read_go(read_go_tx),.write_go(write_go_tx),
+ .clear(clear_tx),.done(fdone_tx),.error(ferror_tx),
+
+
.en_o(en_tx),.we_o(we_tx),.addr_o(addr_tx),.dat_to_buf(f2r_tx),.dat_from_buf(r2f_tx),
+
+ .wr_dat_i(0),.wr_write_i(0),.wr_done_i(0),
+ .wr_error_i(0),.wr_ready_o(),.wr_full_o(),
+
+ .rd_dat_o(data_tx),.rd_read_i(read_tx),.rd_done_i(done_tx),
+ .rd_error_i(error_tx),.rd_ready_o(ready_tx),.rd_empty_o(empty_tx)
+ );
+
+
+ // RX Side
+ wire en_rx, we_rx;
+ wire [8:0] addr_rx;
+ wire [31:0] f2r_rx, r2f_rx;
+ wire [31:0] data_rx;
+ wire write_rx, done_rx, error_rx, ready_rx, empty_rx;
+
+ reg [8:0] fl_rx, ll_rx;
+ reg read_go_rx, write_go_rx, clear_rx;
+ wire fdone_rx, ferror_rx;
+
+ serdes_rx serdes_rx
+ (.clk(clk),.rst(rst),
+
.ser_rx_clk(ser_rx_clk),.ser_r(ser_r),.ser_rklsb(ser_rklsb),.ser_rkmsb(ser_rkmsb),
+ .fifo_data_o(data_rx),.fifo_write_o(write_rx),.fifo_done_o(done_rx),
+ .fifo_error_o(error_rx),.fifo_ready_i(ready_rx),.fifo_full_i(full_rx)
+ );
+
+ ram_2port #(.DWIDTH(32),.AWIDTH(9))
+
ram_rx(.clka(clk),.ena(wb_en_rx),.wea(wb_we),.addra(wb_adr),.dia(wb_dat_i),.doa(wb_dat_o_rx),
+
.clkb(clk),.enb(en_rx),.web(we_rx),.addrb(addr_rx),.dib(f2r_rx),.dob(r2f_rx));
+
+ fifo_int fifo_int_rx
+ (.clk(clk),.rst(rst),
+
.firstline(fl_rx),.lastline(ll_rx),.step(1),.read_go(read_go_rx),.write_go(write_go_rx),
+ .clear(clear_rx),.done(fdone_rx),.error(ferror_rx),
+
+
.en_o(en_rx),.we_o(we_rx),.addr_o(addr_rx),.dat_to_buf(f2r_rx),.dat_from_buf(r2f_rx),
+
+ .wr_dat_i(data_rx),.wr_write_i(write_rx),.wr_done_i(done_rx),
+ .wr_error_i(error_rx),.wr_ready_o(ready_rx),.wr_full_o(full_rx),
+
+ .rd_dat_o(),.rd_read_i(0),.rd_done_i(0),
+ .rd_error_i(0),.rd_ready_o(),.rd_empty_o()
+ );
+
+ // Simulate the connection
+ assign ser_rx_clk = ser_tx_clk;
+ assign ser_rkmsb = ser_tkmsb;
+ assign ser_rklsb = ser_tklsb;
+ assign ser_r = ser_t;
+
+ // Fill the ram
+ initial wb_en_rx <= 0;
+
+ initial begin
+ wb_adr <= 0;
+ wb_en_tx <=0;
+ wb_we <= 0;
+ wb_dat_i <= 32'hab200c00;
+ @(negedge rst);
+ @(posedge clk);
+
+ repeat(511) begin
+ @(posedge clk);
+ wb_we <= 1;
+ wb_en_tx <= 1;
+ @(posedge clk);
+ wb_we <= 0;
+ wb_en_tx <= 0;
+ @(posedge clk);
+ wb_dat_i <= wb_dat_i + 32'h00010001;
+ wb_adr <= wb_adr + 1;
+ end // repeat (511)
+ $display("Done entering Data into RAM\n");
+ repeat(10)
+ @(posedge clk);
+ write_go_rx = 1;
+ @(posedge clk);
+ write_go_rx = 0;
+ repeat(30)
+ @(posedge clk);
+ read_go_tx = 1;
+ @(posedge clk);
+ read_go_tx = 0;
+
+
+ end // initial begin
+
+ initial begin
+ fl_tx = 0;
+ fl_rx = 0;
+ ll_tx = 100;
+ ll_rx = 100;
+ clear_tx = 0;
+ clear_rx = 0;
+ read_go_tx = 0;
+ write_go_tx = 0;
+ read_go_rx = 0;
+ write_go_rx = 0;
+ end
+
+
+ always @(posedge clk)
+ if(write_rx)
+ $display("SERDES RX, FIFO WRITE %x, FIFO RDY %d, FIFO EMPTY
%d",data_rx, ready_rx, empty_rx);
+
+ always @(posedge clk)
+ if(read_tx)
+ $display("SERDES TX, FIFO READ %x, FIFO RDY %d, FIFO EMPTY %d",data_tx,
ready_tx, empty_tx);
+
+ initial begin
+ $dumpfile("serdes_tb.vcd");
+ $dumpvars(0,serdes_tb);
+ end
+
+ initial #10000000 $finish;
+
+endmodule // serdes_tb
Modified: gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
2007-06-25 22:47:44 UTC (rev 5835)
+++ gnuradio/branches/developers/matt/u2f/control_lib/serdes_tx.v
2007-06-25 23:44:17 UTC (rev 5836)
@@ -39,11 +39,11 @@
input fifo_empty_i
);
- localparam COMMA = 8'b101_11100; // K28.5
- localparam PKT_START = 8'b110_11100; // K28.6
- localparam PKT_END = 8'b100_11100; // K28.4
- localparam LOS = 8'b111_11111; // K31.7
- localparam ERROR = 8'b000_00000; // K0.0
+ localparam COMMA = 8'b101_11100; // 0xBC K28.5
+ localparam PKT_START = 8'b110_11100; // 0xDC K28.6
+ localparam PKT_END = 8'b100_11100; // 0x9C K28.4
+ localparam LOS = 8'b111_11111; // 0xFF K31.7
+ localparam ERROR = 8'b000_00000; // 0x00 K0.0
assign ser_tx_clk = clk;
@@ -56,11 +56,12 @@
localparam SENDCRC = 3'd6;
reg [2:0] state, next_state;
- wire [15:0] crc_out;
// FIXME Implement sending of flow control
// FIXME Send CRC
// DONE Add idles if data not ready yet
+
+ reg [15:0] second_word;
always @(posedge clk)
if(rst)
@@ -85,10 +86,11 @@
begin
{ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_i[15:0]};
state <= RUN2;
+ second_word <= fifo_data_i[31:16];
end
RUN2 :
begin
- {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,fifo_data_i[31:16]};
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,second_word};
if(fifo_empty_i)
state <= DONE;
else if(fifo_ready_i)
@@ -109,14 +111,14 @@
end
SENDCRC :
begin
- {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,crc_out};
+ {ser_tkmsb,ser_tklsb,ser_t} <= {2'b00,CRC};
state <= IDLE;
end
default
state <= IDLE;
endcase // case(state)
- assign fifo_read_o = ((state == RUN2) & ~fifo_empty_i);
+ assign fifo_read_o = ((state == RUN1) & ~fifo_empty_i);
assign fifo_done_o = 1'b0; // Unused -- we always send everything we're
given
assign fifo_error_o = 1'b0; // Unused -- there should never be any errors
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