[Commit-gnuradio] r5809 - gnuradio/branches/developers/matt/u2f/control_lib

[matt]

Author: matt
Date: 2007-06-21 14:41:01 -0600 (Thu, 21 Jun 2007)
New Revision: 5809

Added:
   gnuradio/branches/developers/matt/u2f/control_lib/mux4.v
   gnuradio/branches/developers/matt/u2f/control_lib/mux8.v
Modified:
   gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
Log:
more progress on buffer pool -- now does crossbar.  kills icarus though


Modified: gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-21 20:38:57 UTC (rev 5808)
+++ gnuradio/branches/developers/matt/u2f/control_lib/buffer_pool.v     
2007-06-21 20:41:01 UTC (rev 5809)
@@ -112,9 +112,24 @@
              .rd_ready_o(rd_ready_o[i]),
              .rd_empty_o(rd_empty_o[i]) 
              );
-       end
+          mux4 #(.WIDTH(32)) 
+            mux4_dat_i (.sel(write_port[i]),.i0(wr0_dat_i),.i1(wr1_dat_i),
+                        .i2(wr2_dat_i),.i3(wr3_dat_i),.o(wr_dat_i[i]));
+          mux4 #(.WIDTH(1)) 
+            mux4_write_i 
(.sel(write_port[i]),.i0(wr0_write_i),.i1(wr1_write_i),
+                          .i2(wr2_write_i),.i3(wr3_write_i),.o(wr_write_i[i]));
+          mux4 #(.WIDTH(1)) 
+            mux4_wrdone_i (.sel(write_port[i]),.i0(wr0_done_i),.i1(wr1_done_i),
+                           .i2(wr2_done_i),.i3(wr3_done_i),.o(wr_done_i[i]));
+          mux4 #(.WIDTH(1)) 
+            mux4_rddone_i (.sel(read_port[i]),.i0(rd0_done_i),.i1(rd1_done_i),
+                           .i2(rd2_done_i),.i3(rd3_done_i),.o(rd_done_i[i]));
+          mux4 #(.WIDTH(1)) 
+            mux4_read_i (.sel(read_port[i]),.i0(rd0_read_i),.i1(rd1_read_i),
+                         .i2(rd2_read_i),.i3(rd3_read_i),.o(rd_read_i[i]));
+       end // block: gen_buffer
    endgenerate
-
+   
    // Wishbone Outputs
    always @*
      wb_dat_o <= buf_doa[which_buf];
@@ -129,5 +144,132 @@
    assign wb_err_o = 1'b0;  // Unused for now
    assign wb_rty_o = 1'b0;  // Unused for now
 
+   // FIFO interface outputs
+   integer   j,k;
+
+   // Read FIFO Outputs
+   reg [2:0] wr_src[0:3];
+   always @(posedge stream_clk)
+     if(stream_rst)
+       for(k=0;k<4;k=k+1)
+        wr_src[k] <= 0;
+     else
+       for(k=0;k<4;k=k+1)
+        for(j=0;j<8;j=j+1)
+          if(changed[j] & write_go[j] & (write_port[j]==k))
+            wr_src[k] <= j;
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_ready0(.sel(wr_src[0]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+                   .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
+                   .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), 
.i7(wr_ready_o[7]),.o(wr0_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_full0(.sel(wr_src[0]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+                  .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
+                  .i5(wr_full_o[5]), .i6(wr_full_o[6]), 
.i7(wr_full_o[7]),.o(wr0_full_o));
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_ready1(.sel(wr_src[1]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+                   .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
+                   .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), 
.i7(wr_ready_o[7]),.o(wr1_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_full1(.sel(wr_src[1]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+                  .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
+                  .i5(wr_full_o[5]), .i6(wr_full_o[6]), 
.i7(wr_full_o[7]),.o(wr1_full_o));
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_ready2(.sel(wr_src[2]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+                   .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
+                   .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), 
.i7(wr_ready_o[7]),.o(wr2_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_full2(.sel(wr_src[2]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+                  .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
+                  .i5(wr_full_o[5]), .i6(wr_full_o[6]), 
.i7(wr_full_o[7]),.o(wr2_full_o));
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_ready3(.sel(wr_src[3]), .i0(wr_ready_o[0]), .i1(wr_ready_o[1]),
+                   .i2(wr_ready_o[2]), .i3(wr_ready_o[3]), .i4(wr_ready_o[4]),
+                   .i5(wr_ready_o[5]), .i6(wr_ready_o[6]), 
.i7(wr_ready_o[7]),.o(wr3_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_wr_full3(.sel(wr_src[3]), .i0(wr_full_o[0]), .i1(wr_full_o[1]),
+                  .i2(wr_full_o[2]), .i3(wr_full_o[3]), .i4(wr_full_o[4]),
+                  .i5(wr_full_o[5]), .i6(wr_full_o[6]), 
.i7(wr_full_o[7]),.o(wr3_full_o));
+   
+   // Read FIFO Outputs
+   reg [2:0] rd_src[0:3];
+   always @(posedge stream_clk)
+     if(stream_rst)
+       for(k=0;k<4;k=k+1)
+        rd_src[k] <= 0;
+     else
+       for(k=0;k<4;k=k+1)
+        for(j=0;j<8;j=j+1)
+          if(changed[j] & read_go[j] & (read_port[j]==k))
+            rd_src[k] <= j;
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_ready0(.sel(rd_src[0]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
+                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd0_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_empty0(.sel(rd_src[0]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
+                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd0_empty_o));
+
+   mux8 #(.WIDTH(32))
+     mux8_rd_dat_0 (.sel(rd_src[0]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+                   .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
+                   .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd0_dat_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_ready1(.sel(rd_src[1]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
+                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd1_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_empty1(.sel(rd_src[1]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
+                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd1_empty_o));
+
+   mux8 #(.WIDTH(32))
+     mux8_rd_dat_1 (.sel(rd_src[1]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+                   .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
+                   .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd1_dat_o));
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_ready2(.sel(rd_src[2]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
+                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd2_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_empty2(.sel(rd_src[2]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
+                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd2_empty_o));
+
+   mux8 #(.WIDTH(32))
+     mux8_rd_dat_2 (.sel(rd_src[2]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+                   .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
+                   .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd2_dat_o));
+   
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_ready3(.sel(rd_src[3]), .i0(rd_ready_o[0]), .i1(rd_ready_o[1]),
+                   .i2(rd_ready_o[2]), .i3(rd_ready_o[3]), .i4(rd_ready_o[4]),
+                   .i5(rd_ready_o[5]), .i6(rd_ready_o[6]), 
.i7(rd_ready_o[7]),.o(rd3_ready_o));
+
+   mux8 #(.WIDTH(1)) 
+     mux8_rd_empty3(.sel(rd_src[3]), .i0(rd_empty_o[0]), .i1(rd_empty_o[1]),
+                   .i2(rd_empty_o[2]), .i3(rd_empty_o[3]), .i4(rd_empty_o[4]),
+                   .i5(rd_empty_o[5]), .i6(rd_empty_o[6]), 
.i7(rd_empty_o[7]),.o(rd3_empty_o));
+
+   mux8 #(.WIDTH(32))
+     mux8_rd_dat_3 (.sel(rd_src[3]), .i0(rd_dat_o[0]), .i1(rd_dat_o[1]),
+                   .i2(rd_dat_o[2]), .i3(rd_dat_o[3]), .i4(rd_dat_o[4]),
+                   .i5(rd_dat_o[5]), .i6(rd_dat_o[6]), 
.i7(rd_dat_o[7]),.o(rd3_dat_o));
+
 endmodule // buffer_pool
 

Added: gnuradio/branches/developers/matt/u2f/control_lib/mux4.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/mux4.v                    
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/mux4.v    2007-06-21 
20:41:01 UTC (rev 5809)
@@ -0,0 +1,14 @@
+
+
+module mux4
+  #(parameter WIDTH=32)
+    (input [1:0] sel,
+     input [WIDTH-1:0] i0,
+     input [WIDTH-1:0] i1,
+     input [WIDTH-1:0] i2,
+     input [WIDTH-1:0] i3,
+     output [WIDTH-1:0] o);
+
+   assign              o = sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0);
+   
+endmodule // mux4

Added: gnuradio/branches/developers/matt/u2f/control_lib/mux8.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/mux8.v                    
        (rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/mux8.v    2007-06-21 
20:41:01 UTC (rev 5809)
@@ -0,0 +1,19 @@
+
+
+module mux8
+  #(parameter WIDTH=32)
+    (input [2:0] sel,
+     input [WIDTH-1:0] i0,
+     input [WIDTH-1:0] i1,
+     input [WIDTH-1:0] i2,
+     input [WIDTH-1:0] i3,
+     input [WIDTH-1:0] i4,
+     input [WIDTH-1:0] i5,
+     input [WIDTH-1:0] i6,
+     input [WIDTH-1:0] i7,
+     output [WIDTH-1:0] o);
+
+   assign              o = sel[2] ? (sel[1] ? (sel[0] ? i7 : i6) : (sel[0] ? 
i5 : i4)) :
+                       (sel[1] ? (sel[0] ? i3 : i2) : (sel[0] ? i1 : i0));
+   
+endmodule // mux8