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[Commit-gnuradio] r5757 - in gnuradio/branches/developers/matt/u2f: cont
From: |
matt |
Subject: |
[Commit-gnuradio] r5757 - in gnuradio/branches/developers/matt/u2f: control_lib sdr_lib |
Date: |
Sun, 10 Jun 2007 01:59:48 -0600 (MDT) |
Author: matt
Date: 2007-06-10 01:59:48 -0600 (Sun, 10 Jun 2007)
New Revision: 5757
Added:
gnuradio/branches/developers/matt/u2f/control_lib/shortfifo.v
Modified:
gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
Log:
added shortfifo to allow TX and RX to continue while the processor is switching
fifos
Added: gnuradio/branches/developers/matt/u2f/control_lib/shortfifo.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/control_lib/shortfifo.v
(rev 0)
+++ gnuradio/branches/developers/matt/u2f/control_lib/shortfifo.v
2007-06-10 07:59:48 UTC (rev 5757)
@@ -0,0 +1,43 @@
+
+module shortfifo
+ (input clk, input rst,
+ input [31:0] datain,
+ output [31:0] dataout,
+ input read,
+ input write,
+ output full,
+ output reg empty);
+
+ reg [3:0] a;
+ genvar i;
+
+ generate
+ for (i=0;i<32;i++)
+ begin : gen_srl16
+ srl16e
+ srl16e(.Q(dataout[i]),
+ .A0(a[0]),.A1(a[1]),.A2(a[2]),.A3(a[3]),
+ .CE(write),.CLK(clk).,D(datain[i]));
+ end
+ endgenerate
+
+ always @(posedge clk)
+ if(rst)
+ begin
+ a <= 0;
+ empty <= 1;
+ end
+ else if(read & ~write)
+ if(a==0)
+ empty <= 1;
+ else
+ a <= a - 1;
+ else if(write & ~read)
+ begin
+ a <= a + 1;
+ empty <= 0;
+ end
+
+ assign full = (a == 15);
+
+endmodule // shortfifo
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-06-10
05:35:44 UTC (rev 5756)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_rx.v 2007-06-10
07:59:48 UTC (rev 5757)
@@ -17,6 +17,18 @@
wire [31:0] phase_inc;
reg [31:0] phase;
+ setting_reg #(.my_addr(1))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(phase_inc),.changed());
+
+ setting_reg #(.my_addr(2))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out({scale_i,scale_q}),.changed());
+
+ setting_reg #(.my_addr(3))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(decim_rate),.changed());
+
always @(posedge clk)
if(rst)
phase <= 0;
@@ -25,6 +37,9 @@
wire [23:0] i_bb, q_bb;
+ strobe_gen (.clock(clk),.reset(rst),.enable(1'b1),.rate(decim_rate),
+ .strobe_in(1),.strobe(stb_decim) );
+
cordic #(.bitwidth(24))
cordic(.clock(clk), .reset(rst), .enable(1'b1),
.xi({adc_a,10'b0}),. yi({adc_b,10'b0}), .zi(phase[31:16]),
@@ -32,14 +47,24 @@
cic_decim #(.bw(24))
decim_i (.clock(clk),.reset(rst),.enable(1'b1),
- .rate(),.strobe_in(1'b1),.strobe_out(decim_strobe),
- .signal_in(),.signal_out());
+ .rate(decim_rate),.strobe_in(1'b1),.strobe_out(stb_decim),
+ .signal_in(i_bb),.signal_out(i_decim));
- cic_decim_shifter #(.bw_in(),.bw_out())
- cds_i (.clock(clk),.reset(rst),.enable(1),.sig_in(),.sig_out());
-
+ cic_decim #(.bw(24))
+ decim_q (.clock(clk),.reset(rst),.enable(1'b1),
+ .rate(decim_rate),.strobe_in(1'b1),.strobe_out(stb_decim),
+ .signal_in(q_bb),.signal_out(q_decim));
+
MULT18X18S mult_i
(.P(prod_i),.A({{2{da[15]}},da} ),.B({{2{scale_i[15]}},scale_i}),
.C(dsp_clk),.CE(1'b1),.R(dsp_rst) );
+
+ assign rx_done_o = 0;
+ assign rx_write_o = rx_ready_i & ~empty;
+ assign overrun = full & stb_decim;
+ shortfifo rxshortfifo
+ (.clk(clk),.rst(rst),.datain({i_decim,q_decim}),.dataout(rx_dat_o),
+ .read(rx_write_o),.write(stb_decim & ~full),.full(full),.empty(empty));
+
endmodule // dsp_core_rx
Modified: gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v
===================================================================
--- gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-06-10
05:35:44 UTC (rev 5756)
+++ gnuradio/branches/developers/matt/u2f/sdr_lib/dsp_core_tx.v 2007-06-10
07:59:48 UTC (rev 5757)
@@ -1,49 +1,53 @@
-module dsp_core
- (input wb_clk_i,
- input wb_rst_i,
- input wb_stb_i,
- input wb_we_i,
- input [15:0] wb_adr_i,
- input [3:0] wb_sel_i,
- input [31:0] wb_dat_i,
- output [31:0] wb_dat_o,
- output wb_ack_o,
+module dsp_core_tx
+ (input clk, input rst,
+ input set_stb, input [7:0] set_addr, input [31:0] set_data,
+
+ output [15:0] dac_a
+ output [13:0] dac_b,
- input dsp_clk,
- input dsp_rst,
- input [13:0] adc_a,
- input adc_ovf_a,
- input [13:0] adc_b,
- input adc_ovf_b,
- output reg [15:0] dac_a,
- output reg [15:0] dac_b
+ input [31:0] tx_dat_i,
+ output tx_read_o,
+ output tx_done_o,
+ input tx_ready_i,
+ input tx_empty_i
);
- assign wb_dat_o = 32'd0; // No readback for now
+ wire [15:0] i, q, scale_i, scale_q;
+ wire [31:0] phase_inc;
+ reg [31:0] phase;
+ wire [7:0] interp_rate;
+ wire stb_interp;
+
+ //setting_reg #(.my_addr(0))
+ // (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ // .in(set_data),.out({i,q}),.changed());
+
+ setting_reg #(.my_addr(1))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(phase_inc),.changed());
+
+ setting_reg #(.my_addr(2))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out({scale_i,scale_q}),.changed());
+
+ setting_reg #(.my_addr(3))
+ (.clk(clk),.rst(rst),.strobe(set_stb),.addr(set_addr),
+ .in(set_data),.out(interp_rate),.changed());
- wire [15:0] i, q, scale_i, scale_q;
- wire [31:0] phase_inc;
- reg [31:0] phase;
+ assign tx_done_o = 0;
+ assign tx_read_o = tx_ready_i & ~full;
+ assign underrun = empty & stb_interp;
- wb_regfile_2clock
- regs (.wb_clk_i(wb_clk_i),.wb_rst_i(wb_rst_i),
- .wb_stb_i(wb_stb_i),.wb_we_i(wb_we_i),
- .wb_adr_i(wb_adr_i),.wb_dat_i(wb_dat_i),
- .wb_sel_i(wb_sel_i),.wb_ack_o(wb_ack_o),
- .alt_clk(dsp_clk),.alt_rst(dsp_rst),
- .reg00({i,q}),
- .reg01(phase_inc),
- .reg02({scale_i,scale_q}),
- .reg03(),
- .reg04(),
- .reg05(),
- .reg06(),
- .reg07()
- );
+ shortfifo txshortfifo
+ (.clk(clk),.rst(rst),.datain(tx_dat_i),.dataout({i,q}),
+ .read(stb_interp & ~empty),.write(tx_read_o),.full(full),.empty(empty));
- always @(posedge dsp_clk)
- if(dsp_rst)
+ strobe_gen (.clock(clk),.reset(rst),.enable(1'b1),.rate(interp_rate),
+ .strobe_in(1),.strobe(stb_interp) );
+
+ always @(posedge clk)
+ if(rst)
phase <= 0;
else
phase <= phase + phase_inc;
@@ -51,50 +55,45 @@
wire signed [15:0] da, db;
reg signed [15:0] dar, dbr;
- cordic cordic(.clock(dsp_clk),
- .reset(dsp_rst),
- .enable(1'b1),
- .xi(i),.yi(q),.zi(phase[31:16]),
- .xo(da),.yo(db),.zo() );
+ wire signed [35:0] prod_i, prod_q;
- wire signed [35:0] prod_i, prod_q;
-/* MULT18X18S MULT18X18S_inst (
- .P(prod_i), // 36-bit multiplier output
+ cic_interp #(parameter bw = 16, parameter N = 4, parameter
log2_of_max_rate = 7)
+ cic_interp_i(.clock(clk),.reset(rst),.enable(1),.rate(interp_rate),
+ .strobe_in(stb_interp),.strobe_out(1),
+ .signal_in(i),.signal_out(i_interp));
+
+ cic_interp #(parameter bw = 16, parameter N = 4, parameter
log2_of_max_rate = 7)
+ cic_interp_q(.clock(clk),.reset(rst),.enable(1),.rate(interp_rate),
+ .strobe_in(stb_interp),.strobe_out(1),
+ .signal_in(q),.signal_out(q_interp));
+
+ cordic #(.bitwidth(16),.zwidth(16))
+ cordic(.clock(clk), .reset(rst), .enable(1'b1),
+ .xi(i_interp),.yi(q_interp),.zi(phase[31:16]),
+ .xo(da),.yo(db),.zo() );
+
+ MULT18X18S MULT18X18S_inst
+ (.P(prod_i), // 36-bit multiplier output
.A({{2{da[15]}},da} ), // 18-bit multiplier input
.B({{2{scale_i[15]}},scale_i}), // 18-bit multiplier input
- .C(dsp_clk), // Clock input
+ .C(clk), // Clock input
.CE(1'b1), // Clock enable input
- .R(dsp_rst) // Synchronous reset input
- );
-MULT18X18S MULT18X18S_inst_2 (
- .P(prod_q), // 36-bit multiplier output
+ .R(rst) // Synchronous reset input
+ );
+
+ MULT18X18S MULT18X18S_inst_2
+ (.P(prod_q), // 36-bit multiplier output
.A({{2{db[15]}},da} ), // 18-bit multiplier input
.B({{2{scale_q[15]}},scale_q}), // 18-bit multiplier input
- .C(dsp_clk), // Clock input
+ .C(clk), // Clock input
.CE(1'b1), // Clock enable input
- .R(dsp_rst) // Synchronous reset input
- );
- */
- /*
- reg signed [35:0] prod_i, prod_q;
-
- always @(posedge dsp_clk)
- if(dsp_rst)
- prod_i <= 36'sd0;
- else
- prod_i <= {{2{da[15]}},da} * {{2{scale_i[15]}},scale_i};
-
- always @(posedge dsp_clk)
- if(dsp_rst)
- prod_q <= 36'sd0;
- else
- prod_q <= {{2{db[15]}},db} * {{2{scale_q[15]}},scale_q};
-*/
-
- always @(posedge dsp_clk)
+ .R(rst) // Synchronous reset input
+ );
+
+ always @(posedge clk)
dac_a <= prod_i[23:8];
- always @(posedge dsp_clk)
+ always @(posedge clk)
dac_b <= prod_q[23:8];
endmodule // dsp_core
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